coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: Add support for PSP NVRAM base addr and size
by Bao Zheng (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Paul Menzel, Fred Reitberger, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67137 ) Change subject: Add support for PSP NVRAM base addr and size ...................................................................... Patch Set 5: (1 comment) File util/amdfwtool/amdfwtool.h: https://review.coreboot.org/c/coreboot/+/67137/comment/8e9cd44b_30febaa7 PS4, Line 279: uint64_t dest; : size_t size; > yes, as when filename does not exist then dest addr and size will be updated in psp dir for PSP_NVRA […] But this amd_fw_entry is for legacy XHCI,IMC firmware, not for PSP FW. -- To view, visit https://review.coreboot.org/c/coreboot/+/67137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Gerrit-Change-Number: 67137 Gerrit-PatchSet: 5 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Sep 2022 11:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
by Simon Yang (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tim Wawrzynczak, Vidya Gopalakrishnan, Sumeet R Pawnikar, Paul Fagerburg. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67374 ) Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/67374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270 Gerrit-Change-Number: 67374 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 10:42:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
by Nico Huber (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Martin L Roth, Jakub Czapiga, Arthur Heymans, Patrick Rudolph, Elyes Haouas. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62181 ) Change subject: device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4} ...................................................................... Patch Set 8: (1 comment) File src/include/device/dram/ddr4.h: https://review.coreboot.org/c/coreboot/+/62181/comment/06ccbbd1_281b520f PS7, Line 29: SPD_DDR4_DIMM_TYPE_EXTENDED = 0x0, > SPD_DDR2_DIMM_TYPE_MASK is used here : src/device/dram/ddr2.c […] Yeah, let's postpone this. Using register values in an internal API isn't a good design choice, but that's how things are right now. But maybe move this entry to the other enum. So we are reminded that there is more to it. -- To view, visit https://review.coreboot.org/c/coreboot/+/62181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621 Gerrit-Change-Number: 62181 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 06 Sep 2022 10:13:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: allocator_v4: Disable top-down mode by default
by Felix Held (Code Review) 06 Sep '22

06 Sep '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67328 ) Change subject: allocator_v4: Disable top-down mode by default ...................................................................... allocator_v4: Disable top-down mode by default The top-down allocation feature was merged prematurely before platforms that don't report their resources correctly were fixed. Let's turn it off by default. Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67328 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M src/device/Kconfig 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Christian Walter: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index af9beb3..b9284cb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -935,8 +935,11 @@ config RESOURCE_ALLOCATION_TOP_DOWN bool "Allocate resources from top down" - default y + default n depends on RESOURCE_ALLOCATOR_V4 + help + Should be the default, but many platforms don't report resources + correctly. Hence, the allocator might cause conflicts. config XHCI_UTILS def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/67328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Gerrit-Change-Number: 67328 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: tests: Add support for tests build failures detection
by Jakub Czapiga (Code Review) 06 Sep '22

06 Sep '22

Jakub Czapiga has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/67372 ) Change subject: tests: Add support for tests build failures detection ...................................................................... tests: Add support for tests build failures detection This patch introduces new target: junit.xml-unit-tests, which builds and runs unit-tests. It also creates build log containing build logs. This feature allows for one to see build failures in Jenkins dashboard. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe --- M payloads/libpayload/tests/Makefile.inc M tests/Makefile.inc M util/testing/Makefile.inc 3 files changed, 101 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/67372/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe Gerrit-Change-Number: 67372 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: device/pci_device: Add missing spaces to log messages
by Elyes Haouas (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Paul Menzel. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67370 ) Change subject: device/pci_device: Add missing spaces to log messages ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If933d8fb0db5b58ff12f043cc73172a3f6ffc624 Gerrit-Change-Number: 67370 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 09:25:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/variants/shotzo: Turn off LAN power in S0ix
by build bot (Jenkins) (Code Review) 06 Sep '22

06 Sep '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67373 ) Change subject: mb/google/dedede/variants/shotzo: Turn off LAN power in S0ix ...................................................................... Patch Set 1: (41 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/4b58e475_955ba703 PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/mainboard/google/dedede/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/340f4eb5_ef5448c3 PS1, Line 69: acpigen_write_if_lequal_op_int(ARG0_OP, 1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/c76028ef_8dcb3a5d PS1, Line 69: acpigen_write_if_lequal_op_int(ARG0_OP, 1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/8e345c95_6581462c PS1, Line 70: { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/07ab26e4_697a78f9 PS1, Line 70: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/09b2a87c_0161164e PS1, Line 71: variant_generate_s0ix_hook(S0IX_ENTRY); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/f547fa7a_af3278d4 PS1, Line 71: variant_generate_s0ix_hook(S0IX_ENTRY); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/e72ca72a_683969e9 PS1, Line 72: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/06ae0766_f1104bab PS1, Line 72: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/83dd2117_66033e6c PS1, Line 73: acpigen_write_else(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/96874e00_d543546d PS1, Line 73: acpigen_write_else(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/31e23b34_7abe7332 PS1, Line 74: { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/c45b08c8_36c4f435 PS1, Line 74: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/5f747677_5c5bbc32 PS1, Line 75: variant_generate_s0ix_hook(S0IX_EXIT); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/599e5ddc_61c1a270 PS1, Line 75: variant_generate_s0ix_hook(S0IX_EXIT); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/41672efe_6d2df5b0 PS1, Line 76: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/73d5d869_9f7ab5cd PS1, Line 76: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/d661854e_0eeb4ea2 PS1, Line 77: acpigen_write_if_end(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/02791937_3ee2fe0d PS1, Line 77: acpigen_write_if_end(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/35b71547_68a42b6c PS1, Line 83: acpigen_write_scope("\\_SB"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/542ca2c0_57629929 PS1, Line 83: acpigen_write_scope("\\_SB"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/0a56e2e9_b057280f PS1, Line 84: acpigen_write_method_serialized("MS0X", 1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/9d88bef4_5d95ccb3 PS1, Line 84: acpigen_write_method_serialized("MS0X", 1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/d1a7c5ac_86c94f1b PS1, Line 85: mainboard_generate_s0ix_hook(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/328c6bbf_ac3c9235 PS1, Line 85: mainboard_generate_s0ix_hook(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/cb98cf83_c1b789b7 PS1, Line 86: acpigen_write_method_end(); /* Method */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/b3bdbd47_2835d1b5 PS1, Line 86: acpigen_write_method_end(); /* Method */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/c77f0f3a_b4bb5b82 PS1, Line 87: acpigen_write_scope_end(); /* Scope */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/75983c4d_82ccceb4 PS1, Line 87: acpigen_write_scope_end(); /* Scope */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/b4817220_4412b983 PS1, Line 95: /* code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/09dd67e1_cbf2f1b5 PS1, Line 96: if (s0ix_entry == S0IX_ENTRY) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/5ce8fef3_f7f5a5b6 PS1, Line 97: implement variant operations here code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/2d73f790_27028ea3 PS1, Line 98: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/51e711d0_2faf88e5 PS1, Line 99: if (s0ix_entry == S0IX_EXIT) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/5f823168_82378b1b PS1, Line 100: implement variant operations here code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/4613c644_9dd0ecf9 PS1, Line 101: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/b25340d9_46a666e2 PS1, Line 102: */ code indent should use tabs where possible File src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/ce1e7c0a_98052f67 PS1, Line 19: S0IX_EXIT, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/886fa9f8_0ae473c9 PS1, Line 19: S0IX_EXIT, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/24e877a2_afb65db5 PS1, Line 20: S0IX_ENTRY, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158125): https://review.coreboot.org/c/coreboot/+/67373/comment/8d074a27_e5e10317 PS1, Line 20: S0IX_ENTRY, please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/67373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb Gerrit-Change-Number: 67373 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 09:06:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/variants/shotzo: Turn off LAN power in S0ix
by Tony Huang (Code Review) 06 Sep '22

06 Sep '22

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67373 ) Change subject: mb/google/dedede/variants/shotzo: Turn off LAN power in S0ix ...................................................................... mb/google/dedede/variants/shotzo: Turn off LAN power in S0ix Turn off the onboard LAN power which is controlled by GPP_A10 to save power in S0ix states. For an USB device, the S0ix hook is needed for the on/off operations to take place. BUG=b:12345 BRANCH=firmware-dedede-13606.B TEST=emerge-shotzo coreboot check LAN LED off in s0ix states Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dedede/variants/shotzo/Makefile.inc A src/mainboard/google/dedede/variants/shotzo/variant.c 4 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/67373/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index ca5a21c..0e87758 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> @@ -63,10 +64,50 @@ return current; } +static void mainboard_generate_s0ix_hook(void) +{ + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + { + variant_generate_s0ix_hook(S0IX_ENTRY); + } + acpigen_write_else(); + { + variant_generate_s0ix_hook(S0IX_EXIT); + } + acpigen_write_if_end(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + + acpigen_write_scope("\\_SB"); + acpigen_write_method_serialized("MS0X", 1); + mainboard_generate_s0ix_hook(); + acpigen_write_method_end(); /* Method */ + acpigen_write_scope_end(); /* Scope */ + +} + +void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + + /* Add board-specific MS0X entries */ + /* + if (s0ix_entry == S0IX_ENTRY) { + implement variant operations here + } + if (s0ix_entry == S0IX_EXIT) { + implement variant operations here + } + */ +} + + static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index aef3075..0b11f26 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -15,6 +15,11 @@ const struct pad_config *variant_sleep_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); +enum s0ix_entry { + S0IX_EXIT, + S0IX_ENTRY, +}; + /** * Get board's Hardware features as defined in FW_CONFIG * @@ -44,4 +49,6 @@ /* Modify LTE devictree settings during ramstage. */ void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio); + +void variant_generate_s0ix_hook(enum s0ix_entry); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/dedede/variants/shotzo/Makefile.inc b/src/mainboard/google/dedede/variants/shotzo/Makefile.inc index eb2c9bc..655f3c8 100644 --- a/src/mainboard/google/dedede/variants/shotzo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/shotzo/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/shotzo/variant.c b/src/mainboard/google/dedede/variants/shotzo/variant.c new file mode 100644 index 0000000..7f13fbc --- /dev/null +++ b/src/mainboard/google/dedede/variants/shotzo/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <variant/gpio.h> +#include <acpi/acpigen.h> + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(GPP_A10); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(GPP_A10); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/67373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb Gerrit-Change-Number: 67373 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: tests/commonlib/rational-test: Use test group runner wrapper
by Yu-Ping Wu (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Jakub Czapiga. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67371 ) Change subject: tests/commonlib/rational-test: Use test group runner wrapper ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iead63cab0465f37b2da0c7b3ef256057e3a191a2 Gerrit-Change-Number: 67371 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 09:02:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek: a common implementation to register BL31 reset
by Yu-Ping Wu (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67359 ) Change subject: soc/mediatek: a common implementation to register BL31 reset ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf Gerrit-Change-Number: 67359 Gerrit-PatchSet: 7 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 09:01:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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