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Change subject: mb/google/guybrush: enable display backlight in ramstage
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/67246/comment/18cf170d_2807f80f
PS1, Line 141: PAD_GPO
> The pin seems to be in the S5 domain, so it should retain its value
looking at the original bug, it seemed that some SKUs were having issues with the backlight being restored at min value coming out of Si0x, and using ACPI to set the backlight was part of the workaround. I'm unable to reproduce that problem on Dewatt though.
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Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
guybrush: remove RO_GSCVD area from FMAP
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com>
Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945
---
M src/mainboard/google/guybrush/chromeos.fmd
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/67376/2
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Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158134):
https://review.coreboot.org/c/coreboot/+/67376/comment/dff5e755_88f1d9ce
PS1, Line 9: This area relates to storing of AP RO verification information.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
guybrush: remove RO_GSCVD area from FMAP
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and guybrush is
using TPM_GOOGLE_CR50.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com>
Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945
---
M src/mainboard/google/guybrush/chromeos.fmd
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/67376/1
diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd
index a6dbc2c..3875700 100644
--- a/src/mainboard/google/guybrush/chromeos.fmd
+++ b/src/mainboard/google/guybrush/chromeos.fmd
@@ -22,7 +22,6 @@
RW_LEGACY(CBFS)
WP_RO@8M 8M {
RO_VPD(PRESERVE) 16K
- RO_GSCVD 8K
RO_SECTION {
FMAP 2K
RO_FRID 64
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Change subject: Add support for PSP NVRAM base addr and size
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File util/amdfwtool/amdfwtool.h:
https://review.coreboot.org/c/coreboot/+/67137/comment/031422b9_10c625ac
PS4, Line 279: uint64_t dest;
: size_t size;
> But this amd_fw_entry is for legacy XHCI,IMC firmware, not for PSP FW.
Done.
you are right.
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I'd like you to reexamine a change. Please visit
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Change subject: device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
......................................................................
device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
Change-Id: Iaffa84704d2a627394b2aae4d35d47d1358a2621
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/device/dram/ddr2.c
M src/device/dram/ddr3.c
M src/device/dram/ddr4.c
M src/device/dram/spd.c
M src/include/device/dram/ddr2.h
M src/include/device/dram/ddr3.h
M src/include/device/dram/ddr4.h
M src/include/spd.h
M src/mainboard/scaleway/tagada/ramstage.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M tests/lib/dimm_info_util-test.c
12 files changed, 106 insertions(+), 180 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62181/9
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Change subject: mb/google/skyrim: Enable ASPM for SD
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/skyrim/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/67304/comment/307f5e1a_188e552f
PS1, Line 31: 2
i'd use ASPM_L1 from enum dxio_aspm_type instead. same for the other two descriptors, but that's probably something for another patch
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Change subject: mb/google/zork: Enable AC wake
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
Will this be a full wake or a dark resume?
Was this also tested with the lid closed? i.e. Does the Ezkinil go back to sleep properly when inserting AC while the lid is closed?
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