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Change subject: util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
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Patch Set 6: Code-Review+1
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Change subject: soc/amd/mendocino/Kconfig: Enable APOB_HASH
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Change subject: util/amdfwtool/amdfwread: Handle recovery A/B layout
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Patch Set 7: Code-Review+1
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Change subject: lib/xxhash.c: Add new hash functions
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Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/block/apob: Add hashed APOB support
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Patch Set 4:
(1 comment)
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/67301/comment/13ff8a4a_b9535798
PS2, Line 22: RW_MRC_HASH
> Okay, I'll give that a test and see if I can simplify this even more. […]
Can we store the hash in the GSC instead of on the ROM? I believe that's what is being done on the intel side.
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Change subject: util/lint/lint: Add -I option to invert test results
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Patch Set 2: Code-Review+2
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Change subject: mb/google/guybrush: enable display backlight in ramstage
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Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/67246/comment/4ae54d28_93e395f8
PS1, Line 141: PAD_GPO
> looking at the original bug, it seemed that some SKUs were having issues with the backlight being re […]
Yeah, this GPIO wouldn't control the min value, it would just make the screen black. I'm not sure if the SMU restores this GPIO on S0i3 resume. Can you try removing the extra ACPI code?
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Change subject: mb/amd/chausie: Enable APOB_HASH
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