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Change subject: libpayload/Makefile.inc: Initialize vboot depending on UPDATED_SUBMODULES
......................................................................
Patch Set 3:
(1 comment)
File payloads/libpayload/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/67118/comment/a3542765_2b26b7fd
PS2, Line 91: ifneq ($(UPDATED_SUBMODULES),1)
> > Apparently one purpose of UPDATED_SUBMODULES in coreboot's top level Makefile. […]
Hi Nico, are you building manually libpayload?
Here what I see when building libpayload manually (I added few logs to the Makefile.inc)
sbensaid@sbensaid-Z97X-UD7-TH:/tmp/coreboot_build/payloads/libpayload$ make
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES is not defined
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES 0
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES synching
bensaid@sbensaid-Z97X-UD7-TH:/tmp/coreboot_build/payloads/libpayload$ UPDATED_SUBMODULES=1 make
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES 1
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES 1
sbensaid@sbensaid-Z97X-UD7-TH:/tmp/coreboot_build/payloads/libpayload$ UPDATED_SUBMODULES=0 make
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES 0
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES 0
@@@@@@@@@@@@@@@@@@@@@@@@@ UPDATED_SUBMODULES synching
I did not export UPDATED_SUBMODULES
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Change subject: device/dram/ddr: Deduplicate enum spd_dimm_type_ddr{2,3,4}
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Patch Set 9: Code-Review+1
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Change subject: soc/amd: Refactor DPTC Tablet Mode
......................................................................
Patch Set 12:
(2 comments)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/66994/comment/1070d84a_95bfc61c
PS10, Line 91: /* Enable dptc tablet mode */
: bool dptc_tablet_mode_enable;
> > Hrmm, how about you reorder your Cls. Move the CL that deletes the tablet mode before this one. […]
We never call `acpigen_write_alib_dptc` on cezanne though.
File src/soc/amd/picasso/chip.h:
https://review.coreboot.org/c/coreboot/+/66994/comment/2b51f76b_0ff1ec2c
PS10, Line 120: /* Enable dptc for tablet mode */
: bool dptc_enable;
> As you pointed out, removing `dptc_enable` means the default DPTC settings can't be set without also […]
The default settings are always initially set by FSP, so we don't need any ACPI to handle that case. Since we don't use DPTC on CZN and MDN, we should be able to delete `dptc_enable` without any behavior change.
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Change subject: amd: Convert dptc_enable to bool
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Patch Set 8: Code-Review+2
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Change subject: libpayload/Makefile.inc: Initialize vboot depending on UPDATED_SUBMODULES
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Btw. […]
Hi, I tested this with depthcharge payload. I think providing the user the possibility to build with or without submodules is a nice feature. In such a case, it's user responsibility to ensure that all repos needed are installed properly.
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Change subject: soc/amd: Throttle SOC during low/no battery
......................................................................
Patch Set 9:
(2 comments)
File src/mainboard/google/skyrim/variants/skyrim/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67189/comment/f91d2a32_227859ba
PS5, Line 234: # Normal
> No one is setting `dptc_enable`, so we don't have to worry about writing incorrect data.
> ...
> Having the different CLs will make it easier to bisect and blame any regressions.
As you point out, there's nothing to bisect here, so there's no benefit to breaking this CL apart. There is no executable code, so there's nothing to regress aside from build errors which already give a line number.
Regardless, in the interest of trying to move these CLs forward I've split this into another CL.
File src/soc/amd/mendocino/chip.h:
https://review.coreboot.org/c/coreboot/+/67189/comment/f83cee9d_83ce9be4
PS7, Line 68: vrm_current_limit_mA
> Do we need to pass these into FSP as well? […]
I've validated that these values are applied using `agt`. Why would we need to pass these to FSP (what does adding these to `fsp_m_params.c` fix)?
@Felix - Any thoughts here?
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Change subject: soc/amd/acpi: Add low/no battery mode to DPTC
......................................................................
Patch Set 18:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66804/comment/8601240f_d1bc3d3f
PS16, Line 7: soc/amd
> soc/amd/common/acpi
Done
https://review.coreboot.org/c/coreboot/+/66804/comment/9812aea2_abc2b647
PS16, Line 13: refactor CL
> It's not really a refactor CL, it's adding new functionality.
Done
File src/soc/amd/common/acpi/dptc.asl:
https://review.coreboot.org/c/coreboot/+/66804/comment/59e4163a_0108799c
PS16, Line 20: (
> Do we need to group these?
Ah, no. That's a relic from when these were being generated.
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Change subject: soc/amd: Refactor DPTC Tablet Mode
......................................................................
Patch Set 12:
(3 comments)
File src/mainboard/google/zork/variants/morphius/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/66994/comment/a1c40fca_ef5125e3
PS9, Line 34: true
> quote
Done
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/66994/comment/baeff4f4_41b5c41a
PS10, Line 91: /* Enable dptc tablet mode */
: bool dptc_tablet_mode_enable;
> Hrmm, how about you reorder your Cls. Move the CL that deletes the tablet mode before this one.
`acpigen_write_alib_dptc()` requires good (non-null) values for `tablet_param` and `tablet_param_len`, so we can't remove tablet mode without this refactor first.
> I would also just delete the dptc_enable bit in that CL.
See the comment below.
File src/soc/amd/picasso/chip.h:
https://review.coreboot.org/c/coreboot/+/66994/comment/1a7e5845_c913a0ab
PS10, Line 120: /* Enable dptc for tablet mode */
: bool dptc_enable;
> So in reality this bit is already doing what you want. […]
As you pointed out, removing `dptc_enable` means the default DPTC settings can't be set without also including either tablet or no battery settings also.
I'm going to leave it, since I these are three distinct options:
1. Default DPTC
2. Tablet DPTC
3. No Battery DPTC
The only thing special about the default DPTC is that it must be specified if tablet or no battery are enabled, so we have default values to restore when the device leaves those modes.
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Change subject: amd: Convert dptc_enable to bool
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/zork/variants/morphius/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/67188/comment/a7c0f194_d58fbe50
PS5, Line 33: true
> I would say quote it to keep the consistency. […]
Done
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