Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held.
Tim Van Patten has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67378 )
Change subject: skyrim/overridetree: Add "Normal" DPTC values ......................................................................
skyrim/overridetree: Add "Normal" DPTC values
Add the Normal Mode DPTC values for Skyrim.
These values were generated by AMD.
BRANCH=none BUG=b:217911928 TEST=Build skyrim
Signed-off-by: Tim Van Patten timvp@google.com Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a --- M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb M src/soc/amd/mendocino/chip.h 2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/67378/1
diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 945ea19..b60c14a 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -245,4 +245,15 @@ end end # UART1
+ # Normal + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "15000" + register "thermctl_limit_degreeC" = "100" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + end # chip soc/amd/mendocino diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 7b33340..0863f9c 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -56,6 +56,7 @@ uint16_t stt_error_coeff; uint16_t stt_error_rate_coefficient;
+ /* Default */ uint8_t stapm_boost; uint32_t stapm_time_constant_s; uint32_t apu_only_sppt_limit; @@ -64,6 +65,9 @@ uint32_t slow_ppt_limit_mW; uint32_t slow_ppt_time_constant_s; uint32_t thermctl_limit_degreeC; + uint32_t vrm_current_limit_mA; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_current_limit_mA;
uint8_t smartshift_enable;