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Change subject: mb/google/guybrush: enable display backlight in ramstage
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/67246/comment/4ae54d28_93e395f8
PS1, Line 141: PAD_GPO
> looking at the original bug, it seemed that some SKUs were having issues with the backlight being re […]
Yeah, this GPIO wouldn't control the min value, it would just make the screen black. I'm not sure if the SMU restores this GPIO on S0i3 resume. Can you try removing the extra ACPI code?
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Change subject: mb/amd/chausie: Enable APOB_HASH
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Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67377 )
Change subject: soc/amd/mendocino/Kconfig: Enable APOB_HASH
......................................................................
soc/amd/mendocino/Kconfig: Enable APOB_HASH
Enable the APOB_HASH feature. This improves boot times by ~10ms.
BUG=b:193557430
TEST=boot to OS and verify boot time improvement
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: I9628b67cd3206ffdbef23162c453dc183c69e5a5
---
M src/soc/amd/mendocino/Kconfig
1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/67377/1
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index e9d549d..c114af6 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -57,7 +57,8 @@
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_AOAC
- select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_BLOCK_APOB
+ select SOC_AMD_COMMON_BLOCK_APOB_HASH
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
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Change subject: soc/amd/common/block/apob: Add hashed APOB support
......................................................................
soc/amd/common/block/apob: Add hashed APOB support
Comparing the APOB in RAM to flash takes a significant amount of time
(~11ms). Instead of comparing the entire APOB, use a fast hash function
and compare just that. Reading, hashing, and comparing the hash take
~70 microseconds.
BUG=b:193557430
TEST=compile and boot to OS in chausie with and without this option set
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: I241968b115aaf41af63445410660bdd5199ceaba
---
M src/soc/amd/common/block/apob/Kconfig
M src/soc/amd/common/block/apob/apob_cache.c
2 files changed, 78 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/67301/4
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Change subject: mainboard/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
......................................................................
mainboard/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
TEST=Boot ADL-S DDR5 UDIMM 1DPC and check that ramstage is executing
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ic1f62d6dd0b00d26f8c8a71b624ba5fba4c63774
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Kconfig.name
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/devicetree_s.cb
A src/mainboard/intel/adlrvp/early_gpio_s.c
A src/mainboard/intel/adlrvp/gpio_s.c
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
A src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb
11 files changed, 112 insertions(+), 4 deletions(-)
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Change subject: mb/intel/adlrvp: Make SOC_INTEL_CSE_LITE_SKU configurable
......................................................................
mb/intel/adlrvp: Make SOC_INTEL_CSE_LITE_SKU configurable
Having a CSE Lite SKU's firmware is not necessarily depending
on the underlying hardware nor on having ChromeOS installed as
already mentioned in commit f3419b29b7e0 ("soc/intel/common/cse:
Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU").
For example RVP Boards sometimes have a CSE LITE FW, if Chrome board
related stuff is tested, which doesn't necessarily imply a ChromeOS
being used. It is therefore changed to an option, which can be
changed in menuconfig.
Change-Id: I4da7feab881ae43528c9d852cc842ac93fa9c6de
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/mainboard/intel/adlrvp/Kconfig
1 file changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/67078/13
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Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Could we please separate this into 2 commits? One that update the acpigen_dptf.h file and the other for kinox overridetree ? Thanks.
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Change subject: guybrush: remove RO_GSCVD area from FMAP
......................................................................
Patch Set 2: Code-Review+2
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