coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/prodrive/hermes: Add libgfxinit support
by build bot (Jenkins) (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Christian Walter. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62648 ) Change subject: mb/prodrive/hermes: Add libgfxinit support ...................................................................... Patch Set 5: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158130): https://review.coreboot.org/c/coreboot/+/62648/comment/a3dfa770_9adbec02 PS5, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/62648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib71d06e1d83cd26b0fef37acc64f699c452c13dc Gerrit-Change-Number: 62648 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 06 Sep 2022 12:25:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/hermes: Skip setting up ASPEED if primary is IGD
by Angel Pons (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph, Christian Walter. Angel Pons has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/62649 ) Change subject: mb/prodrive/hermes: Skip setting up ASPEED if primary is IGD ...................................................................... mb/prodrive/hermes: Skip setting up ASPEED if primary is IGD This allows the payload to be usable on the Intel integrated graphic device instead of the BMC depending on an eeprom variable. TODO Angel: We also need to skip stuff when coreboot enumerates buses, otherwise coreboot sets up VGA for the ASPEED instead of the Intel iGPU. Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/prodrive/hermes/mainboard.c 1 file changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/62649/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Gerrit-Change-Number: 62649 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/variants/skolas: Set power limit values
by Sumeet R Pawnikar (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67375 to look at the new patch set (#2). Change subject: mb/google/brya/variants/skolas: Set power limit values ...................................................................... mb/google/brya/variants/skolas: Set power limit values Skolas board is based on Raptor Lake SoC, not Alder Lake. The code change sets CPU power limit values as performance configuration based on various Raptor Lake SoC SKUs as per the document #686872. BUG=b:242869605 BRANCH=None TEST=Built and tested on skolas board Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/skolas/ramstage.c M src/mainboard/google/brya/variants/skolas4es/ramstage.c 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/67375/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Gerrit-Change-Number: 67375 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal
by Mario Scheithauer (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Martin L Roth, Arthur Heymans, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67099 ) Change subject: drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Gerrit-Change-Number: 67099 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 12:17:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Change to new RTC RV3028-C7
by Mario Scheithauer (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67101 ) Change subject: mb/siemens/mc_ehl2: Change to new RTC RV3028-C7 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dd00855b8c9b22bdea21d3c8563cdb392868751 Gerrit-Change-Number: 67101 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 12:16:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/variants/skolas: Set power limit values
by build bot (Jenkins) (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67375 ) Change subject: mb/google/brya/variants/skolas: Set power limit values ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158129): https://review.coreboot.org/c/coreboot/+/67375/comment/31a2b74d_daca2086 PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158129): https://review.coreboot.org/c/coreboot/+/67375/comment/341c8660_9b3944e1 PS1, Line 9: Skolas board is based on Raptor Lake SoC, not Alder Lake. The code change Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/67375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Gerrit-Change-Number: 67375 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Sep 2022 12:16:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/variants/skolas: Set power limit values
by Sumeet R Pawnikar (Code Review) 06 Sep '22

06 Sep '22

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67375 ) Change subject: mb/google/brya/variants/skolas: Set power limit values ...................................................................... mb/google/brya/variants/skolas: Set power limit values Skolas board is based on Raptor Lake SoC, not Alder Lake. The code change sets CPU power limit values as performance configuration based on various Raptor Lake SoC SKUs as per the document #686872. BUG=b:242869605 BRANCH=None TEST=Built and tested on skolas board Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/skolas/ramstage.c M src/mainboard/google/brya/variants/skolas4es/ramstage.c 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/67375/1 diff --git a/src/mainboard/google/brya/variants/skolas/ramstage.c b/src/mainboard/google/brya/variants/skolas/ramstage.c index 970c628..b468320 100644 --- a/src/mainboard/google/brya/variants/skolas/ramstage.c +++ b/src/mainboard/google/brya/variants/skolas/ramstage.c @@ -5,12 +5,10 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ - /* All values are for baseline config as per bug:191906315 comment #10 */ - { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, - { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, - { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, - { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, - { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, }; void variant_devtree_update(void) diff --git a/src/mainboard/google/brya/variants/skolas4es/ramstage.c b/src/mainboard/google/brya/variants/skolas4es/ramstage.c index 970c628..b468320 100644 --- a/src/mainboard/google/brya/variants/skolas4es/ramstage.c +++ b/src/mainboard/google/brya/variants/skolas4es/ramstage.c @@ -5,12 +5,10 @@ const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ - /* All values are for baseline config as per bug:191906315 comment #10 */ - { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, - { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, - { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, - { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, - { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, }; void variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/67375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Gerrit-Change-Number: 67375 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50
by Mario Scheithauer (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Martin L Roth, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67169 ) Change subject: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Gerrit-Change-Number: 67169 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 12:15:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add WWAN poweron sequencing
by Ivy Jian (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Eric Lai. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67332 ) Change subject: mb/google/rex: Add WWAN poweron sequencing ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/67332/comment/f6775eab_35970b98 PS1, Line 373: /* GPP_B17 : [] ==> EN_WWAN_PWR */ > Agreed. Asserting reset here sounds sensible. EN_WWAN_PWR could be moved to romstage, it also works with non-serial fw image, https://review.coreboot.org/c/coreboot/+/67332/comment/e323b536_8faa33fd PS1, Line 425: PAD_CFG_GPO(GPP_E07, 1, DEEP), > Have we confirmed timing requirements per the datasheet for the sequencing (ton1, ton2) with non deb […] Sure, will update result later. -- To view, visit https://review.coreboot.org/c/coreboot/+/67332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13 Gerrit-Change-Number: 67332 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 11:38:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
by Sumeet R Pawnikar (Code Review) 06 Sep '22

06 Sep '22

Attention is currently required from: Tim Wawrzynczak, Vidya Gopalakrishnan, Paul Fagerburg, Simon Yang. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67374 ) Change subject: soc/intel/alderlake: add power limits for Alder Lake-N 7W soc ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67374/comment/cf91b14a_2ce759dd PS1, Line 12: None Add bug details. If there is no bug present, let's create new one and add bug information here. -- To view, visit https://review.coreboot.org/c/coreboot/+/67374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270 Gerrit-Change-Number: 67374 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Comment-Date: Tue, 06 Sep 2022 11:15:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2022