[M] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add gpio override settings

[Raul Rangel (Code Review)]

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67209 )

Change subject: mb/google/skyrim/var/winterhold: Add gpio override settings
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mb/google/skyrim/var/winterhold: Add gpio override settings

Follow FT6_SOC_GPIO_PM&Strap_20220815A.XLSX
update Gpio setting

BUG=b:240824497
BRANCH=None

Signed-off-by: EricKY Cheng 
Change-Id: I2086c326cbf46ba6378d18d37dcbbe9fafa6b2bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67209
Tested-by: build bot (Jenkins) 
Reviewed-by: Frank Wu 
Reviewed-by: Dtrain Hsu 
Reviewed-by: Raul Rangel 
---
M src/mainboard/google/skyrim/variants/winterhold/Makefile.inc
A src/mainboard/google/skyrim/variants/winterhold/gpio.c
2 files changed, 51 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Frank Wu: Looks good to me, approved
  Raul Rangel: Looks good to me, approved
  Dtrain Hsu: Looks good to me, approved

diff --git a/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc b/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc
index 88e75bd..db72b15 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc
+++ b/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-or-later

subdirs-y += ./memory
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/skyrim/variants/winterhold/gpio.c b/src/mainboard/google/skyrim/variants/winterhold/gpio.c
new file mode 100644
index 0000000..bed7f4b
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/winterhold/gpio.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* GPIO configuration in ramstage */
+static const struct soc_amd_gpio override_gpio_table[] = {
+
+	/* SOC_PEN_DETECT_ODL */
+	PAD_NC(GPIO_3),
+
+	/* EN_PWR_WWAN_X */
+	PAD_NC(GPIO_8),
+
+	/* SD_AUX_RST_SOC_L */
+	PAD_NC(GPIO_27),
+
+	/* WWAN_RST_L */
+	PAD_NC(GPIO_42),
+
+};
+
+void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
+{
+	*size = ARRAY_SIZE(override_gpio_table);
+	*gpio = override_gpio_table;
+}