[M] Change in coreboot[master]: device: Clear lane error status

[Jonathan Zhang (Code Review)]

Attention is currently required from: Wilson Chou, Marc Jones, Nico Huber, Ryback Hung, Johnny Lin, Tim Wawrzynczak, Paul Menzel, Shuming Chu (Shuming).

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67264 )

Change subject: device: Clear lane error status
......................................................................

Patch Set 5:

(2 comments)

Patchset:

PS2:
> Well, that's the only link training triggered by corebooot. If we want to do […]

Wilson, let's add a code comment accordingly: Lane error status is cleared if PCIEXP_LANE_ERR_STAT_CLEAR is set. Lane error is normal during link training, so we need to clear it. At this moment, link has been used, but for a very short duration.

File src/device/pciexp_device.c:

https://review.coreboot.org/c/coreboot/+/67264/comment/7677f6e4_4fb67bf0 
PS5, Line 551: 	printk(BIOS_DEBUG, "%s: Clear Lane Error Status.\n", dev_path(dev));
> Would anyone ever be interested in the value it may have had before it gets cleared?

Wilson, let's print the current value while we clear it.