coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
by Michael Niewöhner (Code Review) 11 Jan '21

11 Jan '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49046 ) Change subject: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support ...................................................................... soc/intel/cnl: add SLP_S0 residency register and enable LPIT support Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. - Windows and Linux tested on google/akemi - Linux tested on clevo/cml-u Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Tested-By: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: Michael Niewöhner <foss(a)mniewoehner.de> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49046 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 36fa596..259a4a0 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -87,6 +87,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 3576d80..7b00398 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -103,6 +103,8 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) +#define SLP_S0_RES 0x193c + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) /* * The values for GPIO_CFG in Intel Document #572235 are incorrect. -- To view, visit https://review.coreboot.org/c/coreboot/+/49046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Gerrit-Change-Number: 49046 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Michael Niewöhner (Code Review) 11 Jan '21

11 Jan '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... acpi,soc/intel/common: add support for Intel Low Power Idle Table Add support for the Intel LPIT table to support reading Low Power Idle Residency counters by the OS. On platforms supporting S0ix sleep states there can be two types of residencies: * CPU package PC10 residency counter (read from MSR via FFH interface) * PCH SLP_S0 assertion residency counter (read via memory mapped interface) With presence of one or both of these counters in the LPIT table, Linux dynamically adds the corresponding attributes to the cpuidle sysfs interface, that can be used to read the residency timers: * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us The code in src/acpi implements generic LPIT support. Each SoC or platform has to implement `acpi_fill_lpit` to fill the table with platform-specific LPI state entries. This is done in this change for soc/intel/common, while being added as its own compilation unit, so SoCs not yet using common acpi code (like Skylake) can use it, too. Reference: https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle… Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. - Windows and Linux tested on google/akemi together with CB:49046 - Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046 Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Tested-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: Michael Niewöhner <foss(a)mniewoehner.de> Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49045 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c A src/soc/intel/common/block/acpi/lpit.c 7 files changed, 182 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 293c194..2727889 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -40,3 +40,9 @@ help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. + +config ACPI_LPIT + bool + depends on HAVE_ACPI_TABLES + help + Selected by platforms that support and fill Intel Low Power Idle Table. diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a16800b..ee30391 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1293,6 +1293,44 @@ acpi_checksum((void *) fadt, header->length); } +void acpi_create_lpit(acpi_lpit_t *lpit) +{ + acpi_header_t *header = &(lpit->header); + unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t); + + memset((void *)lpit, 0, sizeof(acpi_lpit_t)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "LPIT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->revision = get_acpi_table_revision(LPIT); + header->oem_revision = 42; + header->length = sizeof(acpi_lpit_t); + + current = acpi_fill_lpit(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)lpit; + header->checksum = acpi_checksum((void *)lpit, header->length); +} + +unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid) +{ + memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t)); + lpi_desc->header.length = sizeof(acpi_lpi_desc_ncst_t); + lpi_desc->header.type = ACPI_LPI_DESC_TYPE_NATIVE_CSTATE; + lpi_desc->header.uid = uid; + + return lpi_desc->header.length; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -1313,6 +1351,7 @@ acpi_tcpa_t *tcpa; acpi_tpm2_t *tpm2; acpi_madt_t *madt; + acpi_lpit_t *lpit; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -1507,6 +1546,18 @@ } } + if (CONFIG(ACPI_LPIT)) { + printk(BIOS_DEBUG, "ACPI: * LPIT\n"); + + lpit = (acpi_lpit_t *)current; + acpi_create_lpit(lpit); + if (lpit->header.length >= sizeof(acpi_lpit_t)) { + current += lpit->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, lpit); + } + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; @@ -1515,6 +1566,7 @@ current += madt->header.length; acpi_add_table(rsdp, madt); } + current = acpi_align_current(current); printk(BIOS_DEBUG, "current = %lx\n", current); @@ -1665,6 +1717,8 @@ return 1; case CRAT: return 1; + case LPIT: /* ACPI 5.1 up to 6.3: 0 */ + return 0; default: return -1; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 1c364a0..e266a2d 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -71,7 +71,7 @@ enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, + RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; @@ -257,6 +257,48 @@ u32 flags; /* Multiple APIC flags */ } __packed acpi_madt_t; +/* + * LPIT (Low Power Idle Table) + * Conforms to "Intel Low Power S0 Idle" specification, rev 002 from July 2017. + */ +typedef struct acpi_lpit { + acpi_header_t header; +} __packed acpi_lpit_t; + +/* LPIT: LPI descriptor flags */ +typedef struct acpi_lpi_flags { + uint32_t disabled : 1; + uint32_t counter_not_available : 1; + uint32_t reserved : 30; +} __packed acpi_lpi_desc_flags_t; + +/* LPIT: LPI descriptor types */ +enum acpi_lpi_desc_type { + ACPI_LPI_DESC_TYPE_NATIVE_CSTATE = 0x00, + /* type >= 1 reserved */ +}; + +/* LPIT: LPI descriptor header */ +typedef struct acpi_lpi_desc_hdr { + uint32_t type; + uint32_t length; + uint16_t uid; + uint16_t reserved; +} __packed acpi_lpi_desc_hdr_t; + +#define ACPI_LPIT_CTR_FREQ_TSC 0 + +/* LPIT: Native C-state instruction based LPI structure */ +typedef struct acpi_lpi_desc_ncst { + acpi_lpi_desc_hdr_t header; + acpi_lpi_desc_flags_t flags; + acpi_addr_t entry_trigger; /* Entry trigger C-state */ + uint32_t min_residency; /* Minimum residency or "break-even" in microseconds */ + uint32_t max_latency; /* Worst case exit latency in microseconds */ + acpi_addr_t residency_counter; + uint64_t counter_frequency; /* Frequency in cycles per second - 0 means TSC freq */ +} __packed acpi_lpi_desc_ncst_t; + /* VFCT image header */ typedef struct acpi_vfct_image_hdr { u32 PCIBus; @@ -922,6 +964,8 @@ void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); +unsigned long acpi_fill_lpit(unsigned long current); + /* These can be used by the target port. */ u8 acpi_checksum(u8 *table, u32 length); @@ -1025,6 +1069,9 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +void acpi_create_lpit(acpi_lpit_t *lpit); +unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); + /* For ACPI S3 support. */ void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index d9a7a87..a4f9844 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -5,6 +5,13 @@ help Intel Processor common code for ACPI +config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + bool + depends on HAVE_ACPI_TABLES + select ACPI_LPIT + help + Generate LPIT table with LPI state entries. + if SOC_INTEL_COMMON_BLOCK_ACPI config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c6bdac5..4e3a323 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f4560bd..1a18cfc 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -10,6 +10,7 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/turbo.h> +#include <cpu/intel/msr.h> #include <cpu/intel/common/common.h> #include <cpu/x86/smm.h> #include <intelblocks/acpi.h> diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c new file mode 100644 index 0000000..5b9689c --- /dev/null +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <cpu/intel/msr.h> +#include <soc/iomap.h> +#include <soc/pmc.h> + +unsigned long acpi_fill_lpit(unsigned long current) +{ + uint16_t uid = 0; + acpi_lpi_desc_ncst_t *pkg_counter; + acpi_lpi_desc_ncst_t *sys_counter; + + /* + * Package C10 (PC10) residency counter + */ + pkg_counter = (void *)current; + current += acpi_create_lpi_desc_ncst((void *)current, uid++); + + /* MWAIT LPI state entry trigger */ + pkg_counter->entry_trigger.addrl = 0x60; /* MWAIT(6,0) / HW C10 */ + pkg_counter->entry_trigger.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT; + pkg_counter->entry_trigger.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL; + pkg_counter->entry_trigger.space_id = ACPI_ADDRESS_SPACE_FIXED; + pkg_counter->entry_trigger.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + + /* PC10 residency counter */ + pkg_counter->residency_counter.addrl = MSR_PKG_C10_RESIDENCY; + pkg_counter->residency_counter.bit_offset = 0; + pkg_counter->residency_counter.bit_width = 64; + pkg_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_FIXED; + pkg_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + pkg_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + + /* Min. residency and worst-case latency (from FSP and vendor dumps) */ + pkg_counter->min_residency = 30000; /* break-even: 30 ms */ + pkg_counter->max_latency = 3000; /* worst-case latency: 3 ms */ + + /* + * System (Slp_S0) residency counter + */ + sys_counter = (void *)current; + current += acpi_create_lpi_desc_ncst((void *)current, uid++); + + /* MWAIT LPI state entry trigger */ + sys_counter->entry_trigger.addrl = 0x60; /* MWAIT(6,0) / HW C10 */ + sys_counter->entry_trigger.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT; + sys_counter->entry_trigger.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL; + sys_counter->entry_trigger.space_id = ACPI_ADDRESS_SPACE_FIXED; + sys_counter->entry_trigger.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + + /* Slp_S0 residency counter */ + sys_counter->residency_counter.addrl = PCH_PWRM_BASE_ADDRESS + SLP_S0_RES; + sys_counter->residency_counter.bit_offset = 0; + sys_counter->residency_counter.bit_width = 32; + sys_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_MEMORY; + sys_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + sys_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + + /* Min. residency and worst-case latency (from FSP and vendor dumps) */ + sys_counter->min_residency = 30000; /* break-even: 30 ms */ + sys_counter->max_latency = 3000; /* worst-case latency: 3 ms */ + + return current; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Tim Wawrzynczak (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 11 Jan 2021 20:37:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{common,adl}: drop unneeded Kconfig PMC_LOW_POWER_MODE_PROGRAM
by Tim Wawrzynczak (Code Review) 11 Jan '21

11 Jan '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49125 ) Change subject: soc/intel/{common,adl}: drop unneeded Kconfig PMC_LOW_POWER_MODE_PROGRAM ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: probably, thanks for keeping on eye out! -- To view, visit https://review.coreboot.org/c/coreboot/+/49125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1ffb0ee0078e923fbaeaca640d215408b8f4ec8 Gerrit-Change-Number: 49125 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 20:29:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Move L1_substates_control to pcie_rp.h
by Tim Wawrzynczak (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49295 ) Change subject: soc/intel/common: Move L1_substates_control to pcie_rp.h ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/49295/comment/7022fdab_1bc19525 PS2, Line 37: enum L1_substates_control { Maybe a comment too like, `/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */` -- To view, visit https://review.coreboot.org/c/coreboot/+/49295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Gerrit-Change-Number: 49295 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 20:20:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/xeon_sp: Use busno register definitions
by Maxim Polyakov (Code Review) 11 Jan '21

11 Jan '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49315 ) Change subject: intel/xeon_sp: Use busno register definitions ...................................................................... intel/xeon_sp: Use busno register definitions Tested with BUILD_TIMELESS=1, OCP Delta Lake, remains identical. Change-Id: Ib0998053c9f8c690606b91c1b8c0f1d14caf0658 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/util.c 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/49315/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 95290f2..25ef19f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -52,7 +52,8 @@ #define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 -#define UBOX_DECS_CPUBUSNO_CSR 0xcc +#define UBOX_DECS_CPUBUSNO0_CSR 0xcc +#define UBOX_DECS_CPUBUSNO1_CSR 0xd0 #define VTD_TOLM_CSR 0xd0 #define VTD_TSEG_BASE_CSR 0xa8 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 02061f9..08a5335 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -76,7 +76,8 @@ #define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 -#define UBOX_DECS_CPUBUSNO_CSR 0xcc +#define UBOX_DECS_CPUBUSNO0_CSR 0xcc +#define UBOX_DECS_CPUBUSNO1_CSR 0xd0 #define VTD_TOLM_CSR 0xd0 #define VTD_TSEG_BASE_CSR 0xa8 diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index b4f7eaa..d8c7aff 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -18,9 +18,9 @@ uint32_t reg1, reg2; reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xcc); + UBOX_DECS_CPUBUSNO0_CSR); reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xd0); + UBOX_DECS_CPUBUSNO1_CSR); for (int i = 0; i < 4; ++i) bus[i] = ((reg1 >> (i * 8)) & 0xff); @@ -51,7 +51,7 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) { uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, - UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); + UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO0_CSR); if (bus0) *bus0 = (bus & 0xff); if (bus1) -- To view, visit https://review.coreboot.org/c/coreboot/+/49315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0998053c9f8c690606b91c1b8c0f1d14caf0658 Gerrit-Change-Number: 49315 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Generate ACPI CRAT objects in cb
by Marshall Dawson (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Jason Glenesk. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47727 ) Change subject: soc/amd/picasso: Generate ACPI CRAT objects in cb ...................................................................... Patch Set 4: (3 comments) Patchset: PS4: I have a few ideas for follow-on changes but I think this is pretty close right now. File src/soc/amd/picasso/agesa_acpi.c: https://review.coreboot.org/c/coreboot/+/47727/comment/151dca6a_54717c79 PS4, Line 598: (*cache_affinity)->length = sizeof(struct crat_cache); Remove duplicate. Or was this a copy/paste/modify problem and something's missing? https://review.coreboot.org/c/coreboot/+/47727/comment/76ed7453_139d305b PS4, Line 1028: printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); Nit, this comment is out of place now, however it's mostly outlived its usefulness. -- To view, visit https://review.coreboot.org/c/coreboot/+/47727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Gerrit-Change-Number: 47727 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 17:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: {soc,vc,mb}/intel: Drop support for Cannon Lake SoC
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48775 ) Change subject: {soc,vc,mb}/intel: Drop support for Cannon Lake SoC ...................................................................... {soc,vc,mb}/intel: Drop support for Cannon Lake SoC Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/mainboard/intel/cannonlake_rvp/Kconfig D src/mainboard/intel/cannonlake_rvp/Kconfig.name D src/mainboard/intel/cannonlake_rvp/Makefile.inc D src/mainboard/intel/cannonlake_rvp/board_info.txt D src/mainboard/intel/cannonlake_rvp/bootblock.c D src/mainboard/intel/cannonlake_rvp/chromeos.c D src/mainboard/intel/cannonlake_rvp/chromeos.fmd D src/mainboard/intel/cannonlake_rvp/dsdt.asl D src/mainboard/intel/cannonlake_rvp/mainboard.c D src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c D src/mainboard/intel/cannonlake_rvp/smihandler.c D src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc D src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex D src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex D src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex D src/mainboard/intel/cannonlake_rvp/spd/spd.h D src/mainboard/intel/cannonlake_rvp/spd/spd_util.c D src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc D src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c D src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h D src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h D src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c D src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb D src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h D src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb D src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/romstage/fsp_params.c D src/vendorcode/intel/fsp/fsp2_0/cannonlake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h 36 files changed, 0 insertions(+), 8,033 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Nico Huber: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved -- To view, visit https://review.coreboot.org/c/coreboot/+/48775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Gerrit-Change-Number: 48775 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: {soc,vc,mb}/intel: Drop support for Cannon Lake SoC
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Nathaniel L Desimone. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48775 ) Change subject: {soc,vc,mb}/intel: Drop support for Cannon Lake SoC ...................................................................... Patch Set 11: Code-Review+2 (1 comment) Patchset: PS11: Got feedback from Nate, he doesn't see any future for Cannon Lake work either. Let's get rid of this. -- To view, visit https://review.coreboot.org/c/coreboot/+/48775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Gerrit-Change-Number: 48775 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 17:23:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add APEI EINJ support
by Jonathan Zhang (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Lance Zhao, Marc Jones, Martin Roth, Marshall Dawson, Paul Menzel, Rocky Phagura, Subrata Banik, Angel Pons, Patrick Rudolph. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49286 ) Change subject: src/acpi: Add APEI EINJ support ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49286/comment/b43fcad2_ba4fd323 PS1, Line 11: acpi_create_einj with an address where action table resides. The action table It would be more clear to explain that soc code should prepare the action table, and call acpi_create_einj() with the address of the action table. https://review.coreboot.org/c/coreboot/+/49286/comment/fbcd7e20_9eb7de5e PS1, Line 13: E820 table. The action table must be shared memory between FW and OS. It should be marked as reserved in the E820 table. File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49286/comment/0246a133_f6745c53 PS1, Line 790: for (i = 0; i < TRIGGER_ACTION_TABLES; i++) { Not all socs would define all the entries in action table. Either the size of action table, or the number of entries should be passed to this function. File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/49286/comment/2ea78b99_717f4751 PS1, Line 76: VFCT, NHLT, SPMI, CRAT, EINJ EINJ is not a proprietary table, we should move it up and follow alphabetic order. https://review.coreboot.org/c/coreboot/+/49286/comment/15122650_e12a44c8 PS1, Line 930: #define NO_OP 0x04 please align the values to make it easier to read. https://review.coreboot.org/c/coreboot/+/49286/comment/a8752850_b35a47f3 PS1, Line 961: acpi_einj_action_table_t trigger_action[4]; Here 4 is hardcoded. What is that number? Should we define a macro? -- To view, visit https://review.coreboot.org/c/coreboot/+/49286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Gerrit-Change-Number: 49286 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 17:11:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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