Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49046 )
Change subject: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support ......................................................................
soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR.
- Windows and Linux tested on google/akemi - Linux tested on clevo/cml-u
Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Tested-By: Matt DeVillier matt.devillier@gmail.com Tested-by: Michael Niewöhner foss@mniewoehner.de Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/49046 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 36fa596..259a4a0 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -87,6 +87,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 3576d80..7b00398 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -103,6 +103,8 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
+#define SLP_S0_RES 0x193c + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) /* * The values for GPIO_CFG in Intel Document #572235 are incorrect.