Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49047 )
Change subject: soc/intel/skl: add SLP_S0 residency register and enable LPIT support ......................................................................
soc/intel/skl: add SLP_S0 residency register and enable LPIT support
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR.
Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/49047 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/pmc.h 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0a14bc7..0969a9b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -49,6 +49,7 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 350649a..8fe3f83 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -84,6 +84,7 @@ #define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 +#define SLP_S0_RES 0x13c #define CPPMVRIC 0x31c #define XTALSDQDIS (1 << 22) #endif