Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49048 )
Change subject: soc/intel/{icl,tgl,jsl,ehl}: add LPIT support ......................................................................
soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
Add SLP_S0 residency register and enable LPIT support.
Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048 Reviewed-by: Lance Zhao Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/include/soc/pmc.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/include/soc/pmc.h M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/include/soc/pmc.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/include/soc/pmc.h 8 files changed, 12 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 3031769..25aea15 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h index f331961..1c8cb1a 100644 --- a/src/soc/intel/elkhartlake/include/soc/pmc.h +++ b/src/soc/intel/elkhartlake/include/soc/pmc.h @@ -123,6 +123,8 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928
+#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22)
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 06c1a9b..d1efa55 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 26dae7e..2ca3328 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -119,6 +119,8 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928
+#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22)
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 0a15f05..9e15a50 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index e65e884..1df2c63 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -119,6 +119,8 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928
+#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22)
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c7e10a9..9d073fa 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -43,6 +43,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index f926799..cd0299a 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -152,6 +152,8 @@ #define HPR_CAUSE0_MI_HRPC (1 << 9) #define HPR_CAUSE0_MI_HR (1 << 8)
+#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22)