Change in coreboot[master]: intel/xeon_sp: Use busno register definitions

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49315 )

Change subject: intel/xeon_sp: Use busno register definitions
......................................................................

intel/xeon_sp: Use busno register definitions

Tested with BUILD_TIMELESS=1, OCP Delta Lake, remains identical.

Change-Id: Ib0998053c9f8c690606b91c1b8c0f1d14caf0658
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/util.c
3 files changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/49315/1

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 95290f2..25ef19f 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -52,7 +52,8 @@
 #define UBOX_DECS_BUS			0
 #define UBOX_DECS_DEV			8
 #define UBOX_DECS_FUNC			2
-#define UBOX_DECS_CPUBUSNO_CSR		0xcc
+#define UBOX_DECS_CPUBUSNO0_CSR		0xcc
+#define UBOX_DECS_CPUBUSNO1_CSR		0xd0

#define VTD_TOLM_CSR			0xd0
 #define VTD_TSEG_BASE_CSR		0xa8
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 02061f9..08a5335 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -76,7 +76,8 @@
 #define UBOX_DECS_BUS			0
 #define UBOX_DECS_DEV			8
 #define UBOX_DECS_FUNC			2
-#define UBOX_DECS_CPUBUSNO_CSR		0xcc
+#define UBOX_DECS_CPUBUSNO0_CSR		0xcc
+#define UBOX_DECS_CPUBUSNO1_CSR		0xd0

#define VTD_TOLM_CSR			0xd0
 #define VTD_TSEG_BASE_CSR		0xa8
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index b4f7eaa..d8c7aff 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -18,9 +18,9 @@
    uint32_t reg1, reg2;

reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
-		0xcc);
+		UBOX_DECS_CPUBUSNO0_CSR);
    reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
-		0xd0);
+		UBOX_DECS_CPUBUSNO1_CSR);

for (int i = 0; i < 4; ++i)
    	bus[i] = ((reg1 >> (i * 8)) & 0xff);
@@ -51,7 +51,7 @@
 void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3)
 {
    uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV,
-		UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR);
+		UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO0_CSR);
    if (bus0)
    	*bus0 = (bus & 0xff);
    if (bus1)