coreboot-gerrit January 2021

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Change in coreboot[master]: arch/x86: Simplify .id section
by Kyösti Mälkki (Code Review) 01 Jan '21

01 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48500 ) Change subject: arch/x86: Simplify .id section ...................................................................... arch/x86: Simplify .id section The version string is not required for backwards flashrom compatibility. TBD: FILO needs to switch to board_info in CBFS first. Change-Id: I3f4c066b2d914c3cf81275df5080e442bf57d568 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/id.S 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/48500/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8e8cb56..f61e0e5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -102,8 +102,6 @@ bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h - ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) else diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 574a7dc..5b660e7 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -1,22 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <build.h> - .section ".id", "a", @progbits -ver: - .asciz COREBOOT_VERSION vendor: .asciz CONFIG_MAINBOARD_VENDOR part: .asciz CONFIG_MAINBOARD_PART_NUMBER #if ENV_X86_64 -.long 0xffffffff - ver + 1 /* Reverse offset to the version */ .long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */ .long 0xffffffff - part + 1 /* Reverse offset to the part number */ #else -.long - ver /* Reverse offset to the version */ .long - vendor /* Reverse offset to the vendor id */ .long - part /* Reverse offset to the part number */ #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f4c066b2d914c3cf81275df5080e442bf57d568 Gerrit-Change-Number: 48500 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Copano: Update SPD table
by Hao Chou (Code Review) 01 Jan '21

01 Jan '21

Hao Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48948 ) Change subject: mb/google/volteer: Copano: Update SPD table ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2 Gerrit-Change-Number: 48948 Gerrit-PatchSet: 4 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Jan 2021 13:29:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings
by Michael Niewöhner (Code Review) 01 Jan '21

01 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48885 ) Change subject: nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings ...................................................................... Patch Set 19: (1 comment) https://review.coreboot.org/c/coreboot/+/48885/16/src/soc/intel/apollolake/… File src/soc/intel/apollolake/chip.h: https://review.coreboot.org/c/coreboot/+/48885/16/src/soc/intel/apollolake/… PS16, Line 40: * the secondary controls. > Gone. There it is again https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/48885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Gerrit-Change-Number: 48885 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jan 2021 11:47:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation
by Michael Niewöhner (Code Review) 01 Jan '21

01 Jan '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48958 ) Change subject: soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation ...................................................................... soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation For easier review of the switch to a new register struct in the follow-up change, the panel delay times get converted from destination register raw format to milliseconds representation in this change. Formula for conversion of power cycle delay: gpu_panel_power_cycle_delay_ms = (gpu_panel_power_cycle_delay - 1) * 100 Formula for all others: gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10 The register names gain a suffix `_ms` and calculation of the destination register raw values gets done in gma code now. Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/slippy/variants/falco/overridetree.cb M src/mainboard/google/slippy/variants/leon/overridetree.cb M src/mainboard/google/slippy/variants/peppy/overridetree.cb M src/mainboard/google/slippy/variants/wolf/overridetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/gma.c 17 files changed, 88 insertions(+), 87 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 8111040..cb7fb62 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,11 +1,11 @@ chip soc/intel/broadwell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "7" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index eb33d43..746ec9a 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,11 +1,11 @@ chip soc/intel/broadwell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "210" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 60fb08c..5423043 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,11 +1,11 @@ chip soc/intel/broadwell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "7" + register "gpu_panel_power_backlight_off_delay_ms" = "210" register "s0ix_enable" = "0" diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index c7e2421..19c0ca0 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,11 +1,11 @@ chip soc/intel/broadwell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "500" # 50ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "50" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 8111040..cb7fb62 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,11 +1,11 @@ chip soc/intel/broadwell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "7" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index d8aec0a..989b887 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -4,11 +4,11 @@ register "gpu_dp_c_hotplug" = "0x06" # Set panel power delays - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + register "gpu_panel_power_cycle_delay_ms" = "500" + register "gpu_panel_power_up_delay_ms" = "200" + register "gpu_panel_power_down_delay_ms" = "50" + register "gpu_panel_power_backlight_on_delay_ms" = "200" + register "gpu_panel_power_backlight_off_delay_ms" = "200" register "vr_slow_ramp_rate_set" = "3" register "vr_slow_ramp_rate_enable" = "1" diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index 7df0ca1..54ae615 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/haswell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) - register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) - register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "60" + register "gpu_panel_power_down_delay_ms" = "60" + register "gpu_panel_power_backlight_on_delay_ms" = "210" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb index 6dee38e..9c45f00 100644 --- a/src/mainboard/google/slippy/variants/leon/overridetree.cb +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/haswell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "210" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index 689fee4..47edc62 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/haswell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "gpu_panel_power_cycle_delay_ms" = "400" + register "gpu_panel_power_up_delay_ms" = "40" + register "gpu_panel_power_down_delay_ms" = "15" + register "gpu_panel_power_backlight_on_delay_ms" = "210" + register "gpu_panel_power_backlight_off_delay_ms" = "210" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index de61839..43bdf56 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/haswell # Set panel power delays - register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) - register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) - register "gpu_panel_power_down_delay" = "500" # 50ms (T10) - register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + register "gpu_panel_power_cycle_delay_ms" = "500" + register "gpu_panel_power_up_delay_ms" = "200" + register "gpu_panel_power_down_delay_ms" = "50" + register "gpu_panel_power_backlight_on_delay_ms" = "1" + register "gpu_panel_power_backlight_off_delay_ms" = "200" device domain 0 on diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 140aa84..9baec90 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -4,11 +4,11 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" - register "gpu_panel_power_backlight_off_delay" = "1" - register "gpu_panel_power_backlight_on_delay" = "1" - register "gpu_panel_power_cycle_delay" = "6" - register "gpu_panel_power_down_delay" = "500" - register "gpu_panel_power_up_delay" = "2000" + register "gpu_panel_power_backlight_off_delay_ms" = "1" + register "gpu_panel_power_backlight_on_delay_ms" = "1" + register "gpu_panel_power_cycle_delay_ms" = "500" + register "gpu_panel_power_down_delay_ms" = "50" + register "gpu_panel_power_up_delay_ms" = "200" register "gpu_pch_backlight_pwm_hz" = "200" register "usb_xhci_on_resume" = "true" device cpu_cluster 0 on diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 9359bb4..e17807f 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -4,11 +4,11 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_power_backlight_off_delay" = "1" - register "gpu_panel_power_backlight_on_delay" = "1" - register "gpu_panel_power_cycle_delay" = "6" - register "gpu_panel_power_down_delay" = "500" - register "gpu_panel_power_up_delay" = "2000" + register "gpu_panel_power_backlight_off_delay_ms" = "1" + register "gpu_panel_power_backlight_on_delay_ms" = "1" + register "gpu_panel_power_cycle_delay_ms" = "500" + register "gpu_panel_power_down_delay_ms" = "50" + register "gpu_panel_power_up_delay_ms" = "200" register "gpu_pch_backlight_pwm_hz" = "220" register "ec_present" = "true" device cpu_cluster 0x0 on diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0d0fc72..41943e7 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -10,11 +10,11 @@ register "gpu_pch_backlight_pwm_hz" = "200" # Set panel power delays - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + register "gpu_panel_power_cycle_delay_ms" = "500" + register "gpu_panel_power_up_delay_ms" = "200" + register "gpu_panel_power_down_delay_ms" = "50" + register "gpu_panel_power_backlight_on_delay_ms" = "200" + register "gpu_panel_power_backlight_off_delay_ms" = "200" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 73375d7..b1c8d37 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,11 +17,11 @@ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ - u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ - u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u16 gpu_panel_power_cycle_delay_ms; /* T4 time sequence */ + u16 gpu_panel_power_up_delay_ms; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay_ms; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay_ms; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay_ms; /* Tx time sequence */ unsigned int gpu_pch_backlight_pwm_hz; enum { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 71d5ab6..7adcfda 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -257,24 +257,24 @@ /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay) { + if (conf->gpu_panel_power_cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 81c9780..b77cb71 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -19,11 +19,11 @@ u8 gpu_dp_d_hotplug; /* Panel power sequence timings */ - u8 gpu_panel_power_cycle_delay; - u16 gpu_panel_power_up_delay; - u16 gpu_panel_power_down_delay; - u16 gpu_panel_power_backlight_on_delay; - u16 gpu_panel_power_backlight_off_delay; + u16 gpu_panel_power_cycle_delay_ms; + u16 gpu_panel_power_up_delay_ms; + u16 gpu_panel_power_down_delay_ms; + u16 gpu_panel_power_backlight_on_delay_ms; + u16 gpu_panel_power_backlight_off_delay_ms; /* Panel backlight settings */ unsigned int gpu_pch_backlight_pwm_hz; diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index c033b49..9866ed3 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -4,6 +4,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <bootmode.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -298,24 +299,24 @@ /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay) { + if (conf->gpu_panel_power_cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230 Gerrit-Change-Number: 48958 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/tigerlake: Use the newly added meminit block driver
by Furquan Shaikh (Code Review) 01 Jan '21

01 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49041 ) Change subject: soc/intel/tigerlake: Use the newly added meminit block driver ...................................................................... soc/intel/tigerlake: Use the newly added meminit block driver This change uses the newly added meminit block driver and updates TGL SoC and mainboard code accordingly. Change-Id: I9daed06b9d09b2c274f93e0a4cbf608f0f334a60 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/volteer/romstage.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/drobit/memory.c M src/mainboard/google/volteer/variants/eldrid/memory.c M src/mainboard/google/volteer/variants/elemi/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/lindar/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voema/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 26 files changed, 1,104 insertions(+), 1,409 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/49041/1 diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 67d3489..f3fb454 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -14,13 +14,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct ddr_memory_cfg *board_cfg = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *board_cfg = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 4d5dc87..2431c59 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct ddr_memory_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); int variant_memory_sku(void); /* Modify devictree settings during ramstage. */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b..096aa5c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -4,64 +4,59 @@ #include <baseboard/variants.h> #include <gpio.h> -static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { - /* DQ CPU<>DRAM map */ - .dq_map = { - [0] = { - { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &baseboard_lpddr4x_memcfg -}; - -const struct ddr_memory_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 9d8ad40..6ccb503 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -2,64 +2,59 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg delbin_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &delbin_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/drobit/memory.c b/src/mainboard/google/volteer/variants/drobit/memory.c index 9d8ad40..2b4ec29 100644 --- a/src/mainboard/google/volteer/variants/drobit/memory.c +++ b/src/mainboard/google/volteer/variants/drobit/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg delbin_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &delbin_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c index 577734d..04dbe44 100644 --- a/src/mainboard/google/volteer/variants/eldrid/memory.c +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -4,16 +4,11 @@ #include <baseboard/variants.h> #include <gpio.h> -/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ -static const struct mb_ddr4_cfg eldrid_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_DDR4, - .ddr4_cfg = &eldrid_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c index 32b7abc..8ec6996 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory.c +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -4,16 +4,11 @@ #include <baseboard/variants.h> #include <gpio.h> -/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ -static const struct mb_ddr4_cfg elemi_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_DDR4, - .ddr4_cfg = &elemi_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c index edbb681..ef039a4 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg halvor_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ + .dq1 = { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &halvor_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c index 11bcf4c..b2de562 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory.c +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -2,64 +2,60 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg lindar_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &lindar_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 2c879e0..b2de562 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -2,64 +2,60 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg malefor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, .ect = 1, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &malefor_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 7d95658..b4414d4 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg terrador_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &terrador_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index c8b4ab4..b4414d4 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg todor_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &todor_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voema/memory.c b/src/mainboard/google/volteer/variants/voema/memory.c index b611af5..b4414d4 100644 --- a/src/mainboard/google/volteer/variants/voema/memory.c +++ b/src/mainboard/google/volteer/variants/voema/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg voema_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &voema_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 40b1086..fe2b2b1 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg voxel_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ - { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ - { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ - { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ - { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ - { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ - { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ - { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ + .ect = true, /* Enable Early Command Training */ }; -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &voxel_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 80ec14a..32ee7e8 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -5,85 +5,179 @@ #include <baseboard/variants.h> #include <soc/romstage.h> -static const struct mb_cfg ddr4_mem_config = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* Baseboard Rcomp target values */ - .rcomp_targets = {40, 30, 33, 33, 30}, - - .dq_pins_interleaved = false, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, -}; - static const struct mb_cfg lpddr4_mem_config = { - /* DQ byte map */ - .dq_map = { - { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 }, - { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 }, - { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 }, - { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 }, - { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 }, - { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 }, - { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 }, - { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 }, + .type = MEM_TYPE_LP4X, + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 2, 3, 1, 6, 7, 5, 4 }, + .dq1 = { 10, 8, 11, 9, 14, 12, 13, 15 }, + }, + .ddr1 = { + .dq0 = { 12, 8, 14, 10, 11, 13, 15, 9 }, + .dq1 = { 5, 0, 7, 3, 6, 2, 1, 4 }, + }, + .ddr2 = { + .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7 }, + .dq1 = { 12, 13, 14, 15, 10, 9, 8, 11 }, + }, + .ddr3 = { + .dq0 = { 2, 6, 7, 1, 3, 4, 0, 5 }, + .dq1 = { 9, 13, 8, 15, 14, 11, 12, 10 }, + }, + .ddr4 = { + .dq0 = { 3, 0, 1, 2, 7, 4, 6, 5 }, + .dq1 = { 10, 8, 11, 9, 14, 13, 12, 15 }, + }, + .ddr5 = { + .dq0 = { 10, 12, 14, 8, 9, 13, 15, 11 }, + .dq1 = { 3, 7, 6, 2, 0, 4, 5, 1 }, + }, + .ddr6 = { + .dq0 = { 12, 15, 14, 13, 9, 10, 11, 8 }, + .dq1 = { 7, 4, 6, 5, 0, 1, 3, 2 }, + }, + .ddr7 = { + .dq0 = { 0, 2, 4, 3, 1, 6, 7, 5 }, + .dq1 = { 13, 9, 10, 11, 8, 12, 14, 15 }, + }, }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + .lpx_dqs_map = { + .ddr0 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr1 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr2 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr3 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr4 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr5 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr6 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr7 = { + .dqs0 = 0, + .dqs1 = 1, + }, }, - - .dq_pins_interleaved = false, - - .ect = true, /* Early Command Training */ - + .ect = true, .UserBd = BOARD_TYPE_MOBILE, }; static const struct mb_cfg lp5_mem_config = { - - /* DQ byte map */ - .dq_map = { - { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, - { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, - { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, - { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, - { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, - { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, - { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, - { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, + .type = MEM_TYPE_LP5X, + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 12, 8, 14, 10, 11, 13, 15, 9 }, + .dq1 = { 5, 0, 7, 3, 6, 2, 1, 4 }, + }, + .ddr2 = { + .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7 }, + .dq1 = { 12, 13, 14, 15, 10, 9, 8, 11 }, + }, + .ddr3 = { + .dq0 = { 2, 6, 7, 1, 3, 4, 0, 5 }, + .dq1 = { 9, 13, 8, 15, 14, 11, 12, 10 }, + }, + .ddr4 = { + .dq0 = { 3, 0, 1, 2, 7, 4, 6, 5 }, + .dq1 = { 10, 8, 11, 9, 14, 13, 12, 15 }, + }, + .ddr5 = { + .dq0 = { 10, 12, 14, 8, 9, 13, 15, 11 }, + .dq1 = { 3, 7, 6, 2, 0, 4, 5, 1 }, + }, + .ddr6 = { + .dq0 = { 12, 15, 14, 13, 9, 10, 11, 8 }, + .dq1 = { 7, 4, 6, 5, 0, 1, 3, 2 }, + }, + .ddr7 = { + .dq0 = { 0, 2, 4, 3, 1, 6, 7, 5 }, + .dq1 = { 13, 9, 10, 11, 8, 12, 14, 15 }, + }, + }, + .lpx_dqs_map = { + .ddr0 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr1 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr2 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr3 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr4 = { + .dqs0 = 0, + .dqs1 = 1, + }, + .ddr5 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr6 = { + .dqs0 = 1, + .dqs1 = 0, + }, + .ddr7 = { + .dqs0 = 0, + .dqs1 = 1, + }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } - }, - - .dq_pins_interleaved = false, - - .ect = false, /* Early Command Training */ - - .lp5_ccc_config = 0xff, - + .ect = false, .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + .ccc_config = 0xff, + }, }; static const struct mb_cfg ddr5_mem_config = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* Baseboard Rcomp target values */ - .rcomp_targets = {50, 30, 30, 30, 27}, - - .dq_pins_interleaved = false, - - .ect = true, /* Early Command Training */ - + .type = MEM_TYPE_DDR5, + .ect = true, .UserBd = BOARD_TYPE_MOBILE, + .ddr_config = { + .rcomp_resistor = {100, 100, 100}, + .rcomp_targets = {50, 30, 30, 30, 27}, + .dq_pins_interleaved = false, + }, +}; + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + .ect = true, + .UserBd = BOARD_TYPE_MOBILE, + .ddr_config = { + .rcomp_resistor = {100, 100, 100}, + .rcomp_targets = {40, 30, 33, 33, 30}, + .dq_pins_interleaved = false, + }, }; const struct mb_cfg *variant_memory_params(void) diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 2f03cb4..2145f26 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,19 +31,21 @@ int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lp4_lp5_spd_info = { - .read_type = READ_SPD_CBFS, - .spd_spec.spd_index = get_spd_index(), + const struct mem_spd lp4_lp5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), }; - const struct spd_info ddr4_ddr5_spd_info = { - .read_type = READ_SMBUS, - .spd_spec = { - .spd_smbus_address = { - [0] = 0xa0, - [1] = 0xa2, - [8] = 0xa4, - [9] = 0xa6, + const struct mem_spd ddr4_ddr5_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .dimm_addr[0] = 0xa0, + .dimm_addr[1] = 0xa2, + }, + [1] = { + .dimm_addr[0] = 0xa4, + .dimm_addr[1] = 0xa6, }, }, }; diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 47507f4..3341568 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -42,14 +42,13 @@ { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct lpddr4x_cfg *mem_config = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *mem_config = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = mainboard_get_spd_index(), }; bool half_populated = false; - meminit_lpddr4x(mem_cfg, mem_config, &spd_info, half_populated); + memcfg_init(mem_cfg, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index bad9e9e..fbb86f7 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -15,6 +15,6 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index 490a145..e965e6b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -9,59 +9,61 @@ return 0; } -static const struct lpddr4x_cfg mem_config = { +static const struct mb_cfg mem_config = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */ }, - [1] = { - { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */ - { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */ - { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */ - { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */ - { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */ - { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */ - { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */ - { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Early Command Training */ + .ect = true, /* Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index ca60357..8e7bb14 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -9,59 +9,61 @@ return 0; } -static const struct lpddr4x_cfg mem_config = { +static const struct mb_cfg mem_config = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ - { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ - { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ - { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ - { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ - { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ - { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Early Command Training */ + .ect = true, /* Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index c73df50..80ee1cc 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -50,6 +50,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP @@ -234,4 +235,17 @@ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual + +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config MRC_CHANNEL_WIDTH + int + default 16 + endif diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 36d0750..5d480dc 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -6,105 +6,123 @@ #include <stddef.h> #include <stdint.h> #include <fsp/soc_binding.h> +#include <intelblocks/meminit.h> -#define BYTES_PER_CHANNEL 2 -#define BITS_PER_BYTE 8 -#define DQS_PER_CHANNEL 2 +#define LPX_PHYSICAL_CH_WIDTH 16 +#define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) -/* 64-bit Channel identification */ -enum { - DDR_CH0, - DDR_CH1, - DDR_CH2, - DDR_CH3, - DDR_CH4, - DDR_CH5, - DDR_CH6, - DDR_CH7, - DDR_NUM_CHANNELS -}; -/* Number of memory DIMM slots available on Alderlake board */ -#define NUM_DIMM_SLOT 16 +#define DDR4_PHYSICAL_CH_WIDTH 64 +#define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH) -struct spd_by_pointer { - size_t spd_data_len; - uintptr_t spd_data_ptr; +#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) + +enum mem_type { + MEM_TYPE_DDR4, + MEM_TYPE_DDR5, + MEM_TYPE_LP4X, + MEM_TYPE_LP5X, }; -enum mem_info_read_type { - NOT_EXISTING, /* No memory in this slot */ - READ_SMBUS, /* Read on-module spd by SMBUS. */ - READ_SPD_CBFS, /* Find SPD file in CBFS. */ - READ_SPD_MEMPTR /* Find SPD data from pointer. */ +struct ddr4_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; + uint8_t dq2[BITS_PER_BYTE]; + uint8_t dq3[BITS_PER_BYTE]; + uint8_t dq4[BITS_PER_BYTE]; + uint8_t dq5[BITS_PER_BYTE]; + uint8_t dq6[BITS_PER_BYTE]; + uint8_t dq7[BITS_PER_BYTE]; }; -struct spd_info { - enum mem_info_read_type read_type; - union spd_data_by { - /* To read on-module SPD when read_type is READ_SMBUS. */ - uint8_t spd_smbus_address[NUM_DIMM_SLOT]; - - /* To identify SPD file when read_type is READ_SPD_CBFS. */ - int spd_index; - - /* To find SPD data when read_type is READ_SPD_MEMPTR. */ - struct spd_by_pointer spd_data_ptr_info; - } spd_spec; +struct ddr4_dqs { + uint8_t dqs0; + uint8_t dqs1; + uint8_t dqs2; + uint8_t dqs3; + uint8_t dqs4; + uint8_t dqs5; + uint8_t dqs6; + uint8_t dqs7; }; -/* Board-specific memory configuration information */ -struct mb_cfg { - /* DQ mapping */ - uint8_t dq_map[DDR_NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; +struct ddr4_dq_map { + struct ddr4_dq ddr0; + struct ddr4_dq ddr1; +}; - /* - * DQS CPU<>DRAM map. Each array entry represents a - * mapping of a dq bit on the CPU to the bit it's connected to on - * the memory part. The array index represents the dqs bit number - * on the memory part, and the values in the array represent which - * pin on the CPU that DRAM pin connects to. - */ - uint8_t dqs_map[DDR_NUM_CHANNELS][DQS_PER_CHANNEL]; +struct ddr4_dqs_map { + struct ddr4_dqs ddr0; + struct ddr4_dqs ddr1; +}; - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ +struct mem_ddr_config { + uint8_t dq_pins_interleaved; uint16_t rcomp_resistor[3]; - - /* Rcomp target values. */ uint16_t rcomp_targets[5]; - - /* - * Dqs Pins Interleaved Setting. Enable/Disable Control - * TRUE = enable, FALSE = disable - */ - bool dq_pins_interleaved; - - /* - * Early Command Training Enable/Disable Control - * TRUE = enable, FALSE = disable - */ - bool ect; - - /* Board type */ - uint8_t UserBd; - - /* - * Command pins mapping for Controller Channel (ccc) - * lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and - * bits [7:4] are Controller 1 Channel [3:0] - * Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending. - */ - uint8_t lp5_ccc_config; }; -/* - * Initialize default memory configurations for Alder Lake. - */ +struct lpx_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; +}; -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, - const struct spd_info *spd_info, bool half_populated); +struct lpx_dqs { + uint8_t dqs0; + uint8_t dqs1; +}; + +struct lpx_dq_map { + struct lpx_dq ddr0; + struct lpx_dq ddr1; + struct lpx_dq ddr2; + struct lpx_dq ddr3; + struct lpx_dq ddr4; + struct lpx_dq ddr5; + struct lpx_dq ddr6; + struct lpx_dq ddr7; +}; + +struct lpx_dqs_map { + struct lpx_dqs ddr0; + struct lpx_dqs ddr1; + struct lpx_dqs ddr2; + struct lpx_dqs ddr3; + struct lpx_dqs ddr4; + struct lpx_dqs ddr5; + struct lpx_dqs ddr6; + struct lpx_dqs ddr7; +}; + +struct mem_lp5x_config { + uint8_t ccc_config; +}; + +struct mb_cfg { + enum mem_type type; + + union { + uint8_t dq_map[CONFIG_DATA_BUS_WIDTH]; + struct lpx_dq_map lpx_dq_map; + struct ddr4_dq_map ddr4_dq_map; + }; + + union { + uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE]; + struct lpx_dqs_map lpx_dqs_map; + struct ddr4_dqs_map ddr4_dqs_map; + }; + + union { + struct mem_lp5x_config lp5x_config; + struct mem_ddr_config ddr_config; + }; + + bool ect; + uint8_t UserBd; +}; + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 8473ad8..2e9cae2 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -7,179 +7,131 @@ #include <spd_bin.h> #include <string.h> -enum dimm_enable_options { - ENABLE_BOTH_DIMMS = 0, - DISABLE_DIMM0 = 1, - DISABLE_DIMM1 = 2, - DISABLE_BOTH_DIMMS = 3 +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_DDR4] = { + .num_phys_channels = DDR4_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 4, + }, + .md_phy_masks = { + .half_channel = BIT(0), + .mixed_topo = BIT(1), + }, + }, + [MEM_TYPE_DDR5] = { + .num_phys_channels = DDR5_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 4, + [3] = 5, + }, + .md_phy_masks = { + .half_channel = BIT(0) | BIT(1), + .mixed_topo = BIT(2) | BIT(3), + }, + }, + [MEM_TYPE_LP4X] = { + .num_phys_channels = LPX_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + }, + }, + [MEM_TYPE_LP5X] = { + .num_phys_channels = LPX_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + }, + }, }; -static void spd_read_from_cbfs(const struct spd_info *spd_info, - uintptr_t *spd_data_ptr, size_t *spd_data_len) +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) { - struct region_device spd_rdev; - size_t spd_index = spd_info->spd_spec.spd_index; + struct board_cfg board_cfg = { + .dq_map = mb_cfg->dq_map, + .dqs_map = mb_cfg->dqs_map, + .half_populated = half_populated, + .mem_type = mb_cfg->type, + .spd_info = spd_info, + }; + struct fspm_upd_ptrs upd_ptrs = { + .dq = { + &mem_cfg->DqMapCpu2DramCh0, + &mem_cfg->DqMapCpu2DramCh1, + &mem_cfg->DqMapCpu2DramCh2, + &mem_cfg->DqMapCpu2DramCh3, + &mem_cfg->DqMapCpu2DramCh4, + &mem_cfg->DqMapCpu2DramCh5, + &mem_cfg->DqMapCpu2DramCh6, + &mem_cfg->DqMapCpu2DramCh7, + }, + .dqs = { + &mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1, + &mem_cfg->DqsMapCpu2DramCh2, + &mem_cfg->DqsMapCpu2DramCh3, + &mem_cfg->DqsMapCpu2DramCh4, + &mem_cfg->DqsMapCpu2DramCh5, + &mem_cfg->DqsMapCpu2DramCh6, + &mem_cfg->DqsMapCpu2DramCh7, + }, + .disable_dimm = { + &mem_cfg->DisableDimmMc0Ch0, + &mem_cfg->DisableDimmMc0Ch1, + &mem_cfg->DisableDimmMc0Ch2, + &mem_cfg->DisableDimmMc0Ch3, + &mem_cfg->DisableDimmMc1Ch0, + &mem_cfg->DisableDimmMc1Ch1, + &mem_cfg->DisableDimmMc1Ch2, + &mem_cfg->DisableDimmMc1Ch3, + }, + .spd = { + [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, + [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, + [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, + [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, + [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, + [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, + [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, + [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + }, + .spd_len = &mem_cfg->MemorySpdDataLen, + }; - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); + mem_init_fspm_upds(&board_cfg, &soc_mem_cfg[0], &upd_ptrs); - *spd_data_len = region_device_sz(&spd_rdev); - - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); -} - -static void get_spd_data(const struct spd_info *spd_info, - uintptr_t *spd_data_ptr, size_t *spd_data_len) -{ - if (spd_info->read_type == READ_SPD_MEMPTR) { - *spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr; - *spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len; - return; + switch (mb_cfg->type) { + case MEM_TYPE_DDR4: + break; + case MEM_TYPE_DDR5: + break; + case MEM_TYPE_LP4X: + break; + case MEM_TYPE_LP5X: + break; + default: + die("Unsupported memory type(%d)\n", mb_cfg->type); } - - if (spd_info->read_type == READ_SPD_CBFS) { - spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len); - return; - } -} - -static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, - const struct mb_cfg *board_cfg, - bool half_populated) -{ - memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); - - memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, - sizeof(mem_cfg->RcompTarget)); - - memcpy(&mem_cfg->DqMapCpu2DramCh0, &board_cfg->dq_map[DDR_CH0], - sizeof(board_cfg->dq_map[DDR_CH0])); - memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], - sizeof(board_cfg->dqs_map[DDR_CH0])); - - memcpy(&mem_cfg->DqMapCpu2DramCh1, &board_cfg->dq_map[DDR_CH1], - sizeof(board_cfg->dq_map[DDR_CH1])); - memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], - sizeof(board_cfg->dqs_map[DDR_CH1])); - - memcpy(&mem_cfg->DqMapCpu2DramCh2, &board_cfg->dq_map[DDR_CH2], - sizeof(board_cfg->dq_map[DDR_CH2])); - memcpy(&mem_cfg->DqsMapCpu2DramCh2, &board_cfg->dqs_map[DDR_CH2], - sizeof(board_cfg->dqs_map[DDR_CH2])); - - memcpy(&mem_cfg->DqMapCpu2DramCh3, &board_cfg->dq_map[DDR_CH3], - sizeof(board_cfg->dq_map[DDR_CH3])); - memcpy(&mem_cfg->DqsMapCpu2DramCh3, &board_cfg->dqs_map[DDR_CH3], - sizeof(board_cfg->dqs_map[DDR_CH3])); - - if (half_populated) - return; - - memcpy(&mem_cfg->DqMapCpu2DramCh4, &board_cfg->dq_map[DDR_CH4], - sizeof(board_cfg->dq_map[DDR_CH4])); - memcpy(&mem_cfg->DqsMapCpu2DramCh4, &board_cfg->dqs_map[DDR_CH4], - sizeof(board_cfg->dqs_map[DDR_CH4])); - - memcpy(&mem_cfg->DqMapCpu2DramCh5, &board_cfg->dq_map[DDR_CH5], - sizeof(board_cfg->dq_map[DDR_CH5])); - memcpy(&mem_cfg->DqsMapCpu2DramCh5, &board_cfg->dqs_map[DDR_CH5], - sizeof(board_cfg->dqs_map[DDR_CH5])); - - memcpy(&mem_cfg->DqMapCpu2DramCh6, &board_cfg->dq_map[DDR_CH6], - sizeof(board_cfg->dq_map[DDR_CH6])); - memcpy(&mem_cfg->DqsMapCpu2DramCh6, &board_cfg->dqs_map[DDR_CH6], - sizeof(board_cfg->dqs_map[DDR_CH6])); - - memcpy(&mem_cfg->DqMapCpu2DramCh7, &board_cfg->dq_map[DDR_CH7], - sizeof(board_cfg->dq_map[DDR_CH7])); - memcpy(&mem_cfg->DqsMapCpu2DramCh7, &board_cfg->dqs_map[DDR_CH7], - sizeof(board_cfg->dqs_map[DDR_CH7])); -} - -static void meminit_channels(FSP_M_CONFIG *mem_cfg, - const struct mb_cfg *board_cfg, - uintptr_t spd_data_ptr, - bool half_populated) -{ - uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ - - /* Channel 0 */ - mem_cfg->DisableDimmMc0Ch0 = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - mem_cfg->MemorySpdPtr01 = 0; - - /* Channel 1 */ - mem_cfg->DisableDimmMc0Ch1 = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_data_ptr; - mem_cfg->MemorySpdPtr03 = 0; - - /* Channel 2 */ - mem_cfg->DisableDimmMc0Ch2 = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_data_ptr; - mem_cfg->MemorySpdPtr05 = 0; - - /* Channel 3 */ - mem_cfg->DisableDimmMc0Ch3 = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_data_ptr; - mem_cfg->MemorySpdPtr07 = 0; - - if (half_populated) { - printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); - dimm_cfg = DISABLE_BOTH_DIMMS; - spd_data_ptr = 0; - } - - /* Channel 4 */ - mem_cfg->DisableDimmMc1Ch0 = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_data_ptr; - mem_cfg->MemorySpdPtr09 = 0; - - /* Channel 5 */ - mem_cfg->DisableDimmMc1Ch1 = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_data_ptr; - mem_cfg->MemorySpdPtr11 = 0; - - /* Channel 6 */ - mem_cfg->DisableDimmMc1Ch2 = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_data_ptr; - mem_cfg->MemorySpdPtr13 = 0; - - /* Channel 7 */ - mem_cfg->DisableDimmMc1Ch3 = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_data_ptr; - mem_cfg->MemorySpdPtr15 = 0; - - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); -} - -/* Initialize onboard memory configurations for lpddr4x */ -void memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct mb_cfg *board_cfg, - const struct spd_info *spd_info, - bool half_populated) -{ - if (spd_info->read_type == READ_SMBUS) { - for (int i = 0; i < NUM_DIMM_SLOT; i++) - mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; - meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); - } else { - size_t spd_data_len = 0; - uintptr_t spd_data_ptr = 0; - - memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); - get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); - - mem_cfg->MemorySpdDataLen = spd_data_len; - meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); - } - - mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config; - mem_cfg->ECT = board_cfg->ect; - mem_cfg->UserBd = board_cfg->UserBd; - mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; } diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c7e10a9..1041507 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -53,6 +53,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM @@ -249,4 +250,16 @@ help Enable displays to be detected over Type-C ports during boot. +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config MRC_CHANNEL_WIDTH + int + default 16 + endif diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 4a52298..5ec50ea 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -6,150 +6,113 @@ #include <stddef.h> #include <stdint.h> #include <fsp/soc_binding.h> +#include <intelblocks/meminit.h> -#define BITS_PER_BYTE 8 - -#define LPDDR4X_CHANNELS 8 -#define LPDDR4X_BYTES_PER_CHANNEL 2 - -#define DDR4_CHANNELS 2 -#define DDR4_BYTES_PER_CHANNEL 8 - -enum mem_topology { - MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */ - SODIMM, /* Supports reading SPD using SMBus (only for DDR4). */ - MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ +enum mem_type { + MEM_TYPE_DDR4, + MEM_TYPE_LP4X, }; -enum ddr_memtype { - MEMTYPE_DDR4, /* Uses DDR4 memory */ - MEMTYPE_LPDDR4X, /* Uses LPDDR4x memory */ +struct ddr4_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; + uint8_t dq2[BITS_PER_BYTE]; + uint8_t dq3[BITS_PER_BYTE]; + uint8_t dq4[BITS_PER_BYTE]; + uint8_t dq5[BITS_PER_BYTE]; + uint8_t dq6[BITS_PER_BYTE]; + uint8_t dq7[BITS_PER_BYTE]; }; -enum md_spd_loc { - /* Read SPD from pointer provided to memory location. */ - SPD_MEMPTR, - /* Read SPD using index into spd.bin in CBFS. */ - SPD_CBFS, +struct ddr4_dqs { + uint8_t dqs0; + uint8_t dqs1; + uint8_t dqs2; + uint8_t dqs3; + uint8_t dqs4; + uint8_t dqs5; + uint8_t dqs6; + uint8_t dqs7; }; -struct spd_info { - enum mem_topology topology; +struct ddr4_dq_map { + struct ddr4_dq ddr0; + struct ddr4_dq ddr1; +}; - /* SPD info for Memory down topology */ - enum md_spd_loc md_spd_loc; +struct ddr4_dqs_map { + struct ddr4_dqs ddr0; + struct ddr4_dqs ddr1; +}; + +struct lp4x_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; +}; + +struct lp4x_dqs { + uint8_t dqs0; + uint8_t dqs1; +}; + +struct lp4x_dq_map { + struct lp4x_dq ddr0; + struct lp4x_dq ddr1; + struct lp4x_dq ddr2; + struct lp4x_dq ddr3; + struct lp4x_dq ddr4; + struct lp4x_dq ddr5; + struct lp4x_dq ddr6; + struct lp4x_dq ddr7; +}; + +struct lp4x_dqs_map { + struct lp4x_dqs ddr0; + struct lp4x_dqs ddr1; + struct lp4x_dqs ddr2; + struct lp4x_dqs ddr3; + struct lp4x_dqs ddr4; + struct lp4x_dqs ddr5; + struct lp4x_dqs ddr6; + struct lp4x_dqs ddr7; +}; + +struct mem_ddr4_config { + bool dq_pins_interleaved; +}; + +struct mb_cfg { + enum mem_type type; + union { - /* Used for SPD_CBFS */ - uint8_t cbfs_index; - - struct { - /* Used for SPD_MEMPTR */ - uintptr_t data_ptr; - size_t data_len; - }; + /* + * DQ CPU<>DRAM map: + * Index of the array represents DQ# on the CPU and the value represents DQ# on + * the DRAM part. + */ + uint8_t dq_map[CONFIG_DATA_BUS_WIDTH]; + struct lp4x_dq_map lp4x_dq_map; + struct ddr4_dq_map ddr4_dq_map; }; - /* - * SPD info for SODIMM topology. - * Leave addr_dimmN as 0 for any DIMMs that are not populated. - */ - struct { - /* SMBus address for DIMM0 within the channel. */ - uint8_t addr_dimm0; - /* SMBus address for DIMM1 within the channel. */ - uint8_t addr_dimm1; - } smbus_info[DDR4_CHANNELS]; -}; - -/* Board-specific memory configuration information */ -struct lpddr4x_cfg { - /* - * DQ CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[7-0]_DQ[1-0][7:0], where - * DDR[7-0] : LPDDR4x channel # - * DQ[1-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - - /* - * DQS CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQS pairs(P/N) per channel. Thus, dqs_map is - * represented as DDR[7-0]_DQS[1:0], where - * DDR[7-0] : LPDDR4x channel # - * DQS[1-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; - /* - * Early Command Training Enable/Disable Control - * 1 = enable, 0 = disable - */ - uint8_t ect; -}; - -/* Board-specific memory configuration information for DDR4 memory variant */ -struct mb_ddr4_cfg { - /* - * DQ CPU<>DRAM map: - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[1-0]_DQ[7-0][7:0], where - * DDR[1-0] : DDR4 channel # - * DQ[7-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - /* - * DQS CPU<>DRAM map: - * DDR4 memory interface has 8 DQS pairs per channel. Thus, dqs_map is represented as - * DDR[1-0]_DQS[7-0], where - * DDR[1-0] : DDR4 channel # - * DQS[7-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQS pin# on the memory part. - */ - uint8_t dqs_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL]; - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ - uint8_t dq_pins_interleaved; - /* - * Early Command Training Enable/Disable Control - * 1 = enable, 0 = disable - */ - uint8_t ect; -}; - -/* DDR Memory Information - Supports DDR4 and LPDDR4x */ -struct ddr_memory_cfg { - enum ddr_memtype mem_type; union { - const struct mb_ddr4_cfg *ddr4_cfg; - const struct lpddr4x_cfg *lpddr4_cfg; + /* + * DQS CPU<>DRAM map: + * Index of the array represents DQS# on the CPU and the value represents DQS# + * on the DRAM part. + */ + uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE]; + struct lp4x_dqs_map lp4x_dqs_map; + struct ddr4_dqs_map ddr4_dqs_map; }; + + /* Early Command Training Enable/Disable Control */ + bool ect; + + struct mem_ddr4_config ddr4_config; }; -/* Initialize LPDDR4x memory configurations */ -void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *spd, bool half_populated); +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated); -/* Initialize DDR4 memory configurations */ -void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *spd, const bool half_populated); - -/* Determine which DDR memory is used and call appropriate init routine */ -void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, - const struct spd_info *info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 7e830f0..ab32b79 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -4,449 +4,132 @@ #include <console/console.h> #include <fsp/util.h> #include <soc/meminit.h> -#include <spd_bin.h> -#include <string.h> -/* If memory is half-populated, then upper half of the channels need to be left empty. */ -#define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ - ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) +#define LP4X_CH_WIDTH 16 +#define LP4X_CHANNELS CHANNEL_COUNT(LP4X_CH_WIDTH) -/* - * Translate DDR4 channel # to FSP UPD index # for the channel. - * Channel 0 -> Index 0 - * Channel 1 -> Index 4 - * Index 1-3 and 5-7 are unused. - */ -#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) +#define DDR4_CH_WIDTH 64 +#define DDR4_CHANNELS CHANNEL_COUNT(DDR4_CH_WIDTH) -enum dimm_enable_options { - ENABLE_BOTH_DIMMS = 0, - DISABLE_DIMM0 = 1, - DISABLE_DIMM1 = 2, - DISABLE_BOTH_DIMMS = 3 -}; - -static uint8_t get_dimm_cfg(uintptr_t dimm0, uintptr_t dimm1) +static void meminit_lp4x(FSP_M_CONFIG *mem_cfg) { - if (dimm0 && dimm1) - return ENABLE_BOTH_DIMMS; - if (!dimm0 && !dimm1) - return DISABLE_BOTH_DIMMS; - if (!dimm1) - return DISABLE_DIMM1; - if (!dimm0) - die("Disabling of only dimm0 is not supported!\n"); - - return DISABLE_BOTH_DIMMS; -} - -static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, - uintptr_t spd_dimm1) -{ - uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1); - - switch (channel) { - case 0: - mem_cfg->DisableDimmCh0 = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_dimm0; - mem_cfg->MemorySpdPtr01 = spd_dimm1; - break; - - case 1: - mem_cfg->DisableDimmCh1 = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_dimm0; - mem_cfg->MemorySpdPtr03 = spd_dimm1; - break; - - case 2: - mem_cfg->DisableDimmCh2 = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_dimm0; - mem_cfg->MemorySpdPtr05 = spd_dimm1; - break; - - case 3: - mem_cfg->DisableDimmCh3 = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_dimm0; - mem_cfg->MemorySpdPtr07 = spd_dimm1; - break; - - case 4: - mem_cfg->DisableDimmCh4 = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_dimm0; - mem_cfg->MemorySpdPtr09 = spd_dimm1; - break; - - case 5: - mem_cfg->DisableDimmCh5 = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_dimm0; - mem_cfg->MemorySpdPtr11 = spd_dimm1; - break; - - case 6: - mem_cfg->DisableDimmCh6 = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_dimm0; - mem_cfg->MemorySpdPtr13 = spd_dimm1; - break; - - case 7: - mem_cfg->DisableDimmCh7 = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_dimm0; - mem_cfg->MemorySpdPtr15 = spd_dimm1; - break; - - default: - die("Invalid channel: %d\n", channel); - } -} - -static inline void init_spd_upds_empty(FSP_M_CONFIG *mem_cfg, int channel) -{ - init_spd_upds(mem_cfg, channel, 0, 0); -} - -static inline void init_spd_upds_dimm0(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0) -{ - init_spd_upds(mem_cfg, channel, spd_dimm0, 0); -} - -static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, const uint8_t *dq_byte0, - const uint8_t *dq_byte1) -{ - uint8_t *dq_upd; - - switch (byte_pair) { - case 0: - dq_upd = mem_cfg->DqMapCpu2DramCh0; - break; - case 1: - dq_upd = mem_cfg->DqMapCpu2DramCh1; - break; - case 2: - dq_upd = mem_cfg->DqMapCpu2DramCh2; - break; - case 3: - dq_upd = mem_cfg->DqMapCpu2DramCh3; - break; - case 4: - dq_upd = mem_cfg->DqMapCpu2DramCh4; - break; - case 5: - dq_upd = mem_cfg->DqMapCpu2DramCh5; - break; - case 6: - dq_upd = mem_cfg->DqMapCpu2DramCh6; - break; - case 7: - dq_upd = mem_cfg->DqMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - if (dq_byte0 && dq_byte1) { - memcpy(dq_upd, dq_byte0, BITS_PER_BYTE); - memcpy(dq_upd + BITS_PER_BYTE, dq_byte1, BITS_PER_BYTE); - } else { - memset(dq_upd, 0, BITS_PER_BYTE * 2); - } -} - -static inline void init_dq_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dq_upds(mem_cfg, byte_pair, NULL, NULL); -} - -static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, uint8_t dqs_byte0, - uint8_t dqs_byte1) -{ - uint8_t *dqs_upd; - - switch (byte_pair) { - case 0: - dqs_upd = mem_cfg->DqsMapCpu2DramCh0; - break; - case 1: - dqs_upd = mem_cfg->DqsMapCpu2DramCh1; - break; - case 2: - dqs_upd = mem_cfg->DqsMapCpu2DramCh2; - break; - case 3: - dqs_upd = mem_cfg->DqsMapCpu2DramCh3; - break; - case 4: - dqs_upd = mem_cfg->DqsMapCpu2DramCh4; - break; - case 5: - dqs_upd = mem_cfg->DqsMapCpu2DramCh5; - break; - case 6: - dqs_upd = mem_cfg->DqsMapCpu2DramCh6; - break; - case 7: - dqs_upd = mem_cfg->DqsMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - dqs_upd[0] = dqs_byte0; - dqs_upd[1] = dqs_byte1; -} - -static inline void init_dqs_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dqs_upds(mem_cfg, byte_pair, 0, 0); -} - -static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) -{ - struct region_device spd_rdev; - - printk(BIOS_DEBUG, "SPD INDEX = %u\n", index); - if (get_spd_cbfs_rdev(&spd_rdev, index) < 0) - die("spd.bin not found or incorrect index\n"); - - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - *len = region_device_sz(&spd_rdev); - *data = (uintptr_t)rdev_mmap_full(&spd_rdev); -} - -static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *len) -{ - if (info->md_spd_loc == SPD_MEMPTR) { - *data = info->data_ptr; - *len = info->data_len; - } else if (info->md_spd_loc == SPD_CBFS) { - read_spd_from_cbfs(info->cbfs_index, data, len); - } else { - die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); - } - - print_spd_info((uint8_t *) *data); -} - -void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *info, bool half_populated) - -{ - size_t spd_len; - uintptr_t spd_data; - int i; - - if (info->topology != MEMORY_DOWN) - die("LPDDR4x only support memory-down topology.\n"); - /* LPDDR4x does not allow interleaved memory */ mem_cfg->DqPinsInterleaved = 0; - mem_cfg->ECT = board_cfg->ect; - - read_md_spd(info, &spd_data, &spd_len); - mem_cfg->MemorySpdDataLen = spd_len; - - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_spd_upds_empty(mem_cfg, i); - else - init_spd_upds_dimm0(mem_cfg, i, spd_data); - } - - /* - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh2 --> dq_map[CHAN=2][0-1] - * DqMapCpu2DramCh3 --> dq_map[CHAN=3][0-1] - * DqMapCpu2DramCh4 --> dq_map[CHAN=4][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=5][0-1] - * DqMapCpu2DramCh6 --> dq_map[CHAN=6][0-1] - * DqMapCpu2DramCh7 --> dq_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dq_upds_empty(mem_cfg, i); - else - init_dq_upds(mem_cfg, i, board_cfg->dq_map[i][0], - board_cfg->dq_map[i][1]); - } - - /* - * LPDDR4x memory interface has 2 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=2][0-1] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=3][0-1] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=4][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=5][0-1] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=6][0-1] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dqs_upds_empty(mem_cfg, i); - else - init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i][0], - board_cfg->dqs_map[i][1]); - } } -static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) +static void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mem_ddr4_config *ddr4_cfg) { - unsigned int i; - - blk->addr_map[0] = info->smbus_info[0].addr_dimm0; - blk->addr_map[1] = info->smbus_info[0].addr_dimm1; - blk->addr_map[2] = info->smbus_info[1].addr_dimm0; - blk->addr_map[3] = info->smbus_info[1].addr_dimm1; - - get_spd_smbus(blk); - - /* - * SPD gets printed only if: - * a) mainboard provides a non-zero SMBus address and - * b) SPD is successfully read using the SMBus address - */ - for (i = 0; i < ARRAY_SIZE(blk->addr_map); i++) { - if (blk->spd_array[i] != NULL) - print_spd_info((uint8_t *)blk->spd_array[i]); - } + mem_cfg->DqPinsInterleaved = ddr4_cfg->dq_pins_interleaved; } -static void ddr4_get_spd(unsigned int channel, const uintptr_t *spd_md_data, - const struct spd_block *spd_sodimm_blk, - const struct spd_info *info, - const bool half_populated, uintptr_t *spd_dimm0, - uintptr_t *spd_dimm1) +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_DDR4] = { + .num_phys_channels = DDR4_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 4, + }, + .md_phy_masks = { + /* + * Only physical channel 0 is populated in case of half-populated + * configuration. + */ + .half_channel = BIT(0), + /* In mixed topologies, channel 0 is always memory-down. */ + .mixed_topo = BIT(0), + }, + }, + [MEM_TYPE_LP4X] = { + .num_phys_channels = LP4X_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP4x does not support mixed topologies. */ + }, + }, +}; + +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) { - if (channel == 0) { - /* For mixed topology, channel 0 can only be Memory_Down */ - if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { - *spd_dimm0 = *spd_md_data; - *spd_dimm1 = 0; - } else if (info->topology == SODIMM) { - *spd_dimm0 = (uintptr_t)spd_sodimm_blk->spd_array[0]; - *spd_dimm1 = (uintptr_t)spd_sodimm_blk->spd_array[1]; - } else - die("Undefined memory topology on Channel 0.\n"); - } else if (channel == 1) { - if (half_populated) { - *spd_dimm0 = *spd_dimm1 = 0; - } else if (info->topology == MEMORY_DOWN) { - *spd_dimm0 = *spd_md_data; - *spd_dimm1 = 0; - /* For mixed topology, channel 1 can only be SODIMM */ - } else if ((info->topology == SODIMM) || (info->topology == MIXED)) { - *spd_dimm0 = (uintptr_t)spd_sodimm_blk->spd_array[2]; - *spd_dimm1 = (uintptr_t)spd_sodimm_blk->spd_array[3]; - } else - die("Undefined memory topology on channel 1.\n"); - } else - die("Unsupported channels.\n"); -} + struct board_cfg board_cfg = { + .dq_map = mb_cfg->dq_map, + .dqs_map = mb_cfg->dqs_map, + .half_populated = half_populated, + .mem_type = mb_cfg->type, + .spd_info = spd_info, + }; -/* Initialize DDR4 memory configurations */ -void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *info, const bool half_populated) -{ - uintptr_t spd_md_data; - size_t spd_md_len; - uintptr_t spd_dimm0 = 0; - uintptr_t spd_dimm1 = 0; - struct spd_block spd_sodimm_blk; - unsigned int i; - unsigned int index = 0; + struct fspm_upd_ptrs upd_ptrs = { + .dq = { + &mem_cfg->DqMapCpu2DramCh0, + &mem_cfg->DqMapCpu2DramCh1, + &mem_cfg->DqMapCpu2DramCh2, + &mem_cfg->DqMapCpu2DramCh3, + &mem_cfg->DqMapCpu2DramCh4, + &mem_cfg->DqMapCpu2DramCh5, + &mem_cfg->DqMapCpu2DramCh6, + &mem_cfg->DqMapCpu2DramCh7, + }, + .dqs = { + &mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1, + &mem_cfg->DqsMapCpu2DramCh2, + &mem_cfg->DqsMapCpu2DramCh3, + &mem_cfg->DqsMapCpu2DramCh4, + &mem_cfg->DqsMapCpu2DramCh5, + &mem_cfg->DqsMapCpu2DramCh6, + &mem_cfg->DqsMapCpu2DramCh7, + }, + .disable_dimm = { + &mem_cfg->DisableDimmCh0, + &mem_cfg->DisableDimmCh1, + &mem_cfg->DisableDimmCh2, + &mem_cfg->DisableDimmCh3, + &mem_cfg->DisableDimmCh4, + &mem_cfg->DisableDimmCh5, + &mem_cfg->DisableDimmCh6, + &mem_cfg->DisableDimmCh7, + }, + .spd = { + [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, + [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, + [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, + [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, + [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, + [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, + [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, + [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + }, + .spd_len = &mem_cfg->MemorySpdDataLen, + }; - /* Early Command Training Enabled */ - mem_cfg->ECT = board_cfg->ect; - mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + mem_init_fspm_upds(&board_cfg, &soc_mem_cfg[0], &upd_ptrs); - if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { - read_md_spd(info, &spd_md_data, &spd_md_len); - mem_cfg->MemorySpdDataLen = spd_md_len; - } + mem_cfg->ECT = mb_cfg->ect; - if ((info->topology == SODIMM) || (info->topology == MIXED)) { - read_sodimm_spd(info, &spd_sodimm_blk); - if ((info->topology == MIXED) && - (mem_cfg->MemorySpdDataLen != spd_sodimm_blk.len)) - die("Mixed topology has incorrect length.\n"); - else - mem_cfg->MemorySpdDataLen = spd_sodimm_blk.len; - } - - for (i = 0; i < DDR4_CHANNELS; i++) { - ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, - half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); - } - - /* - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for every dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=0][2-3] - * DqMapCpu2DramCh2 --> dq_map[CHAN=0][4-5] - * DqMapCpu2DramCh3 --> dq_map[CHAN=0][6-7] - * DqMapCpu2DramCh4 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=1][2-3] - * DqMapCpu2DramCh6 --> dq_map[CHAN=1][4-5] - * DqMapCpu2DramCh7 --> dq_map[CHAN=1][6-7] - */ - - /* - * DDR4 memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for every dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] - */ - - for (i = 0; i < DDR4_CHANNELS; i++) { - for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b += 2) { - if (half_populated && (i == 1)) { - init_dq_upds_empty(mem_cfg, index); - init_dqs_upds_empty(mem_cfg, index); - } else { - init_dq_upds(mem_cfg, index, board_cfg->dq_map[i][b], - board_cfg->dq_map[i][b+1]); - init_dqs_upds(mem_cfg, index, board_cfg->dqs_map[i][b], - board_cfg->dqs_map[i][b+1]); - } - index++; - } - } -} - -void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, - const struct spd_info *info, bool half_populated) -{ - switch (board_cfg->mem_type) { - case MEMTYPE_DDR4: - meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, half_populated); + switch (mb_cfg->type) { + case MEM_TYPE_DDR4: + meminit_ddr4(mem_cfg, &mb_cfg->ddr4_config); break; - case MEMTYPE_LPDDR4X: - meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, half_populated); + case MEM_TYPE_LP4X: + meminit_lp4x(mem_cfg); break; default: - die("Unsupported memory type = %d!\n", board_cfg->mem_type); + die("Unsupported memory type(%d)\n", mb_cfg->type); } + } -- To view, visit https://review.coreboot.org/c/coreboot/+/49041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9daed06b9d09b2c274f93e0a4cbf608f0f334a60 Gerrit-Change-Number: 49041 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/google: enable Eotp feature
by Shaoming Chen (Code Review) 01 Jan '21

01 Jan '21

Shaoming Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48868 ) Change subject: src/mainboard/google: enable Eotp feature ...................................................................... src/mainboard/google: enable Eotp feature enable Eotp feature for anx7625 BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48868/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 4220810d..e6fac84 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -160,8 +160,12 @@ u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM); - if (CONFIG(DRIVER_ANALOGIX_ANX7625)) +/* if (CONFIG(DRIVER_ANALOGIX_ANX7625)) mipi_dsi_flags |= MIPI_DSI_MODE_EOT_PACKET; +*/ + /* if bit9 = 1, then disable EoT packets, other enable EoT pachets in HS mode */ + printk(BIOS_INFO, "mipi_dsi_flags = 0x%x \n", mipi_dsi_flags); + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, panel->s->init) < 0) { printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/48868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa Gerrit-Change-Number: 48868 Gerrit-PatchSet: 1 Gerrit-Owner: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: Add panel api after dsi start
by jitao shi (Code Review) 01 Jan '21

01 Jan '21

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47380 ) Change subject: mb/google/kukui: Add panel api after dsi start ...................................................................... mb/google/kukui: Add panel api after dsi start Some bridge chip or panel require dsi signal output before mipirx enable. Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d --- M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/kukui/panel.h M src/mainboard/google/kukui/panel_anx7625.c 3 files changed, 30 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47380/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 268b7ca..6ac0530 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -96,6 +96,12 @@ mdelay(6); } +static void post_power_on_panel(struct panel_description *panel) +{ + if (panel->post_power_on) + panel->post_power_on(); +} + struct panel_description *get_panel_from_cbfs(struct panel_description *desc) { /* The CBFS name will be panel-{MANUFACTURER}-${PANEL_NAME}, @@ -168,6 +174,9 @@ printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); return false; } + + post_power_on_panel(panel); + mtk_ddp_mode_set(edid); set_vbe_mode_info_valid(edid, 0); set_vbe_framebuffer_orientation(panel->s->orientation); diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/panel.h index 7ae31dd..c60c577 100644 --- a/src/mainboard/google/kukui/panel.h +++ b/src/mainboard/google/kukui/panel.h @@ -21,6 +21,7 @@ const char *name; /* Panel name for constructing CBFS file name */ struct panel_serializable_data *s; void (*power_on)(void); /* Callback to turn on panel */ + void (*post_power_on)(void); /* Callback to run after turn on panel */ }; /* Returns the panel description from given ID. */ diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index cc41c86..d9df6f0 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -27,21 +27,33 @@ gpio_output(GPIO_PP3300_LCM_EN, 1); } -static void dummy_power_on(void) -{ - /* The panel has been already powered on when getting panel information - * so we should do nothing here. - */ -} - static struct panel_serializable_data anx7625_data = { .orientation = LB_FB_ORIENTATION_NORMAL, .init = { INIT_END_CMD }, }; +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static void start_anx7625(void) +{ + u8 i2c_bus = 4; + struct edid *edid = &anx7625_data.edid; + + printk(BIOS_ERR, "start display start_anx7625\n"); + + if (anx7625_dp_start(i2c_bus, edid) < 0) + printk(BIOS_ERR, "Can't start display via ANX7625.\n"); +} + static struct panel_description anx7625_panel = { .s = &anx7625_data, - .power_on = dummy_power_on, + .power_on = dummy_power_on, + .post_power_on = start_anx7625, }; struct panel_description *get_panel_description(int panel_id) @@ -61,9 +73,5 @@ printk(BIOS_ERR, "Can't get panel's edid.\n"); return NULL; } - if (anx7625_dp_start(i2c_bus, edid) < 0) { - printk(BIOS_ERR, "Can't start display via ANX7625.\n"); - return NULL; - } return &anx7625_panel; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d Gerrit-Change-Number: 47380 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021