coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
by Michael Niewöhner (Code Review) 01 Jan '21

01 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49046 ) Change subject: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/49046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Gerrit-Change-Number: 49046 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jan 2021 21:19:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Michael Niewöhner (Code Review) 01 Jan '21

01 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jan 2021 21:19:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Michael Niewöhner (Code Review) 01 Jan '21

01 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 ) Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... Patch Set 2: (1 comment) This change is ready for review. https://review.coreboot.org/c/coreboot/+/49045/2/src/acpi/acpi.c File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49045/2/src/acpi/acpi.c@1689 PS2, Line 1689: case LPIT: /* ACPI 5.1 upto 6.3: 0 */ > . Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jan 2021 21:19:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: add panel and backlight configuration code
by Nico Huber (Code Review) 01 Jan '21

01 Jan '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48749 ) Change subject: soc/intel/cnl: add panel and backlight configuration code ...................................................................... soc/intel/cnl: add panel and backlight configuration code Add code for panel and backlight configuration. Tested successfully with libgfxinit on Clevo L141CU. Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/graphics.c 3 files changed, 69 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..e060581 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -36,6 +36,7 @@ ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 492ebca..2727aa2 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -5,6 +5,7 @@ #include <intelblocks/cfg.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -437,6 +438,10 @@ * Only override CPU flex ratio if don't want to boot with non-turbo max. */ uint8_t cpu_ratio_override; + + struct i915_gpu_panel_config panel_cfg; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c new file mode 100644 index 0000000..93a84c2 --- /dev/null +++ b/src/soc/intel/cannonlake/graphics.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/resource.h> +#include <drivers/intel/gma/i915_reg.h> +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> +#include <types.h> + +void graphics_soc_panel_init(struct device *dev) +{ + const struct soc_intel_cannonlake_config *conf = dev->chip_info; + const struct i915_gpu_panel_config *panel_cfg; + const struct resource *mmio_res; + void *mmio; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + if (!conf) + return; + + panel_cfg = &conf->panel_cfg; + + mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + mmio = (void *)(uintptr_t)mmio_res->base; + + /* Panel timings */ + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + /* Backlight */ + if (panel_cfg->backlight_pwm_hz) { + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); + } +} + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_cannonlake_config *const chip = dev->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Gerrit-Change-Number: 48749 Gerrit-PatchSet: 32 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings
by Nico Huber (Code Review) 01 Jan '21

01 Jan '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48885 ) Change subject: nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings ...................................................................... nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings There are multiple different devicetree setting formats for graphics panel settings present in coreboot. Replace the ones for the platforms that already have (mostly) unified gma/graphics setup code by a unified struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt the devicetrees accordingly. Always ensure that values don't overflow by applying appropriate masks. The remaining platforms implementing panel settings (GM45, i945, ILK and SNB) can be migrated later after unifying their gma/graphics setup code. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/gma.h M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/google/slippy/variants/falco/overridetree.cb M src/mainboard/google/slippy/variants/leon/overridetree.cb M src/mainboard/google/slippy/variants/peppy/overridetree.cb M src/mainboard/google/slippy/variants/wolf/overridetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/graphics.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/gma.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/graphics.c 32 files changed, 247 insertions(+), 246 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/gma/gma.h b/src/drivers/intel/gma/gma.h index d7a336c..ee7d730 100644 --- a/src/drivers/intel/gma/gma.h +++ b/src/drivers/intel/gma/gma.h @@ -11,6 +11,20 @@ u32 did[5]; }; +/* Devicetree panel configuration */ +struct i915_gpu_panel_config { + unsigned int up_delay_ms; + unsigned int down_delay_ms; + unsigned int cycle_delay_ms; + unsigned int backlight_on_delay_ms; + unsigned int backlight_off_delay_ms; + unsigned int backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } backlight_polarity; +}; + #define GMA_STATIC_DISPLAYS(ssc) { \ .use_spread_spectrum_clock = (ssc), \ .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index b51c73c..433bc22 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -1,11 +1,13 @@ chip soc/intel/skylake # Enable Panel as eDP and configure power delays - register "gpu_pp_up_delay_ms" = "210" # T3 - register "gpu_pp_down_delay_ms" = "500" # T10 - register "gpu_pp_cycle_delay_ms" = "5000" # T12 - register "gpu_pp_backlight_on_delay_ms" = "1" # T7 - register "gpu_pp_backlight_off_delay_ms" = "200" # T9 + register "panel_cfg" = "{ + .up_delay_ms = 210, // T3 + .down_delay_ms = 500, // T10 + .cycle_delay_ms = 5000, // T12 + .backlight_on_delay_ms = 1, // T7 + .backlight_off_delay_ms = 200, // T9 + }" # Enable deep Sx states register "deep_s3_enable_ac" = "1" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 808ece0..29f57bd 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -1,13 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" # T3 - register "gpu_pp_down_delay_ms" = " 0" # T10 - register "gpu_pp_cycle_delay_ms" = "500" # T12 - register "gpu_pp_backlight_on_delay_ms" = " 50" # T7 - register "gpu_pp_backlight_off_delay_ms" = " 0" # T9 - - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, // T3 + .down_delay_ms = 0, // T10 + .cycle_delay_ms = 500, // T12 + .backlight_on_delay_ms = 50, // T7 + .backlight_off_delay_ms = 0, // T9 + .backlight_pwm_hz = 200, + }" # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 26a5336..8bf2c12 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,9 +12,6 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - register "s0ix_enable" = "1" device cpu_cluster 0 on diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index cb7fb62..62e42b1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "7" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 746ec9a..174463d 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "210" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 5423043..6762eb4 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "7" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" register "s0ix_enable" = "0" diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 19c0ca0..ca5d616 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "50" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 50, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index cb7fb62..62e42b1 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "7" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 989b887..34a785b 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -3,12 +3,14 @@ # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "500" - register "gpu_panel_power_up_delay_ms" = "200" - register "gpu_panel_power_down_delay_ms" = "50" - register "gpu_panel_power_backlight_on_delay_ms" = "200" - register "gpu_panel_power_backlight_off_delay_ms" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 200, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" register "vr_slow_ramp_rate_set" = "3" register "vr_slow_ramp_rate_enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 0e76de1..c0531fa 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -3,13 +3,14 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "100" - register "gpu_pp_down_delay_ms" = "500" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Enable deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 8c31f9ac..e9d5a35 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -1,12 +1,13 @@ chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 127334e..5a48c5d 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -3,13 +3,14 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Enable deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index a14e927..d3e351a 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -3,12 +3,14 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = "50" - register "gpu_pp_cycle_delay_ms" = "600" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 600, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ff117c8..162b437 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -3,12 +3,14 @@ # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = "500" - register "gpu_pp_cycle_delay_ms" = "600" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 500, + .cycle_delay_ms = 600, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index a6fab83..99cae7a 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -11,9 +11,6 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - register "ec_present" = "true" register "usb_xhci_on_resume" = "true" diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index 54ae615..fc77345 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "60" - register "gpu_panel_power_down_delay_ms" = "60" - register "gpu_panel_power_backlight_on_delay_ms" = "210" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 60, + .down_delay_ms = 60, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb index 9c45f00..1d50086 100644 --- a/src/mainboard/google/slippy/variants/leon/overridetree.cb +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "210" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index 47edc62..e732a92 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "400" - register "gpu_panel_power_up_delay_ms" = "40" - register "gpu_panel_power_down_delay_ms" = "15" - register "gpu_panel_power_backlight_on_delay_ms" = "210" - register "gpu_panel_power_backlight_off_delay_ms" = "210" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index 43bdf56..8246947 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "500" - register "gpu_panel_power_up_delay_ms" = "200" - register "gpu_panel_power_down_delay_ms" = "50" - register "gpu_panel_power_backlight_on_delay_ms" = "1" - register "gpu_panel_power_backlight_off_delay_ms" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 9baec90..712d75e 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -4,12 +4,14 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" - register "gpu_panel_power_backlight_off_delay_ms" = "1" - register "gpu_panel_power_backlight_on_delay_ms" = "1" - register "gpu_panel_power_cycle_delay_ms" = "500" - register "gpu_panel_power_down_delay_ms" = "50" - register "gpu_panel_power_up_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 200, + }" register "usb_xhci_on_resume" = "true" device cpu_cluster 0 on chip cpu/intel/haswell diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index e17807f..fb0442d 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -4,12 +4,14 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_power_backlight_off_delay_ms" = "1" - register "gpu_panel_power_backlight_on_delay_ms" = "1" - register "gpu_panel_power_cycle_delay_ms" = "500" - register "gpu_panel_power_down_delay_ms" = "50" - register "gpu_panel_power_up_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "220" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 220, + }" register "ec_present" = "true" device cpu_cluster 0x0 on chip cpu/intel/haswell diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 41943e7..cd5bb44 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -6,15 +6,14 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "500" - register "gpu_panel_power_up_delay_ms" = "200" - register "gpu_panel_power_down_delay_ms" = "50" - register "gpu_panel_power_backlight_on_delay_ms" = "200" - register "gpu_panel_power_backlight_off_delay_ms" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 200, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index c59df40..c3a9567 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -1,16 +1,17 @@ chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" - # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index b1c8d37..99102b6 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -3,7 +3,7 @@ #ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H #define NORTHBRIDGE_INTEL_HASWELL_CHIP_H -#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/gma.h> /* * Digital Port Hotplug Enable: @@ -17,17 +17,8 @@ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u16 gpu_panel_power_cycle_delay_ms; /* T4 time sequence */ - u16 gpu_panel_power_up_delay_ms; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay_ms; /* T3 time sequence */ - u16 gpu_panel_power_backlight_on_delay_ms; /* T5 time sequence */ - u16 gpu_panel_power_backlight_off_delay_ms; /* Tx time sequence */ - - unsigned int gpu_pch_backlight_pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } gpu_pch_backlight_polarity; + /* IGD panel configuration */ + struct i915_gpu_panel_config panel_cfg; bool gpu_ddi_e_connected; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 7adcfda..21053ec 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -243,6 +243,7 @@ static void gma_setup_panel(struct device *dev) { struct northbridge_intel_haswell_config *conf = config_of(dev); + const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg; u32 reg32; /* Setup Digital Port Hotplug */ @@ -257,30 +258,30 @@ /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff; + reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff; + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay_ms) { + if (panel_cfg->cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f; + reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } /* Enforce the PCH PWM function, as so does Linux. The CPU PWM controls are disabled after reset. */ - if (conf->gpu_pch_backlight_pwm_hz) { + if (panel_cfg->backlight_pwm_hz) { /* Reference clock is either 24MHz or 135MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ @@ -290,7 +291,7 @@ u32 south_chicken2; south_chicken2 = gtt_read(SOUTH_CHICKEN2); - if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + if (panel_cfg->backlight_pwm_hz > hz_limit) { pwm_increment = 16; south_chicken2 |= LPT_PWM_GRANULARITY; } else { @@ -299,7 +300,7 @@ } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz; printk(BIOS_INFO, "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", refclock / MHz, pwm_increment, pwm_period, @@ -309,7 +310,7 @@ gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); gtt_write(BLC_PWM_PCH_CTL1, - (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 6e4c82d..c94b7ef 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -4,6 +4,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include <commonlib/helpers.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> #include <soc/gpe.h> @@ -24,22 +25,6 @@ PNP_PERF_POWER, }; -struct soc_intel_apl_pp { - unsigned int up_delay_ms; - unsigned int down_delay_ms; - unsigned int cycle_delay_ms; - unsigned int backlight_on_delay_ms; - unsigned int backlight_off_delay_ms; -}; - -struct soc_intel_apl_blc { - unsigned int pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } polarity; -}; - struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ @@ -48,12 +33,13 @@ /* Common struct containing power limits configuration info */ struct soc_power_limits_config power_limits_config; - /* IGD panel configuration */ - struct soc_intel_apl_pp gpu_pp[2]; - /* Second backlight control shares logic with other pins (aka. display - utility pin). Be sure it's used for PWM before setting any value for - the secondary controls. */ - struct soc_intel_apl_blc gpu_blc[2]; + /* + * IGD panel configuration + * + * Second backlight control shares logic with other pins (aka. display utility pin). + * Be sure it's used for PWM before setting any secondary backlight value. + */ + struct i915_gpu_panel_config panel_cfg[2]; /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 4144479..c24ccdf 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -11,37 +11,37 @@ #include "chip.h" static void graphics_configure_panelpower( - const struct soc_intel_apl_pp *const pp, + const struct i915_gpu_panel_config *const panel_cfg, uint8_t *const mmio, const unsigned int panel_idx) { const unsigned int offset = panel_idx * 0x100; uint32_t reg32; - reg32 = (DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) << 4 & 0x1f0; + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; reg32 |= PANEL_POWER_RESET; write32(mmio + PCH_PP_CONTROL + offset, reg32); - reg32 = pp->up_delay_ms * 10 << 16; - reg32 |= pp->backlight_on_delay_ms * 10; + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; write32(mmio + PCH_PP_ON_DELAYS + offset, reg32); - reg32 = pp->down_delay_ms * 10 << 16; - reg32 |= pp->backlight_off_delay_ms * 10; + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32); } static void graphics_configure_backlight( - const struct soc_intel_apl_blc *const blc, + const struct i915_gpu_panel_config *const panel_cfg, uint8_t *const mmio, const unsigned int panel_idx) { - if (!blc->pwm_hz) + if (!panel_cfg->backlight_pwm_hz) return; - const unsigned int pwm_period = 19200 * 1000 / blc->pwm_hz; + const unsigned int pwm_period = 19200 * 1000 / panel_cfg->backlight_pwm_hz; write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period); write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2); write32(mmio + BXT_BLC_PWM_CTL(panel_idx), - (blc->polarity ? BXT_BLC_PWM_POLARITY : 0)); + panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0); /* Second backlight control uses display utility pin. */ if (panel_idx == 1) { @@ -68,9 +68,9 @@ return; mmio = (void *)(uintptr_t)mmio_res->base; - for (i = 0; i < ARRAY_SIZE(conf->gpu_pp); ++i) - graphics_configure_panelpower(&conf->gpu_pp[i], mmio, i); + for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i) + graphics_configure_panelpower(&conf->panel_cfg[i], mmio, i); - for (i = 0; i < ARRAY_SIZE(conf->gpu_blc); ++i) - graphics_configure_backlight(&conf->gpu_blc[i], mmio, i); + for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i) + graphics_configure_backlight(&conf->panel_cfg[i], mmio, i); } diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index b77cb71..9f6c58d 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -3,7 +3,7 @@ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ -#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/gma.h> #include <stdint.h> struct soc_intel_broadwell_config { @@ -18,19 +18,8 @@ u8 gpu_dp_c_hotplug; u8 gpu_dp_d_hotplug; - /* Panel power sequence timings */ - u16 gpu_panel_power_cycle_delay_ms; - u16 gpu_panel_power_up_delay_ms; - u16 gpu_panel_power_down_delay_ms; - u16 gpu_panel_power_backlight_on_delay_ms; - u16 gpu_panel_power_backlight_off_delay_ms; - - /* Panel backlight settings */ - unsigned int gpu_pch_backlight_pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } gpu_pch_backlight_polarity; + /* IGD panel configuration */ + struct i915_gpu_panel_config panel_cfg; /* * Graphics CD Clock Frequency diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 9866ed3..bbb6678 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -285,6 +285,7 @@ static void gma_setup_panel(struct device *dev) { config_t *conf = config_of(dev); + const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg; u32 reg32; /* Setup Digital Port Hotplug */ @@ -299,30 +300,30 @@ /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff; + reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff; + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay_ms) { + if (panel_cfg->cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f; + reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } /* So far all devices seem to use the PCH PWM function. The CPU PWM registers are all zero after reset. */ - if (conf->gpu_pch_backlight_pwm_hz) { + if (panel_cfg->backlight_pwm_hz) { /* For Lynx Point-LP: Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less @@ -333,7 +334,7 @@ u32 south_chicken2; south_chicken2 = gtt_read(SOUTH_CHICKEN2); - if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + if (panel_cfg->backlight_pwm_hz > hz_limit) { pwm_increment = 16; south_chicken2 |= 1 << 5; } else { @@ -342,7 +343,7 @@ } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz; printk(BIOS_INFO, "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", refclock / MHz, pwm_increment, pwm_period, @@ -352,7 +353,7 @@ gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); gtt_write(BLC_PWM_PCH_CTL1, - (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 7d9d934..027a2e2 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -6,7 +6,7 @@ #include <acpi/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> -#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -37,16 +37,7 @@ struct soc_power_limits_config power_limits_config; /* IGD panel configuration */ - unsigned int gpu_pp_up_delay_ms; - unsigned int gpu_pp_down_delay_ms; - unsigned int gpu_pp_cycle_delay_ms; - unsigned int gpu_pp_backlight_on_delay_ms; - unsigned int gpu_pp_backlight_off_delay_ms; - unsigned int gpu_pch_backlight_pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } gpu_pch_backlight_polarity; + struct i915_gpu_panel_config panel_cfg; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 46dc9db..d41c4aa 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -15,6 +15,7 @@ void graphics_soc_panel_init(struct device *dev) { struct soc_intel_skylake_config *conf = config_of(dev); + const struct i915_gpu_panel_config *panel_cfg; struct resource *mmio_res; uint8_t *base; u32 reg32; @@ -22,27 +23,29 @@ if (!conf) return; + panel_cfg = &conf->panel_cfg; + mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!mmio_res || !mmio_res->base) return; base = (void *)(uintptr_t)mmio_res->base; - reg32 = conf->gpu_pp_up_delay_ms * 10 << 16; - reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10; + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; write32(base + PCH_PP_ON_DELAYS, reg32); - reg32 = conf->gpu_pp_down_delay_ms * 10 << 16; - reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10; + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; write32(base + PCH_PP_OFF_DELAYS, reg32); reg32 = read32(base + PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f; + reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f; write32(base + PCH_PP_DIVISOR, reg32); /* So far all devices seem to use the PCH PWM function. The CPU PWM registers are all zero after reset. */ - if (conf->gpu_pch_backlight_pwm_hz) { + if (panel_cfg->backlight_pwm_hz) { /* Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ @@ -51,7 +54,7 @@ u32 south_chicken1; south_chicken1 = read32(base + SOUTH_CHICKEN1); - if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + if (panel_cfg->backlight_pwm_hz > hz_limit) { pwm_increment = 16; south_chicken1 &= ~1; } else { @@ -60,15 +63,12 @@ } write32(base + SOUTH_CHICKEN1, south_chicken1); - pwm_period = 24 * 1000 * 1000 / pwm_increment - / conf->gpu_pch_backlight_pwm_hz; + pwm_period = 24 * 1000 * 1000 / pwm_increment / panel_cfg->backlight_pwm_hz; /* Start with a 50% duty cycle. */ - write32(base + BLC_PWM_PCH_CTL2, - pwm_period << 16 | pwm_period / 2); + write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); write32(base + BLC_PWM_PCH_CTL1, - !!conf->gpu_pch_backlight_polarity << 29 | - BLM_PCH_PWM_ENABLE); + !!panel_cfg->backlight_polarity << 29 | BLM_PCH_PWM_ENABLE); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Gerrit-Change-Number: 48885 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI
by Nico Huber (Code Review) 01 Jan '21

01 Jan '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48750 ) Change subject: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI ...................................................................... Patch Set 34: (2 comments) https://review.coreboot.org/c/coreboot/+/48750/34//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48750/34//COMMIT_MSG@12 PS34, Line 12: Brightness control still requires ACPI code to link the EC events to it. : This will be done in a separate change later. > is this still true? the parent commit should be sufficient, no? The generic code can only tell how to act on events but it can't trigger them. But... maybe reword to avoid the misunderstanding "Keyboard brightness control still requires [...]" at least that's how I read it. https://review.coreboot.org/c/coreboot/+/48750/34/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb: https://review.coreboot.org/c/coreboot/+/48750/34/src/mainboard/clevo/cml-u… PS34, Line 69: GMA_STATIC_DISPLAYS Is this actually what you want? The macro was introduced to reduce the historic clutter to one line because we didn't want to risk breaking things in case it does something useful for a board. -- To view, visit https://review.coreboot.org/c/coreboot/+/48750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Gerrit-Change-Number: 48750 Gerrit-PatchSet: 34 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Jan 2021 21:09:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: add panel and backlight configuration code
by Nico Huber (Code Review) 01 Jan '21

01 Jan '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48749 ) Change subject: soc/intel/cnl: add panel and backlight configuration code ...................................................................... Patch Set 31: Code-Review+2 I find the additional brackets quite irritating but they seem correct so let's get it in. Generally I believe brackets are not a good way to make things more human readable. If you want to make the execution order clearly visible, you can use intermediate statements. Each on one line. -- To view, visit https://review.coreboot.org/c/coreboot/+/48749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Gerrit-Change-Number: 48749 Gerrit-PatchSet: 31 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Jan 2021 21:00:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI
by Matt DeVillier (Code Review) 01 Jan '21

01 Jan '21

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48750 ) Change subject: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI ...................................................................... Patch Set 34: (1 comment) https://review.coreboot.org/c/coreboot/+/48750/34//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48750/34//COMMIT_MSG@12 PS34, Line 12: Brightness control still requires ACPI code to link the EC events to it. : This will be done in a separate change later. is this still true? the parent commit should be sufficient, no? -- To view, visit https://review.coreboot.org/c/coreboot/+/48750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Gerrit-Change-Number: 48750 Gerrit-PatchSet: 34 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Jan 2021 20:53:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings
by Nico Huber (Code Review) 01 Jan '21

01 Jan '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48885 ) Change subject: nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings ...................................................................... Patch Set 19: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Gerrit-Change-Number: 48885 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Jan 2021 20:48:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 01 Jan '21

01 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > Any news? :-) If you need any help with this or in case you don't have the time to finalize it, I can take that if you wish. Just let me know > > Hi Michael. Sorry, i was still waiting for Angle's reply for the location of the change and was busy with some other high priority issues. Thanks for asking, please go ahead and take it over. The present form of patch is working. I had verifies it with 5.4 kernel. Hi Shaunak, I finally managed to finish this with a bunch of improvements. Have a look at topic:acpi_lpit -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Jan 2021 20:39:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2021