coreboot-gerrit January 2021

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Change in coreboot[master]: nb/intel/sandybridge: Split receive enable calibration
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49289 ) Change subject: nb/intel/sandybridge: Split receive enable calibration ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib435eec122b3a3d707e1792b604ad43635b650fa Gerrit-Change-Number: 49289 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: nb/intel/sandybridge: Clean up `channel_test` function
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49288 ) Change subject: nb/intel/sandybridge: Clean up `channel_test` function ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8b1db2b2b17d000061b451dcdd212a2adfabf94 Gerrit-Change-Number: 49288 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: nb/intel/sandybridge: Shorten `slotrank` to `rank`
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47751 ) Change subject: nb/intel/sandybridge: Shorten `slotrank` to `rank` ...................................................................... nb/intel/sandybridge: Shorten `slotrank` to `rank` The longer name doesn't add any useful information. Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: Ie1fa6285c10cf12a0aecb0f0345ad7a55cd7e900 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_iosav.c 3 files changed, 300 insertions(+), 300 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47751/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b3a59fc..d227472 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -534,7 +534,7 @@ static void write_reset(ramctr_timing *ctrl) { - int channel, slotrank; + int channel, rank; /* Choose a populated channel */ channel = (ctrl->rankmap[0]) ? 0 : 1; @@ -542,9 +542,9 @@ wait_for_iosav(channel); /* Choose a populated rank */ - slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; + rank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); + iosav_write_zqcs_sequence(channel, rank, 3, 8, 0); /* * Execute command queue - why is bit 22 set here?! @@ -618,11 +618,11 @@ *addr = (*addr & ~0x1f8) | ((*addr >> 1) & 0xa8) | ((*addr & 0xa8) << 1); } -static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) +static void write_mrreg(ramctr_timing *ctrl, int channel, int rank, int reg, u32 val) { wait_for_iosav(channel); - if (ctrl->rank_mirror[channel][slotrank]) + if (ctrl->rank_mirror[channel][rank]) ddr3_mirror_mrreg(&reg, &val); const struct iosav_ssq sequence[] = { @@ -641,7 +641,7 @@ .address = val, .rowbits = 6, .bank = reg, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command MRS */ @@ -660,7 +660,7 @@ .address = val, .rowbits = 6, .bank = reg, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command MRS */ @@ -678,7 +678,7 @@ .address = val, .rowbits = 6, .bank = reg, - .rank = slotrank, + .rank = rank, }, }, }; @@ -832,22 +832,22 @@ void dram_mrscommands(ramctr_timing *ctrl) { - u8 slotrank; + u8 rank; int channel; FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_RANKS { /* MR2 */ - dram_mr2(ctrl, slotrank, channel); + dram_mr2(ctrl, rank, channel); /* MR3 */ - dram_mr3(ctrl, slotrank, channel); + dram_mr3(ctrl, rank, channel); /* MR1 */ - dram_mr1(ctrl, slotrank, channel); + dram_mr1(ctrl, rank, channel); /* MR0 */ - dram_mr0(ctrl, slotrank, channel); + dram_mr0(ctrl, rank, channel); } } @@ -912,12 +912,12 @@ wait_for_iosav(channel); - slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; + rank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* Drain */ wait_for_iosav(channel); - iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); + iosav_write_zqcs_sequence(channel, rank, 4, 101, 31); /* Execute command queue */ iosav_run_once(channel); @@ -937,13 +937,13 @@ { u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; int lane; - int slotrank, slot; + int rank, slot; int full_shift = 0; u16 pi_coding_ctrl[NUM_SLOTS]; FOR_ALL_POPULATED_RANKS { - if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) - full_shift = -ctrl->timings[channel][slotrank].pi_coding; + if (full_shift < -ctrl->timings[channel][rank].pi_coding) + full_shift = -ctrl->timings[channel][rank].pi_coding; } for (slot = 0; slot < NUM_SLOTS; slot++) @@ -986,7 +986,7 @@ reg_logic_delay = 0; FOR_ALL_POPULATED_RANKS { - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][rank].pi_coding + full_shift; int offset_pi_code; if (shift < 0) shift = 0; @@ -994,8 +994,8 @@ offset_pi_code = ctrl->pi_code_offset + shift; /* Set CLK phase shift */ - reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); - reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; + reg_pi_code |= (offset_pi_code & 0x3f) << (6 * rank); + reg_logic_delay |= ((offset_pi_code >> 6) & 1) << rank; } MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; @@ -1010,23 +1010,23 @@ int post_timA_min_high = 7, pre_timA_min_high = 7; int post_timA_max_high = 0, pre_timA_max_high = 0; int shift_402x = 0; - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][rank].pi_coding + full_shift; if (shift < 0) shift = 0; FOR_ALL_LANES { post_timA_min_high = MIN(post_timA_min_high, - (ctrl->timings[channel][slotrank].lanes[lane]. + (ctrl->timings[channel][rank].lanes[lane]. timA + shift) >> 6); pre_timA_min_high = MIN(pre_timA_min_high, - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. timA >> 6); post_timA_max_high = MAX(post_timA_max_high, - (ctrl->timings[channel][slotrank].lanes[lane]. + (ctrl->timings[channel][rank].lanes[lane]. timA + shift) >> 6); pre_timA_max_high = MAX(pre_timA_max_high, - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. timA >> 6); } @@ -1039,38 +1039,38 @@ shift_402x = -1; reg_io_latency |= - (ctrl->timings[channel][slotrank].io_latency + shift_402x - - post_timA_min_high) << (4 * slotrank); + (ctrl->timings[channel][rank].io_latency + shift_402x - + post_timA_min_high) << (4 * rank); reg_roundtrip_latency |= - (ctrl->timings[channel][slotrank].roundtrip_latency + - shift_402x) << (8 * slotrank); + (ctrl->timings[channel][rank].roundtrip_latency + + shift_402x) << (8 * rank); FOR_ALL_LANES { - MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = - (((ctrl->timings[channel][slotrank].lanes[lane]. + MCHBAR32(lane_base[lane] + GDCRRX(channel, rank)) = + (((ctrl->timings[channel][rank].lanes[lane]. timA + shift) & 0x3f) | - ((ctrl->timings[channel][slotrank].lanes[lane]. + ((ctrl->timings[channel][rank].lanes[lane]. rising + shift) << 8) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timA + shift - (post_timA_min_high << 6)) & 0x1c0) << 10) - | ((ctrl->timings[channel][slotrank].lanes[lane]. + | ((ctrl->timings[channel][rank].lanes[lane]. falling + shift) << 20)); - MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = - (((ctrl->timings[channel][slotrank].lanes[lane]. + MCHBAR32(lane_base[lane] + GDCRTX(channel, rank)) = + (((ctrl->timings[channel][rank].lanes[lane]. timC + shift) & 0x3f) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timB + shift) & 0x3f) << 8) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timB + shift) & 0x1c0) << 9) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timC + shift) & 0x40) << 13)); } } @@ -1078,11 +1078,11 @@ MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; } -static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) +static void test_timA(ramctr_timing *ctrl, int channel, int rank) { wait_for_iosav(channel); - iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); + iosav_write_read_mpr_sequence(channel, rank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); /* Execute command queue */ iosav_run_once(channel); @@ -1090,9 +1090,9 @@ wait_for_iosav(channel); } -static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) +static int does_lane_work(ramctr_timing *ctrl, int channel, int rank, int lane) { - u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; + u32 timA = ctrl->timings[channel][rank].lanes[lane].timA; return (MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; @@ -1237,7 +1237,7 @@ return MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, idx)); } -static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int rank, int *upperA) { int timA; u32 statistics[NUM_LANES][4]; @@ -1246,12 +1246,12 @@ for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) { for (timA = 0; timA < 64; timA++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA = + ctrl->timings[channel][rank].lanes[lane].timA = timA + logic_delay * 64; } program_timings(ctrl, channel); - test_timA(ctrl, channel, slotrank); + test_timA(ctrl, channel, rank); } FOR_ALL_LANES { statistics[lane][logic_delay * 2 + 0] = get_stats(channel, lane, 0); @@ -1265,17 +1265,17 @@ FOR_ALL_LANES { printk(BIOS_ERR, "Lane %d:\t", lane); struct run rn = get_passing_region(statistics[lane], 4); - ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; + ctrl->timings[channel][rank].lanes[lane].timA = rn.middle; upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, rank, lane, rn.start, rn.middle, rn.end); } } -static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int rank, int *upperA) { int timA_delta; int statistics[NUM_LANES][51]; @@ -1286,16 +1286,16 @@ for (timA_delta = -25; timA_delta <= 25; timA_delta++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA + ctrl->timings[channel][rank].lanes[lane].timA = upperA[lane] + timA_delta + 0x40; } program_timings(ctrl, channel); for (i = 0; i < 100; i++) { - test_timA(ctrl, channel, slotrank); + test_timA(ctrl, channel, rank); FOR_ALL_LANES { statistics[lane][timA_delta + 25] += - does_lane_work(ctrl, channel, slotrank, lane); + does_lane_work(ctrl, channel, rank, lane); } } } @@ -1324,15 +1324,15 @@ printram("lane %d: %d, %d\n", lane, last_zero, first_all); - ctrl->timings[channel][slotrank].lanes[lane].timA = + ctrl->timings[channel][rank].lanes[lane].timA = (last_zero + first_all) / 2 + upperA[lane]; - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: %x\n", channel, rank, + lane, ctrl->timings[channel][rank].lanes[lane].timA); } } -static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int rank, int *upperA) { int works[NUM_LANES]; int lane; @@ -1341,10 +1341,10 @@ int all_works = 1, some_works = 0; program_timings(ctrl, channel); - test_timA(ctrl, channel, slotrank); + test_timA(ctrl, channel, rank); FOR_ALL_LANES { - works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); + works[lane] = !does_lane_work(ctrl, channel, rank, lane); if (works[lane]) some_works = 1; @@ -1355,40 +1355,40 @@ return 0; if (!some_works) { - if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { + if (ctrl->timings[channel][rank].roundtrip_latency < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", - channel, slotrank); + channel, rank); return MAKE_ERR; } - ctrl->timings[channel][slotrank].roundtrip_latency -= 2; + ctrl->timings[channel][rank].roundtrip_latency -= 2; printram("4024 -= 2;\n"); continue; } - ctrl->timings[channel][slotrank].io_latency += 2; + ctrl->timings[channel][rank].io_latency += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { + if (ctrl->timings[channel][rank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", - channel, slotrank); + channel, rank); return MAKE_ERR; } FOR_ALL_LANES if (works[lane]) { - ctrl->timings[channel][slotrank].lanes[lane].timA += 128; + ctrl->timings[channel][rank].lanes[lane].timA += 128; upperA[lane] += 128; - printram("increment %d, %d, %d\n", channel, slotrank, lane); + printram("increment %d, %d, %d\n", channel, rank, lane); } } return 0; } -static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int slotrank) +static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int rank) { int lane; u16 logic_delay_min = 7; u16 logic_delay_max = 0; FOR_ALL_LANES { - const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + const u16 logic_delay = ctrl->timings[channel][rank].lanes[lane].timA >> 6; logic_delay_min = MIN(logic_delay_min, logic_delay); logic_delay_max = MAX(logic_delay_max, logic_delay); @@ -1396,7 +1396,7 @@ if (logic_delay_max < logic_delay_min) { printk(BIOS_EMERG, "Logic delay max < min (%u < %u): %d, %d\n", - logic_delay_max, logic_delay_min, channel, slotrank); + logic_delay_max, logic_delay_min, channel, rank); } assert(logic_delay_max >= logic_delay_min); @@ -1404,12 +1404,12 @@ return logic_delay_max - logic_delay_min; } -static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int slotrank, int prev) +static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int rank, int prev) { int latency_offset = 0; /* Get changed maxima */ - const int post = get_logic_delay_delta(ctrl, channel, slotrank); + const int post = get_logic_delay_delta(ctrl, channel, rank); if (prev < post) latency_offset = +1; @@ -1420,40 +1420,40 @@ else latency_offset = 0; - ctrl->timings[channel][slotrank].io_latency += latency_offset; - ctrl->timings[channel][slotrank].roundtrip_latency += latency_offset; + ctrl->timings[channel][rank].io_latency += latency_offset; + ctrl->timings[channel][rank].roundtrip_latency += latency_offset; printram("4024 += %d;\n", latency_offset); printram("4028 += %d;\n", latency_offset); return post; } -static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slotrank) +static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int rank) { u16 logic_delay_min = 7; int lane; FOR_ALL_LANES { - const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + const u16 logic_delay = ctrl->timings[channel][rank].lanes[lane].timA >> 6; logic_delay_min = MIN(logic_delay_min, logic_delay); } if (logic_delay_min >= 2) { printk(BIOS_WARNING, "Logic delay %u greater than 1: %d %d\n", - logic_delay_min, channel, slotrank); + logic_delay_min, channel, rank); } FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= logic_delay_min << 6; + ctrl->timings[channel][rank].lanes[lane].timA -= logic_delay_min << 6; } - ctrl->timings[channel][slotrank].io_latency -= logic_delay_min; + ctrl->timings[channel][rank].io_latency -= logic_delay_min; printram("4028 -= %d;\n", logic_delay_min); } int receive_enable_calibration(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, rank, lane; int err; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -1463,74 +1463,74 @@ wait_for_iosav(channel); - iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); + iosav_write_prea_sequence(channel, rank, ctrl->tRP, 0); /* Execute command queue */ iosav_run_once(channel); const union gdcr_training_mod_reg training_mod = { .receive_enable_mode = 1, - .training_rank_sel = slotrank, + .training_rank_sel = rank, .odt_always_on = 1, }; MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; - ctrl->timings[channel][slotrank].io_latency = 4; - ctrl->timings[channel][slotrank].roundtrip_latency = 55; + ctrl->timings[channel][rank].io_latency = 4; + ctrl->timings[channel][rank].roundtrip_latency = 55; program_timings(ctrl, channel); - find_rcven_pi_coarse(ctrl, channel, slotrank, upperA); + find_rcven_pi_coarse(ctrl, channel, rank, upperA); all_high = 1; some_high = 0; FOR_ALL_LANES { - if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) + if (ctrl->timings[channel][rank].lanes[lane].timA >= 0x40) some_high = 1; else all_high = 0; } if (all_high) { - ctrl->timings[channel][slotrank].io_latency--; + ctrl->timings[channel][rank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; + ctrl->timings[channel][rank].lanes[lane].timA -= 0x40; upperA[lane] -= 0x40; } } else if (some_high) { - ctrl->timings[channel][slotrank].roundtrip_latency++; - ctrl->timings[channel][slotrank].io_latency++; + ctrl->timings[channel][rank].roundtrip_latency++; + ctrl->timings[channel][rank].io_latency++; printram("4024++;\n"); printram("4028++;\n"); } program_timings(ctrl, channel); - prev = get_logic_delay_delta(ctrl, channel, slotrank); + prev = get_logic_delay_delta(ctrl, channel, rank); - err = find_roundtrip_latency(ctrl, channel, slotrank, upperA); + err = find_roundtrip_latency(ctrl, channel, rank, upperA); if (err) return err; - prev = align_rt_io_latency(ctrl, channel, slotrank, prev); + prev = align_rt_io_latency(ctrl, channel, rank, prev); - fine_tune_rcven_pi(ctrl, channel, slotrank, upperA); + fine_tune_rcven_pi(ctrl, channel, rank, upperA); - prev = align_rt_io_latency(ctrl, channel, slotrank, prev); + prev = align_rt_io_latency(ctrl, channel, rank, prev); - compute_final_logic_delay(ctrl, channel, slotrank); + compute_final_logic_delay(ctrl, channel, rank); - align_rt_io_latency(ctrl, channel, slotrank, prev); + align_rt_io_latency(ctrl, channel, rank, prev); - printram("4/8: %d, %d, %x, %x\n", channel, slotrank, - ctrl->timings[channel][slotrank].roundtrip_latency, - ctrl->timings[channel][slotrank].io_latency); + printram("4/8: %d, %d, %x, %x\n", channel, rank, + ctrl->timings[channel][rank].roundtrip_latency, + ctrl->timings[channel][rank].io_latency); printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, - ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: %x\n", channel, rank, lane, + ctrl->timings[channel][rank].lanes[lane].timA); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1544,7 +1544,7 @@ return 0; } -static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) +static void test_tx_dq(ramctr_timing *ctrl, int channel, int rank) { int lane; @@ -1555,7 +1555,7 @@ wait_for_iosav(channel); - iosav_write_misc_write_sequence(ctrl, channel, slotrank, + iosav_write_misc_write_sequence(ctrl, channel, rank, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); /* Execute command queue */ @@ -1563,7 +1563,7 @@ wait_for_iosav(channel); - iosav_write_prea_act_read_sequence(ctrl, channel, slotrank); + iosav_write_prea_act_read_sequence(ctrl, channel, rank); /* Execute command queue */ iosav_run_once(channel); @@ -1590,7 +1590,7 @@ printram("threshold=%d min=%d max=%d\n", threshold, min, max); } -static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) +static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int rank) { int start[NUM_LANES]; int tx_dq; @@ -1599,23 +1599,23 @@ wait_for_iosav(channel); - iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); + iosav_write_prea_sequence(channel, rank, ctrl->tRP, 18); /* Execute command queue */ iosav_run_once(channel); FOR_ALL_LANES { /* 32 ticks for ideal centering */ - start[lane] = (ctrl->timings[channel][slotrank].lanes[lane].timB + 32) % 128; + start[lane] = (ctrl->timings[channel][rank].lanes[lane].timB + 32) % 128; } for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { FOR_ALL_LANES - ctrl->timings[channel][slotrank].lanes[lane].timC = + ctrl->timings[channel][rank].lanes[lane].timC = (start[lane] + tx_dq) % 128; program_timings(ctrl, channel); - test_tx_dq(ctrl, channel, slotrank); + test_tx_dq(ctrl, channel, rank); FOR_ALL_LANES { stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); @@ -1637,7 +1637,7 @@ if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + channel, rank, lane); /* * With command training not being done yet, the lane can be erroneous. * Take the average as reference and try again to find a run. @@ -1653,10 +1653,10 @@ rn.start += start[lane]; rn.middle += start[lane]; rn.end += start[lane]; - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle % 128; + ctrl->timings[channel][rank].lanes[lane].timC = rn.middle % 128; printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, rank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1715,7 +1715,7 @@ program_wdb_pattern_length(channel, 16); } -static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) +static int write_level_rank(ramctr_timing *ctrl, int channel, int rank) { int timB; int statistics[NUM_LANES][128]; @@ -1723,26 +1723,26 @@ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, - .training_rank_sel = slotrank, + .training_rank_sel = rank, .enable_dqs_wl = 5, .odt_always_on = 1, .force_drive_enable = 1, }; MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; - u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; + u32 mr1reg = make_mr1(ctrl, rank, channel) | 1 << 7; int bank = 1; - if (ctrl->rank_mirror[channel][slotrank]) + if (ctrl->rank_mirror[channel][rank]) ddr3_mirror_mrreg(&bank, &mr1reg); wait_for_iosav(channel); - iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); + iosav_write_jedec_write_leveling_sequence(ctrl, channel, rank, bank, mr1reg); for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timB = timB; + ctrl->timings[channel][rank].lanes[lane].timB = timB; } program_timings(ctrl, channel); @@ -1773,15 +1773,15 @@ else if ((rn.start & 0x3f) == 0x3f) rn.start += 1; - ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + ctrl->timings[channel][rank].lanes[lane].timB = rn.start; if (rn.all) { printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + channel, rank, lane); return MAKE_ERR; } printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, rank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1808,7 +1808,7 @@ static void train_write_flyby(ramctr_timing *ctrl) { - int channel, slotrank, lane, old; + int channel, rank, lane, old; const union gdcr_training_mod_reg training_mod = { .dq_dqs_training_res = 1, @@ -1825,7 +1825,7 @@ wait_for_iosav(channel); - iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); + iosav_write_misc_write_sequence(ctrl, channel, rank, 3, 1, 3, 3, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1849,7 +1849,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -1871,7 +1871,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command RD */ @@ -1884,15 +1884,15 @@ .cmd_executions = 1, .cmd_delay_gap = 3, .post_ssq_wait = ctrl->tRP + - ctrl->timings[channel][slotrank].roundtrip_latency + - ctrl->timings[channel][slotrank].io_latency, + ctrl->timings[channel][rank].roundtrip_latency + + ctrl->timings[channel][rank].io_latency, .data_direction = SSQ_RD, }, .sp_cmd_addr = { .address = 8, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; @@ -1907,13 +1907,13 @@ res |= ((u64) MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += + old = ctrl->timings[channel][rank].lanes[lane].timB; + ctrl->timings[channel][rank].lanes[lane].timB += get_dqs_flyby_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, - old, ctrl->timings[channel][slotrank].lanes[lane].timB); + printram("Bval+: %d, %d, %d, %x -> %x\n", channel, rank, lane, + old, ctrl->timings[channel][rank].lanes[lane].timB); } } MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1925,9 +1925,9 @@ FOR_ALL_POPULATED_CHANNELS { /* choose an existing rank */ - const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + const int rank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); + iosav_write_zqcs_sequence(channel, rank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1962,7 +1962,7 @@ */ static int jedec_write_leveling(ramctr_timing *ctrl) { - int channel, slotrank; + int channel, rank; disable_refresh_machine(ctrl); @@ -1970,8 +1970,8 @@ Disable all DQ outputs Only NOP is allowed in this mode */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); + write_mrreg(ctrl, channel, rank, 1, + make_mr1(ctrl, rank, channel) | 1 << 12 | 1 << 7); /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { @@ -1986,14 +1986,14 @@ /* Set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - const int err = write_level_rank(ctrl, channel, slotrank); + const int err = write_level_rank(ctrl, channel, rank); if (err) return err; } /* Disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, rank, 1, make_mr1(ctrl, rank, channel)); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -2023,7 +2023,7 @@ int write_training(ramctr_timing *ctrl) { - int channel, slotrank; + int channel, rank; int err; FOR_ALL_POPULATED_CHANNELS @@ -2042,7 +2042,7 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = tx_dq_write_leveling(ctrl, channel, slotrank); + err = tx_dq_write_leveling(ctrl, channel, rank); if (err) return err; } @@ -2059,9 +2059,9 @@ return 0; } -static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) +static int test_command_training(ramctr_timing *ctrl, int channel, int rank) { - struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; + struct ram_rank_timings saved_rt = ctrl->timings[channel][rank]; int timC_delta; int lanes_ok = 0; int ctr = 0; @@ -2069,7 +2069,7 @@ for (timC_delta = -5; timC_delta <= 5; timC_delta++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timC = + ctrl->timings[channel][rank].lanes[lane].timC = saved_rt.lanes[lane].timC + timC_delta; } program_timings(ctrl, channel); @@ -2082,7 +2082,7 @@ wait_for_iosav(channel); - iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); + iosav_write_command_training_sequence(ctrl, channel, rank, ctr); /* Program LFSR for the RD/WR subsequences */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; @@ -2103,7 +2103,7 @@ break; } - ctrl->timings[channel][slotrank] = saved_rt; + ctrl->timings[channel][rank] = saved_rt; return lanes_ok != ((1 << ctrl->lanes) - 1); } @@ -2162,7 +2162,7 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) { struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; - int slotrank; + int rank; int command_pi; int stat[NUM_SLOTRANKS][CT_PI_LENGTH]; int delta = 0; @@ -2170,7 +2170,7 @@ printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); FOR_ALL_POPULATED_RANKS { - saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; + saved_timings[channel][rank] = ctrl->timings[channel][rank]; } ctrl->cmd_stretch[channel] = cmd_stretch; @@ -2192,31 +2192,31 @@ delta = 4; FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank].roundtrip_latency -= delta; + ctrl->timings[channel][rank].roundtrip_latency -= delta; } for (command_pi = CT_MIN_PI; command_pi < CT_MAX_PI; command_pi++) { FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank].pi_coding = command_pi; + ctrl->timings[channel][rank].pi_coding = command_pi; } program_timings(ctrl, channel); reprogram_320c(ctrl); FOR_ALL_POPULATED_RANKS { - stat[slotrank][command_pi - CT_MIN_PI] = - test_command_training(ctrl, channel, slotrank); + stat[rank][command_pi - CT_MIN_PI] = + test_command_training(ctrl, channel, rank); } } FOR_ALL_POPULATED_RANKS { - struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); + struct run rn = get_longest_zero_run(stat[rank], CT_PI_LENGTH - 1); - ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; + ctrl->timings[channel][rank].pi_coding = rn.middle + CT_MIN_PI; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, rn.start, rn.middle, rn.end); + channel, rank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank] = - saved_timings[channel][slotrank]; + ctrl->timings[channel][rank] = + saved_timings[channel][rank]; } return MAKE_ERR; } @@ -2279,7 +2279,7 @@ return 0; } -static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int rank, int *edges) { int dqs_pi; int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; @@ -2287,8 +2287,8 @@ for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = dqs_pi; - ctrl->timings[channel][slotrank].lanes[lane].falling = dqs_pi; + ctrl->timings[channel][rank].lanes[lane].rising = dqs_pi; + ctrl->timings[channel][rank].lanes[lane].falling = dqs_pi; } program_timings(ctrl, channel); @@ -2300,7 +2300,7 @@ wait_for_iosav(channel); iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); + channel, rank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2328,17 +2328,17 @@ if (rn.all) { printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, - slotrank, lane); + rank, lane); return MAKE_ERR; } - printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); + printram("eval %d, %d, %d: %02x\n", channel, rank, lane, edges[lane]); } return 0; } static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) { - int slotrank, lane; + int rank, lane; fill_pattern0(ctrl, channel, 0, 0); FOR_ALL_LANES { @@ -2347,8 +2347,8 @@ } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = 16; + ctrl->timings[channel][rank].lanes[lane].falling = 16; + ctrl->timings[channel][rank].lanes[lane].rising = 16; } program_timings(ctrl, channel); @@ -2357,7 +2357,7 @@ wait_for_iosav(channel); iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); + channel, rank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2368,8 +2368,8 @@ /* XXX: check any measured value ? */ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; + ctrl->timings[channel][rank].lanes[lane].falling = 48; + ctrl->timings[channel][rank].lanes[lane].rising = 48; } program_timings(ctrl, channel); @@ -2378,7 +2378,7 @@ wait_for_iosav(channel); iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); + channel, rank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2398,7 +2398,7 @@ { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane; + int channel, rank, lane; int err; MCHBAR32(GDCRTRAININGMOD) = 0; @@ -2419,8 +2419,8 @@ printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_read_mpr_margin(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + err = find_read_mpr_margin(ctrl, channel, rank, + falling_edges[channel][rank]); if (err) return err; } @@ -2429,8 +2429,8 @@ printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_read_mpr_margin(ctrl, channel, slotrank, - rising_edges[channel][slotrank]); + err = find_read_mpr_margin(ctrl, channel, rank, + rising_edges[channel][rank]); if (err) return err; } @@ -2438,10 +2438,10 @@ MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - falling_edges[channel][slotrank][lane]; - ctrl->timings[channel][slotrank].lanes[lane].rising = - rising_edges[channel][slotrank][lane]; + ctrl->timings[channel][rank].lanes[lane].falling = + falling_edges[channel][rank][lane]; + ctrl->timings[channel][rank].lanes[lane].rising = + rising_edges[channel][rank][lane]; } FOR_ALL_POPULATED_CHANNELS { @@ -2454,7 +2454,7 @@ return 0; } -static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int rank, int *edges) { const int rd_vref_offsets[] = { 0, 0xc, 0x2c }; @@ -2492,13 +2492,13 @@ read_pi = MAX_EDGE_TIMING / 2; FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = read_pi; - ctrl->timings[channel][slotrank].lanes[lane].falling = read_pi; + ctrl->timings[channel][rank].lanes[lane].rising = read_pi; + ctrl->timings[channel][rank].lanes[lane].falling = read_pi; } program_timings(ctrl, channel); /* Write test pattern to memory */ - iosav_write_data_write_sequence(ctrl, channel, slotrank); + iosav_write_data_write_sequence(ctrl, channel, rank); iosav_run_once(channel); @@ -2506,9 +2506,9 @@ for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. rising = read_pi; - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. falling = read_pi; } program_timings(ctrl, channel); @@ -2536,7 +2536,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 0, @@ -2559,7 +2559,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -2582,7 +2582,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; @@ -2624,7 +2624,7 @@ if (!sweep_vref) { printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, i, + "0x%02x-0x%02x\n", channel, rank, i, rn.start, rn.middle, rn.end, rn.start + edge_offset, rn.end - edge_offset); } @@ -2638,7 +2638,7 @@ if (!sweep_vref && (rn.all || lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: " - "%d, %d, %d, %d, %d, %d\n", channel, slotrank, + "%d, %d, %d, %d, %d, %d\n", channel, rank, lane, rn.all, lower[lane], upper[lane]); return MAKE_ERR; @@ -2660,7 +2660,7 @@ { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane, err; + int channel, rank, lane, err; /* * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will @@ -2670,8 +2670,8 @@ printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_agrsv_read_margin(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + err = find_agrsv_read_margin(ctrl, channel, rank, + falling_edges[channel][rank]); if (err) return err; } @@ -2680,8 +2680,8 @@ printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_agrsv_read_margin(ctrl, channel, slotrank, - rising_edges[channel][slotrank]); + err = find_agrsv_read_margin(ctrl, channel, rank, + rising_edges[channel][rank]); if (err) return err; } @@ -2689,11 +2689,11 @@ MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - falling_edges[channel][slotrank][lane]; + ctrl->timings[channel][rank].lanes[lane].falling = + falling_edges[channel][rank][lane]; - ctrl->timings[channel][slotrank].lanes[lane].rising = - rising_edges[channel][slotrank][lane]; + ctrl->timings[channel][rank].lanes[lane].rising = + rising_edges[channel][rank][lane]; } FOR_ALL_POPULATED_CHANNELS @@ -2702,11 +2702,11 @@ return 0; } -static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank) +static void test_aggressive_write(ramctr_timing *ctrl, int channel, int rank) { wait_for_iosav(channel); - iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); + iosav_write_aggressive_write_read_sequence(ctrl, channel, rank); /* Execute command queue */ iosav_run_once(channel); @@ -2727,7 +2727,7 @@ int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane; + int channel, rank, lane; /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ if (!IS_IVY_CPU(ctrl->cpu)) @@ -2737,8 +2737,8 @@ return 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - lower[channel][slotrank][lane] = 0; - upper[channel][slotrank][lane] = MAX_TIMC; + lower[channel][rank][lane] = 0; + upper[channel][rank][lane] = MAX_TIMC; } /* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ @@ -2766,12 +2766,12 @@ for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank] + ctrl->timings[channel][rank] .lanes[lane].timC = timC; } program_timings(ctrl, channel); - test_aggressive_write(ctrl, channel, slotrank); + test_aggressive_write(ctrl, channel, rank); raw_stats[timC] = MCHBAR32( IOSAV_BYTE_SERROR_C_ch(channel)); @@ -2788,24 +2788,24 @@ printk(BIOS_EMERG, "timC write discovery failed: " "%d, %d, %d\n", channel, - slotrank, lane); + rank, lane); return MAKE_ERR; } printram("timC: %d, %d, %d: " "0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, + "0x%02x-0x%02x\n", channel, rank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], rn.end - ctrl->timC_offset[i]); - lower[channel][slotrank][lane] = + lower[channel][rank][lane] = MAX(rn.start + ctrl->timC_offset[i], - lower[channel][slotrank][lane]); + lower[channel][rank][lane]); - upper[channel][slotrank][lane] = + upper[channel][rank][lane] = MIN(rn.end - ctrl->timC_offset[i], - upper[channel][slotrank][lane]); + upper[channel][rank][lane]); } } @@ -2825,13 +2825,13 @@ printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, - (lower[channel][slotrank][lane] + - upper[channel][slotrank][lane]) / 2); + printram("timC %d, %d, %d: %x\n", channel, rank, lane, + (lower[channel][rank][lane] + + upper[channel][rank][lane]) / 2); - ctrl->timings[channel][slotrank].lanes[lane].timC = - (lower[channel][slotrank][lane] + - upper[channel][slotrank][lane]) / 2; + ctrl->timings[channel][rank].lanes[lane].timC = + (lower[channel][rank][lane] + + upper[channel][rank][lane]) / 2; } FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); @@ -2841,23 +2841,23 @@ void normalize_training(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, rank, lane; int mat; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int delta; mat = 0; FOR_ALL_LANES mat = - MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][rank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n", - channel, slotrank, lane, mat); + channel, rank, lane, mat); - delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; + delta = (mat >> 6) - ctrl->timings[channel][rank].io_latency; printram("normalize %d, %d, %d: delta %d\n", - channel, slotrank, lane, delta); + channel, rank, lane, delta); - ctrl->timings[channel][slotrank].roundtrip_latency += delta; - ctrl->timings[channel][slotrank].io_latency += delta; + ctrl->timings[channel][rank].roundtrip_latency += delta; + ctrl->timings[channel][rank].io_latency += delta; } FOR_ALL_POPULATED_CHANNELS { @@ -2867,9 +2867,9 @@ int channel_test(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, rank, lane; - slotrank = 0; + rank = 0; FOR_ALL_POPULATED_CHANNELS if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); @@ -2879,16 +2879,16 @@ fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); } - for (slotrank = 0; slotrank < 4; slotrank++) + for (rank = 0; rank < 4; rank++) FOR_ALL_CHANNELS - if (ctrl->rankmap[channel] & (1 << slotrank)) { + if (ctrl->rankmap[channel] & (1 << rank)) { FOR_ALL_LANES { MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; } wait_for_iosav(channel); - iosav_write_memory_test_sequence(ctrl, channel, slotrank); + iosav_write_memory_test_sequence(ctrl, channel, rank); /* Execute command queue */ iosav_run_once(channel); @@ -2897,7 +2897,7 @@ FOR_ALL_LANES if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", - channel, slotrank, lane); + channel, rank, lane); return MAKE_ERR; } } @@ -2906,7 +2906,7 @@ void channel_scrub(ramctr_timing *ctrl) { - int channel, slotrank, row, rowsize; + int channel, rank, row, rowsize; u8 bank; FOR_ALL_POPULATED_CHANNELS { @@ -2925,7 +2925,7 @@ * and firmware running in x86_32. */ FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; + rowsize = 1 << ctrl->info.dimm[channel][rank >> 1].row_bits; for (bank = 0; bank < 8; bank++) { for (row = 0; row < rowsize; row += 16) { @@ -2950,7 +2950,7 @@ .address = row, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_1 = 1, @@ -2978,7 +2978,7 @@ .address = row, .rowbits = 0, .bank = bank, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -3004,7 +3004,7 @@ .address = 0, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -3069,15 +3069,15 @@ /* Use a larger delay when running fast to improve stability */ const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; - int channel, slotrank; + int channel, rank; FOR_ALL_POPULATED_CHANNELS { int min_pi = 10000; int max_pi = -10000; FOR_ALL_POPULATED_RANKS { - max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); - min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); + max_pi = MAX(ctrl->timings[channel][rank].pi_coding, max_pi); + min_pi = MIN(ctrl->timings[channel][rank].pi_coding, min_pi); } const u32 tWRDRDD = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index f2d0fb5..85553e1 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -249,20 +249,20 @@ void iosav_run_once(const int ch); void wait_for_iosav(int channel); -void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap); -void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); +void iosav_write_zqcs_sequence(int channel, int rank, u32 gap, u32 post, u32 wrap); +void iosav_write_prea_sequence(int channel, int rank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( - int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); -void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); + int channel, int rank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int rank); void iosav_write_jedec_write_leveling_sequence( - ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); -void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, + ramctr_timing *ctrl, int channel, int rank, int bank, u32 mr1reg); +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int rank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); void iosav_write_command_training_sequence( - ramctr_timing *ctrl, int channel, int slotrank, unsigned int address); -void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank); -void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); -void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank); + ramctr_timing *ctrl, int channel, int rank, unsigned int address); +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int rank); +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int rank); +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int rank); /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ @@ -294,10 +294,10 @@ /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ struct ram_rank_timings { - /* ROUNDT_LAT register: One byte per slotrank */ + /* ROUNDT_LAT register: One byte per rank */ u8 roundtrip_latency; - /* IO_LATENCY register: One nibble per slotrank */ + /* IO_LATENCY register: One nibble per rank */ u8 io_latency; /* Phase interpolator coding for command and control */ @@ -390,7 +390,7 @@ #define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++) #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) -#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) +#define FOR_ALL_POPULATED_RANKS for (rank = 0; rank < NUM_SLOTRANKS; rank++) if (ctrl->rankmap[channel] & (1 << rank)) #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) #define MAX_EDGE_TIMING 71 #define MAX_TIMC 127 @@ -399,7 +399,7 @@ #define MAX_CAS 18 #define MIN_CAS 4 -#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) +#define MAKE_ERR ((channel << 16) | (rank << 8) | 1) #define GET_ERR_CHANNEL(x) (x >> 16) void dram_mrscommands(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index d83dfd8..b230ee6 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -49,7 +49,7 @@ } } -void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap) +void iosav_write_zqcs_sequence(int channel, int rank, u32 gap, u32 post, u32 wrap) { const struct iosav_ssq sequence[] = { /* DRAM command ZQCS */ @@ -67,7 +67,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = wrap, @@ -77,7 +77,7 @@ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap) +void iosav_write_prea_sequence(int channel, int rank, u32 post, u32 wrap) { const struct iosav_ssq sequence[] = { /* DRAM command PREA */ @@ -96,7 +96,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = wrap, @@ -107,7 +107,7 @@ } void iosav_write_read_mpr_sequence( - int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) + int channel, int rank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) { const struct iosav_ssq sequence[] = { /* @@ -131,7 +131,7 @@ .address = 4, .rowbits = 6, .bank = 3, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command RD */ @@ -150,7 +150,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command RD */ @@ -169,7 +169,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* @@ -192,14 +192,14 @@ .address = 0, .rowbits = 6, .bank = 3, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command PREA */ @@ -218,7 +218,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -240,7 +240,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -263,7 +263,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -286,7 +286,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -297,13 +297,13 @@ } void iosav_write_jedec_write_leveling_sequence( - ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg) + ramctr_timing *ctrl, int channel, int rank, int bank, u32 mr1reg) { /* First DQS/DQS# rising edge after write leveling mode is programmed */ const u32 tWLMRD = 40; const struct iosav_ssq sequence[] = { - /* DRAM command MRS: enable DQs on this slotrank */ + /* DRAM command MRS: enable DQs on this rank */ [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, @@ -319,7 +319,7 @@ .address = mr1reg, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command NOP */ @@ -338,7 +338,7 @@ .address = 8, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command NOP */ @@ -357,10 +357,10 @@ .address = 4, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, - /* DRAM command MRS: disable DQs on this slotrank */ + /* DRAM command MRS: disable DQs on this rank */ [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, @@ -376,14 +376,14 @@ .address = mr1reg | 1 << 12, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int rank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) { const struct iosav_ssq sequence[] = { @@ -403,7 +403,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = loops0 == 1 ? 0 : 1, @@ -426,7 +426,7 @@ .address = 8, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 31, @@ -448,7 +448,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -471,7 +471,7 @@ .address = 8, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 31, @@ -482,7 +482,7 @@ } void iosav_write_command_training_sequence( - ramctr_timing *ctrl, int channel, int slotrank, unsigned int address) + ramctr_timing *ctrl, int channel, int rank, unsigned int address) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -501,7 +501,7 @@ .address = address, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -524,7 +524,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -549,7 +549,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -574,7 +574,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -584,7 +584,7 @@ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -603,7 +603,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 0, @@ -626,7 +626,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -649,7 +649,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -672,14 +672,14 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -698,7 +698,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -721,7 +721,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -744,7 +744,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -767,14 +767,14 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -793,7 +793,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -816,7 +816,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -839,7 +839,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -862,7 +862,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, -- To view, visit https://review.coreboot.org/c/coreboot/+/47751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1fa6285c10cf12a0aecb0f0345ad7a55cd7e900 Gerrit-Change-Number: 47751 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: nb/intel/sandybridge: Fix programming command timings
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49287 ) Change subject: nb/intel/sandybridge: Fix programming command timings ...................................................................... Patch Set 1: Code-Review-2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49287/comment/27ecc548_56dff78f PS1, Line 11: > That's basically an empty commit message. If you want to avoid documenting […] Yeah, I wrote it while trying not to fall asleep. Now that I know what needs to be fixed and how, I'd rather re-do the whole patch train. File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/c/coreboot/+/49287/comment/bd86596f_4fa83593 PS1, Line 943: FOR_ALL_POPULATED_RANKS { > Please consider making these macros readable before any further reviews. I don't like them myself. I'm just dragging them around because I don't know how to make them better other than outright removing them, and I don't want to deal with a change that always needs to be rebased manually. https://review.coreboot.org/c/coreboot/+/49287/comment/799a8e0a_95c486c4 PS1, Line 939: /* : * Compute command phase shift as the most negative CCC setting : * across all ranks. Use zero if none of the values is negative. : */ : FOR_ALL_POPULATED_RANKS { : cmd_delay = MAX(cmd_delay, -ctrl->timings[channel][slotrank].pi_coding); : } : > This part looks like a mere refactoring. […] The `if (cmd_delay == 0) {` check is nonsense, and clock needs to be offset by `ctrl->pi_code_offset`. I agree there's some refactoring that could have been split out, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/49287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33b2271803e6fa3d8e625bfe5a830152cab2b9d4 Gerrit-Change-Number: 49287 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 23:58:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/uart: Add ACPI SPCR table generation.
by build bot (Jenkins) (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Lance Zhao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49317 ) Change subject: drivers/uart: Add ACPI SPCR table generation. ...................................................................... Patch Set 1: (1 comment) File src/drivers/uart/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49317/comment/1ae6f53a_7b0d2e76 PS1, Line 188: if ( config->spcr.pci_bus_number || config->spcr.pci_device_id || space prohibited after that open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/49317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a Gerrit-Change-Number: 49317 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Comment-Date: Mon, 11 Jan 2021 23:57:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/uart: Add ACPI SPCR table generation.
by Martin Roth (Code Review) 11 Jan '21

11 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49317 ) Change subject: drivers/uart: Add ACPI SPCR table generation. ...................................................................... drivers/uart: Add ACPI SPCR table generation. The SPCR ACPI table is used to indicate whether a serial port or a non-legacy UART interface is available for use with Microsoft Windows Emergency Management Services (EMS). It is also used by Linux and BITS to determine the serial port configuration. For more information, see the Reference Serial Port Console Redirection Table. https://web.archive.org/web/20210111235235/https://docs.microsoft.com/en-us… BUG=b:74392237 TEST=Build Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a --- M src/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/uart/acpi/chip.h M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/drivers/uart/util.c M src/include/acpi/acpi.h M src/include/acpi/acpi_device.h M src/include/console/uart.h 9 files changed, 241 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/49317/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a16800b..727d2ab 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1665,6 +1665,8 @@ return 1; case CRAT: return 1; + case SPCR: + return 1; default: return -1; } diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c index d4b14aa..67f384e 100644 --- a/src/drivers/uart/acpi/acpi.c +++ b/src/drivers/uart/acpi/acpi.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <acpi/acpi_device.h> #include <acpi/acpigen.h> #include <console/console.h> +#include <console/uart.h> #include <device/path.h> #include <string.h> #include "chip.h" @@ -149,11 +151,132 @@ return name; } +/* Update the SPCR table from devicetree settings */ +static void dev_update_spcr(const struct device *dev, struct acpi_spcr *spcr) +{ + struct drivers_uart_acpi_config *config = dev->chip_info; + + if (config->spcr.base_address.addrh) { + spcr->base_address.access_size = config->spcr.base_address.access_size; + spcr->base_address.addrh = config->spcr.base_address.addrh; + spcr->base_address.addrl = config->spcr.base_address.addrl; + spcr->base_address.bit_width = config->spcr.base_address.bit_width; + spcr->base_address.space_id = config->spcr.base_address.space_id; + } + if (config->spcr.base_address.bit_offset) + spcr->base_address.bit_offset = config->spcr.base_address.bit_offset; + if (config->spcr.baud_rate) + spcr->baud_rate = config->spcr.baud_rate; + if (config->spcr.flow_control) + spcr->flow_control = config->spcr.flow_control; + if (config->spcr.global_system_interrupt) + spcr->global_system_interrupt = config->spcr.global_system_interrupt; + if (config->spcr.interface_type) + spcr->interface_type = config->spcr.interface_type; + if (config->spcr.interrupt_type) + spcr->interrupt_type = config->spcr.interrupt_type; + if (config->spcr.irq) + spcr->irq = config->spcr.irq; + if (config->spcr.irq) + spcr->parity = config->spcr.parity; + if (config->spcr.pci_vendor_id) { + spcr->pci_device_number = config->spcr.pci_device_number; + spcr->pci_flags = config->spcr.pci_flags; + spcr->pci_segment = config->spcr.pci_segment; + spcr->pci_vendor_id = config->spcr.pci_vendor_id; + } + if ( config->spcr.pci_bus_number || config->spcr.pci_device_id || + config->spcr.pci_function_number) { + spcr->pci_bus_number = config->spcr.pci_bus_number; + spcr->pci_device_id = config->spcr.pci_device_id; + spcr->pci_function_number = config->spcr.pci_function_number; + } + if (config->spcr.stop_bits) + spcr->stop_bits = config->spcr.stop_bits; + if (config->spcr.terminal_type) + spcr->terminal_type = config->spcr.terminal_type; +} + +/* Return SPCR encoded baudrate */ +static uint8_t get_spcr_baudrate(void) +{ + switch (get_uart_baudrate()) { + case 115200: + return SPCR_115200_BAUD; + case 57600: + return SPCR_57600_BAUD; + case 119200: + return SPCR_19200_BAUD; + case 9600: + return SPCR_9600_BAUD; + default: + printk(BIOS_WARNING, "SPCR Error: Unsupported baud rate.\n" + "SPCR table supports 115200, 57600, 19200, or 9600.\n"); + } + + return 0; +} + +/* + * Serial Port Console Redirection Table (SPCR) + */ +static unsigned long uart_acpi_write_spcr(const struct device *dev, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_table_header *header; + + struct acpi_spcr *spcr = (void *)current; + if (!CONFIG(ENABLE_UART) || !current) + return current; + + printk(BIOS_DEBUG, "ACPI: * SPCR\n"); + memset((void *)spcr, 0, sizeof(struct acpi_spcr)); + + /* Prepare the header */ + header = &(spcr->header); + memcpy(header->signature, "SPCR", 4); + header->length = sizeof(struct acpi_spcr); + header->revision = get_acpi_table_revision(SPCR); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + /* Set some default values. Override these at the uart level + * with update_spcr_data() + */ + spcr->interrupt_type = SPCR_NO_INTERRUPT_SUPPORTED; + spcr->irq = SPCR_NO_IRQ; + spcr->global_system_interrupt = SPCR_NO_GSI; + spcr->baud_rate = get_spcr_baudrate(); + spcr->parity = SPCR_NO_PARITY; + spcr->stop_bits = SPCR_1_STOP_BIT; + spcr->flow_control = SPCR_NO_FLOW_CONTROL; + spcr->terminal_type = SPCR_TERM_VT100; + spcr->pci_device_id = SPCR_DID_NOT_A_PCI_DEVICE; + spcr->pci_vendor_id = SPCR_VID_NOT_A_PCI_DEVICE; + spcr->pci_bus_number = SPCR_BUS_NOT_A_PCI_DEVICE; + spcr->pci_device_number = SPCR_DEV_NOT_A_PCI_DEVICE; + spcr->pci_function_number = SPCR_FUNC_NOT_A_PCI_DEVICE; + spcr->pci_flags = SPCR_PCI_FLAG_NOT_A_PCI_DEVICE; + spcr->pci_segment = SPCR_PCI_SEGMENT_0; + if (CONFIG(ENABLE_UART)) + update_spcr_data(spcr); + dev_update_spcr(dev, spcr); + if (spcr->baud_rate == 0 || spcr->base_address.addrl == 0) + return current; + + header->checksum = acpi_checksum((u8 *)spcr, spcr->header.length); + acpi_add_table(rsdp, spcr); + return current + sizeof(struct acpi_spcr); +} + static struct device_operations uart_acpi_dev_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .acpi_fill_ssdt = uart_acpi_fill_ssdt, .acpi_name = uart_acpi_name, + .write_acpi_tables = uart_acpi_write_spcr, }; static void uart_acpi_enable(struct device *dev) diff --git a/src/drivers/uart/acpi/chip.h b/src/drivers/uart/acpi/chip.h index 0311165..9b6264c 100644 --- a/src/drivers/uart/acpi/chip.h +++ b/src/drivers/uart/acpi/chip.h @@ -43,6 +43,9 @@ unsigned int stop_delay_ms; /* Delay to be inserted after enabling stop. */ unsigned int stop_off_delay_ms; + + /* SPCR table */ + struct acpi_spcr spcr; }; #endif /* __DRIVERS_UART_ACPI_H__ */ diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index aa8c969..f56b383 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> #include <arch/io.h> #include <boot/coreboot_tables.h> #include <console/uart.h> @@ -119,3 +120,13 @@ lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); } + +void update_spcr_8250io(struct acpi_spcr *spcr) +{ + spcr->base_address.addrl = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + if (!spcr->base_address.addrl) + return; + spcr->base_address.addrh = 0; /* currently 32 bit addresses only */ + spcr->base_address.space_id = ACPI_ADDRESS_SPACE_IO; + spcr->base_address.access_size = ACPI_ACCESS_SIZE_UNDEFINED; +} diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 1834095..ee9b846 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <console/uart.h> @@ -151,3 +152,19 @@ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } + +void update_spcr_8250mem(struct acpi_spcr *spcr) +{ + spcr->base_address.addrl = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + if (!spcr->base_address.addrl) + return; + spcr->base_address.space_id = ACPI_ADDRESS_SPACE_MEMORY; + spcr->base_address.addrh = 0; /* currently 32 bit addresses only */ + if (CONFIG(DRIVERS_UART_8250MEM_32)) + spcr->base_address.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + else + spcr->base_address.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + spcr->pci_bus_number = (CONFIG_UART_PCI_ADDR >> 20) & 0xff; + spcr->pci_device_number = (CONFIG_UART_PCI_ADDR >> 15) & 0x1f; + spcr->pci_function_number = (CONFIG_UART_PCI_ADDR >> 12) & 0x07; +} diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 1ac994e..d4dca53 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> #include <console/uart.h> #include <types.h> #include <timer.h> @@ -70,3 +71,12 @@ while (stopwatch_duration_usecs(&sw) < i * MHz / baud_rate) stopwatch_tick(&sw); } + +/* Generate the SPCR table based on what's enabled */ +void update_spcr_data(struct acpi_spcr *spcr) +{ + if (CONFIG(DRIVERS_UART_8250IO)) + return update_spcr_8250io(spcr); + if (CONFIG(DRIVERS_UART_8250MEM)) + return update_spcr_8250mem(spcr); +} diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 1c364a0..3d46059 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -71,7 +71,7 @@ enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, + RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, SPCR, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 301f9b0..8aa89be 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -3,6 +3,7 @@ #ifndef __ACPI_ACPI_DEVICE_H__ #define __ACPI_ACPI_DEVICE_H__ +#include <acpi/acpi.h> #include <device/i2c.h> #include <spi-generic.h> #include <types.h> @@ -458,6 +459,75 @@ unsigned int stop_off_delay_ms; }; +/* SPCR (Serial Port Console Redirection) */ +struct acpi_spcr { + struct acpi_table_header header; + u8 interface_type; + u8 reserved_1; + u8 reserved_2; + u8 reserved_3; + struct acpi_gen_regaddr base_address; + u8 interrupt_type; + u8 irq; + u32 global_system_interrupt; + u8 baud_rate; + u8 parity; + u8 stop_bits; + u8 flow_control; + u8 terminal_type; + u8 reserved_4; + u16 pci_device_id; + u16 pci_vendor_id; + u8 pci_bus_number; + u8 pci_device_number; + u8 pci_function_number; + u32 pci_flags; + u8 pci_segment; + u32 reserved_5; +} __packed; + +#define SPCR_16550_INTERFACE 0 +#define SPCR_16450_INTERFACE 1 + +#define SPCR_RESERVED_MUST_BE_ZERO 0 + +#define SPCR_NO_INTERRUPT_SUPPORTED 0 +#define SPCR_PIC_INTERRUPT_SUPPORTED (1 << 0) +#define SPCR_APIC_INTERRUPT_SUPPORTED (1 << 1) +#define SPCR_SAPIC_INTERRUPT_SUPPORTED (1 << 2) + +#define SPCR_NO_IRQ 0 +#define SPCR_NO_GSI 0 + +#define SPCR_9600_BAUD 3 +#define SPCR_19200_BAUD 4 +#define SPCR_57600_BAUD 6 +#define SPCR_115200_BAUD 7 + +#define SPCR_NO_PARITY 0 + +#define SPCR_1_STOP_BIT 1 + +#define SPCR_NO_FLOW_CONTROL 0 +#define SPCR_DCD_FLOW_CONTROL (1 << 0) +#define SPCR_RTS_CTS_FLOW_CONTROL (1 << 1) +#define SPCR_XON_XOFF_FLOW_CONTROL (1 << 2) + +#define SPCR_TERM_VT100 0 +#define SPCR_TERM_VT100_PLUS 1 +#define SPCR_TERM_VT_UTF8 2 +#define SPCR_TERM_ANSI 3 + +#define SPCR_DID_NOT_A_PCI_DEVICE 0xffff +#define SPCR_VID_NOT_A_PCI_DEVICE 0xffff +#define SPCR_BUS_NOT_A_PCI_DEVICE 0x00 +#define SPCR_DEV_NOT_A_PCI_DEVICE 0x00 +#define SPCR_FUNC_NOT_A_PCI_DEVICE 0x00 +#define SPCR_PCI_FLAG_NOT_A_PCI_DEVICE 0x00 +#define SPCR_PCI_FLAG_NONE 0x00 +#define SPCR_PCI_FLAG_DO_NOT_SUPPRESS_PNP_ENUM (1 << 0) +#define SPCR_PCI_SEGMENT_0 0x00 + /* * Add a basic PowerResource block for a device that includes * GPIOs to control enable, reset and stop operation of the device. Each diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 2e23d43..b7abaff 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -3,6 +3,7 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H +#include <acpi/acpi_device.h> #include <stdint.h> /* Return the clock frequency UART uses as reference clock for @@ -97,5 +98,8 @@ return uart_rx_byte(CONF_UART_FOR_GDB); } #endif +void update_spcr_data(struct acpi_spcr *spcr); +void update_spcr_8250mem(struct acpi_spcr *spcr); +void update_spcr_8250io(struct acpi_spcr *spcr); #endif /* CONSOLE_UART_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a Gerrit-Change-Number: 49317 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46941 ) Change subject: cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot ...................................................................... cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot Commit 542307b (broadwell: Add small delay before Flex Ratio reboot) introduced a workaround for Broadwell. Implement it on Haswell as well. Since this is only necessary when a TPM is present on a system, only do the delay (which is not that small, to be honest) on TPM-enabled builds. Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/bootblock.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46941/1 diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index c9e3f2a..7066637 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -4,6 +4,7 @@ #include <arch/bootblock.h> #include <cpu/x86/msr.h> #include <arch/io.h> +#include <delay.h> #include <halt.h> #include "haswell.h" @@ -50,6 +51,10 @@ /* Set soft reset control to use register value */ RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Delay before reset to avoid potential TPM lockout */ + if (CONFIG(TPM1) || CONFIG(TPM2)) + mdelay(30); + /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); -- To view, visit https://review.coreboot.org/c/coreboot/+/46941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596 Gerrit-Change-Number: 46941 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: cpu/intel/haswell: Allow tuning VR for C-state operations
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46920 ) Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ...................................................................... cpu/intel/haswell: Allow tuning VR for C-state operations Apply commit ff0f460 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification. Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46920/1 diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 9db1ad3..16f1079 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,6 +3,35 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC +#include <stdbool.h> +#include <stdint.h> + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; + + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; + + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + struct cpu_intel_haswell_config { int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5e9b742..5838f1f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -249,8 +249,17 @@ static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr; + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n"); /* Configure VR_CURRENT_CONFIG. */ @@ -280,13 +289,23 @@ msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Gerrit-Change-Number: 46920 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: cpu/intel/haswell: Raise PSI1 threshold to 20A
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46919 ) Change subject: cpu/intel/haswell: Raise PSI1 threshold to 20A ...................................................................... cpu/intel/haswell: Raise PSI1 threshold to 20A Haswell reference code version 1.9.0 uses the same value as Broadwell. Change-Id: I979ea1b4ba2962bd0c55cfb9d0c291f32cf5fcad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46919/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4b927d7..5e9b742 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -260,7 +260,7 @@ msr.hi &= 0xc0000000; msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ if (haswell_is_ult()) msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I979ea1b4ba2962bd0c55cfb9d0c291f32cf5fcad Gerrit-Change-Number: 46919 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: cpu/intel/haswell: Enable turbo ratio if available
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46918 ) Change subject: cpu/intel/haswell: Enable turbo ratio if available ...................................................................... cpu/intel/haswell: Enable turbo ratio if available Commit 7f28e4e (broadwell: Enable turbo ratio if available) is also applicable to Haswell, since the MSR definitions are the same for both. Change-Id: Ic5f30a5b06301449253bbfb9ed58c6b35a767763 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46918/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 6f483a5..4b927d7 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -547,7 +547,10 @@ perf_ctl.hi = 0; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; @@ -606,9 +609,6 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -664,6 +664,9 @@ static void post_mp_init(void) { + /* Set Max Ratio */ + set_max_ratio(); + /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ global_smi_enable(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5f30a5b06301449253bbfb9ed58c6b35a767763 Gerrit-Change-Number: 46918 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021