coreboot-gerrit January 2021

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Change in coreboot[master]: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46917 ) Change subject: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR ...................................................................... cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR This MSR only needs to be programmed when IO MWAIT is to be enabled. The code came from Sandy Bridge, which already showed this inconsistency. Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46917/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 21f3f4a..6f483a5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -452,12 +452,6 @@ /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); - msr.lo &= ~0xffff; - msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); - msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/46917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Gerrit-Change-Number: 46917 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: make uart_max_index's value reflect what its name pretends
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49305 ) Change subject: soc/intel: make uart_max_index's value reflect what its name pretends ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Wouldn't it be even better to rename it to `uart_..._size` instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/49305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Gerrit-Change-Number: 49305 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 23:40:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/lpgcc: Drop redundant linker path
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47632 ) Change subject: libpayload/lpgcc: Drop redundant linker path ...................................................................... libpayload/lpgcc: Drop redundant linker path It either doesn't exist (in-tree builds) or is the same as $_LIBDIR. Change-Id: I9551cbfc3295d86c22a3785be7cdc0f65eeb08c4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/47632/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index cff9fe0..b90c120 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -166,7 +166,7 @@ _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" +_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/47632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9551cbfc3295d86c22a3785be7cdc0f65eeb08c4 Gerrit-Change-Number: 47632 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/lpgcc: Set proper include paths for in-tree builds
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47631 ) Change subject: libpayload/lpgcc: Set proper include paths for in-tree builds ...................................................................... libpayload/lpgcc: Set proper include paths for in-tree builds Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47631/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index fa16149..cff9fe0 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -143,14 +143,19 @@ shift done -_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_OBJ -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" -if [ "$CONFIG_LP_PDCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses" -fi +if [ $_LIBDIR = $_OBJ ]; then + _CFLAGS="$_CFLAGS -I$_OBJ" -if [ "$CONFIG_LP_TINYCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses" + if [ "$CONFIG_LP_PDCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses -I$BASE/../curses/pdcurses-backend" + _CFLAGS="$_CFLAGS -I$BASE/../curses/form -I$BASE/../curses/menu" + fi + + if [ "$CONFIG_LP_TINYCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses" + fi fi # Check for the -fno-stack-protector silliness -- To view, visit https://review.coreboot.org/c/coreboot/+/47631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643 Gerrit-Change-Number: 47631 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/lpgcc: Add more variables to support in-tree builds
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47630 ) Change subject: libpayload/lpgcc: Add more variables to support in-tree builds ...................................................................... libpayload/lpgcc: Add more variables to support in-tree builds Add $_DOTCONFIG and $_XCOMPILE pointing to the respective files and use them. Change-Id: I719b42d1c8abf055948daf5b000daa30cd249edd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47630/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 1e63d05..fa16149 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -57,11 +57,17 @@ # This will set the _LIBDIR and _INCDIR variables used below . $BASE/lp.functions +if [ $_LIBDIR != $_OBJ ]; then + _DOTCONFIG=$BASE/../libpayload.config + _XCOMPILE=$BASE/../libpayload.xcompile +else + _DOTCONFIG=$_OBJ/libpayload.config + _XCOMPILE=$BASE/../.xcompile +fi + # include libpayload config -if [ -f $BASE/../libpayload.config ]; then - . $BASE/../libpayload.config -elif [ -f $BASE/../.config ]; then - . $BASE/../.config +if [ -f $_DOTCONFIG ]; then + . $_DOTCONFIG else echo "Can't find config" exit 1 @@ -174,8 +180,8 @@ exit 1 fi - if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config && - grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then + if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] && + grep -q fix-cortex-a53-843419 $_XCOMPILE; then _LDFLAGS="$_LDFLAGS -Wl,--fix-cortex-a53-843419" fi -- To view, visit https://review.coreboot.org/c/coreboot/+/47630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I719b42d1c8abf055948daf5b000daa30cd249edd Gerrit-Change-Number: 47630 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Fix programming command timings
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Felix Singer, Angel Pons, Arthur Heymans, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49287 ) Change subject: nb/intel/sandybridge: Fix programming command timings ...................................................................... Patch Set 1: Code-Review-1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49287/comment/324ac70a_1eb834dc PS1, Line 11: That's basically an empty commit message. If you want to avoid documenting what the interim code did wrong, how about a revert and then let people review against the original code? Patchset: PS1: Looks like this is mixing refactorings with a fix for a commit that mixed so many refactorings together that it broke things unnoticed... please stop this mess. I've also left some `resolved` comments that would make it much easier to review if they were handled in advance. File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/c/coreboot/+/49287/comment/d21c1302_c2c4d89c PS1, Line 943: FOR_ALL_POPULATED_RANKS { Please consider making these macros readable before any further reviews. https://review.coreboot.org/c/coreboot/+/49287/comment/c48d5364_1ed01386 PS1, Line 939: /* : * Compute command phase shift as the most negative CCC setting : * across all ranks. Use zero if none of the values is negative. : */ : FOR_ALL_POPULATED_RANKS { : cmd_delay = MAX(cmd_delay, -ctrl->timings[channel][slotrank].pi_coding); : } : This part looks like a mere refactoring. What's the fix? did I miss something? https://review.coreboot.org/c/coreboot/+/49287/comment/337a02bc_ad161a8b PS1, Line 1000: gdcr_cmd_pi_coding_reg This type is only used once. If there is no intention to change that, please please please kill it. The type information is very valuable to the reader and should only be hidden in a header file as a last resort (if shared by multiple compilation units). You can also declare it right here as anonymous union. -- To view, visit https://review.coreboot.org/c/coreboot/+/49287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33b2271803e6fa3d8e625bfe5a830152cab2b9d4 Gerrit-Change-Number: 49287 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 23:26:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus: add audio codec into SSFC support for Meep
by Tony Huang (Code Review) 11 Jan '21

11 Jan '21

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48945 ) Change subject: mb/google/octopus: add audio codec into SSFC support for Meep ...................................................................... mb/google/octopus: add audio codec into SSFC support for Meep Also change GPIO_137 for headphone detect DA7219 set to level trigger RT5682 set to edge_both trigger BUG=b:171757619 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/meep/overridetree.cb M src/mainboard/google/octopus/variants/meep/variant.c 4 files changed, 106 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48945/1 diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 6e3dbf4..4e24e5a 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -40,6 +40,7 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_AMPTON bool "-> Ampton" diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 31cd64e..91fcc81 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/cbi_ssfc.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <gpio.h> @@ -15,6 +16,18 @@ DISPUPD), }; +static const struct pad_config rt5682_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* GPIO_137 -- HP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, + DISPUPD), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), +}; + static const struct pad_config hdmi_sku_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -29,19 +42,45 @@ DISPUPD), }; +static const struct pad_config rt5682_hdmi_sku_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, NONE, DEEP, NF1, HIZCRx1, + DISPUPD), + /* HV_DDI1_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1, + DISPUPD), + /* GPIO_137 -- HP_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { uint32_t sku_id; sku_id = google_chromeec_get_board_sku(); + uint32_t codec = ssfc_get_audio_codec(); switch (sku_id) { case SKU_33_DORP: case SKU_34_DORP: case SKU_35_DORP: case SKU_36_DORP: + if (codec == SSFC_AUDIO_CODEC_RT5682) { + *num = ARRAY_SIZE(hdmi_sku_override_table); + return rt5682_hdmi_sku_override_table; + } *num = ARRAY_SIZE(hdmi_sku_override_table); return hdmi_sku_override_table; default: + if (codec == SSFC_AUDIO_CODEC_RT5682) { + *num = ARRAY_SIZE(rt5682_override_table); + return rt5682_override_table; + } *num = ARRAY_SIZE(default_override_table); return default_override_table; } diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index a29d6fa..8752141 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -181,6 +181,19 @@ register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index df4dbd6..362b219 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -5,6 +5,53 @@ #include <baseboard/variants.h> #include <variant/sku.h> #include <sar.h> +#include <baseboard/cbi_ssfc.h> +#include <console/console.h> +#include <device/device.h> +#include <soc/pci_devs.h> +#include <string.h> + +static void audio_codec_init_by_SSFC(void) +{ +#if !DEVTREE_EARLY + struct device *audio_i2c_host; + const struct device *audio_dev; + const struct bus *audio_i2c_bus; + char name; + + audio_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C5); + audio_i2c_bus = audio_i2c_host->link_list; + audio_dev = audio_i2c_bus->children; + + switch (ssfc_get_audio_codec()) { + case SSFC_AUDIO_CODEC_DEFAULT: + case SSFC_AUDIO_CODEC_DA7219: + name = 'D'; + printk(BIOS_INFO, "Enable DA7219.\n"); + break; + case SSFC_AUDIO_CODEC_RT5682: + name = 'R'; + printk(BIOS_ERR, "Enable RT5682.\n"); + break; + default: + printk(BIOS_ERR, + "can't identify any audio codec source from SSFC.\n"); + return; + } + + for (audio_dev = audio_dev; audio_dev; audio_dev = audio_dev->sibling) { + if (audio_dev->chip_ops && audio_dev->chip_ops->enable_dev) + audio_dev->chip_ops->enable_dev((struct device *)audio_dev); + printk(BIOS_ERR, "audio codec dev path %s.\n", + dev_name((struct device *)audio_dev)); + + if (!strncmp(dev_name(audio_dev), &name, 1)) + ((struct device *)audio_dev)->enabled = 1; + else + ((struct device *)audio_dev)->enabled = 0; + } +#endif +} const char *get_wifi_sar_cbfs_filename(void) { @@ -51,3 +98,9 @@ return "vbt.bin"; } } + +void variant_update_devtree(struct device *dev) +{ + + audio_codec_init_by_SSFC(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd Gerrit-Change-Number: 48945 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/boten: Update LTE GPIO configuration
by Furquan Shaikh (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Evan Green, Tim Wawrzynczak, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48623 ) Change subject: mb/google/dedede/var/boten: Update LTE GPIO configuration ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/48623/comment/572bc16e_02dbabb6 PS3, Line 9: LTE module is not expected to be powered off during warm reset Is there any expectation w.r.t. LTE firmware reload after a warm reset? (OS updates trigger a warm reset). -- To view, visit https://review.coreboot.org/c/coreboot/+/48623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8676da6186559288aabe078b6158fc01075c7b41 Gerrit-Change-Number: 48623 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 22:44:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PCH ID 0x5182
by Furquan Shaikh (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49301 ) Change subject: soc/intel/alderlake: Add PCH ID 0x5182 ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/lpc/lpc.c: https://review.coreboot.org/c/coreboot/+/49301/comment/6f77ae65_a04b5428 PS1, Line 308: PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, : PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, nit: Place this up with rest of the ADP_P_ESPI above? -- To view, visit https://review.coreboot.org/c/coreboot/+/49301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Gerrit-Change-Number: 49301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 22:42:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp
by Jonathan Zhang (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Marc Jones, Patrick Rudolph, Johnny Lin, Jingle Hsu, Angel Pons, Morgan Jang, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49235 ) Change subject: ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Gerrit-Change-Number: 49235 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 22:32:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021