coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/volteer: Add CSE Lite SKU support to Copano
by Tim Wawrzynczak (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Hao Chou. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49290 ) Change subject: mb/google/volteer: Add CSE Lite SKU support to Copano ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I875f6b32c4053ef6d23ad7606cd35a129a78c306 Gerrit-Change-Number: 49290 Gerrit-PatchSet: 1 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 16:19:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Provide EC access path for Retimer firmware update
by Tim Wawrzynczak (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: John Zhao, Duncan Laurie, Brandon Breitenstein, Rajmohan Mani. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49257 ) Change subject: ec/google/chromeec: Provide EC access path for Retimer firmware update ...................................................................... Patch Set 1: (1 comment) File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/49257/comment/cb26be31_b6c0697f PS1, Line 242: RFWU I don't see this added to `ec/google/chromeec/acpi/ec.asl` -- To view, visit https://review.coreboot.org/c/coreboot/+/49257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b Gerrit-Change-Number: 49257 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 16:17:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/haswell: Do not determine CPU type at runtime
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46912 ) Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ...................................................................... cpu/intel/haswell: Do not determine CPU type at runtime It is already known at compile-time. Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46912/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 0701332..deadbc5 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -145,8 +145,9 @@ int cpu_config_tdp_levels(void); /* CPU identification */ -int haswell_family_model(void); -int haswell_stepping(void); -int haswell_is_ult(void); +static inline int haswell_is_ult(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4b73c6a..15dcff5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -186,27 +186,6 @@ [0x11] = 128, }; -int haswell_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -int haswell_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int haswell_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) - ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); - - return ult; -} - /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Gerrit-Change-Number: 46912 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN value
by Rob Barnes (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Frank Wu, John Su, Furquan Shaikh, Martin Roth, Paul Menzel. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49236 ) Change subject: mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN value ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica6d04f9c48aa0800189283608bf57416ac75cf7 Gerrit-Change-Number: 49236 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 11 Jan 2021 15:36:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/board_status/board_status.sh: improve mktemp behaviour on non-li...
by Idwer Vollering (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: David Hendricks. Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49308 ) Change subject: util/board_status/board_status.sh: improve mktemp behaviour on non-linux OSes ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: v -- To view, visit https://review.coreboot.org/c/coreboot/+/49308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I763b0e7c7c81a2447ed20db0a25047d106e30606 Gerrit-Change-Number: 49308 Gerrit-PatchSet: 2 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 14:49:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Add coreboot build system support
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49312 to look at the new patch set (#2). Change subject: util/ifdtool: Add coreboot build system support ...................................................................... util/ifdtool: Add coreboot build system support When building as part of the coreboot build system, use the same mechanism as other tools (cbfstool, amdfwtool, ...) so that abuild builds ifdtool once into sharedutils instead of once per board (while avoiding other race conditions, too). Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc A util/ifdtool/Makefile.inc 2 files changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/49312/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Gerrit-Change-Number: 49312 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/board_status/board_status.sh: build the cbmem binary when absent
by Idwer Vollering (Code Review) 11 Jan '21

11 Jan '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49310 to look at the new patch set (#3). Change subject: util/board_status/board_status.sh: build the cbmem binary when absent ...................................................................... util/board_status/board_status.sh: build the cbmem binary when absent Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: Ia6442e8ba5e789fc5eab89b6796ec45635f1e923 --- M util/board_status/board_status.sh 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/49310/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6442e8ba5e789fc5eab89b6796ec45635f1e923 Gerrit-Change-Number: 49310 Gerrit-PatchSet: 3 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
by build bot (Jenkins) (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49313 ) Change subject: [WIP]soc/intel/apollolake: Select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/apollolake/cpu.c: https://review.coreboot.org/c/coreboot/+/49313/comment/c2ae3862_fcbe52fa PS1, Line 185: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/49313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc5468fdd86f88bc8a09a69bfbc59279d1e3828 Gerrit-Change-Number: 49313 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 14:22:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]soc/intel/apollolake: Select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49313 ) Change subject: [WIP]soc/intel/apollolake: Select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT ...................................................................... [WIP]soc/intel/apollolake: Select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT Use common mpinit code as GLK does. Drop now dead code path. Change-Id: Ibdc5468fdd86f88bc8a09a69bfbc59279d1e3828 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/cpu.h 4 files changed, 3 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/49313/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 62049b5..0f8846f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_APOLLOLAKE bool + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT help Intel Apollolake support @@ -8,7 +9,6 @@ default n select SOC_INTEL_APOLLOLAKE select SOC_INTEL_COMMON_BLOCK_CNVI - select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select IDT_IN_EVERY_STAGE diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9670a31..ac4924d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -202,20 +202,11 @@ .acpi_name = &soc_acpi_name, }; -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = apollolake_init_cpus, - .acpi_fill_ssdt = generate_cpu_entries, -}; - static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; else if (dev->path.type == DEVICE_PATH_GPIO) block_gpio_enable(dev); } diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 0ae170b..7d0cf8a 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -83,32 +83,6 @@ } } -#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) -static void soc_init_core(struct device *cpu) -{ - soc_core_init(cpu); -} - -static struct device_operations cpu_dev_ops = { - .init = soc_init_core, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, - { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, - { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, - { X86_VENDOR_INTEL, CPUID_GLK_A0 }, - { X86_VENDOR_INTEL, CPUID_GLK_B0 }, - { X86_VENDOR_INTEL, CPUID_GLK_R0 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; -#endif - /* * MP and SMM loading initialization. */ @@ -123,7 +97,6 @@ /* * Do essential initialization tasks before APs can be fired up. * - * IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP, * that are set prior to ramstage. * Real MTRRs are programmed after resource allocation. @@ -132,56 +105,12 @@ * external stage cache in TSEG does not flush off due to SMM relocation * during MP Init stage. * - * ELSE - - * Enable MTRRs on the BSP. This creates the MTRR solution that the - * APs will use. Otherwise APs will try to apply the incomplete solution - * as the BSP is calculating it. */ static void pre_mp_init(void) { - if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) { - fsps_load(romstage_handoff_is_resume()); - return; - } - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - - /* Enable the local CPU apics */ - setup_lapic(); + fsps_load(romstage_handoff_is_resume()); } -#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) -static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) -{ - msr_t msr; - msr = rdmsr(MSR_CORE_THREAD_COUNT); - *num_virt = (msr.lo >> 0) & 0xffff; - *num_phys = (msr.lo >> 16) & 0xffff; -} - -/* Find CPU topology */ -int get_cpu_count(void) -{ - unsigned int num_virt_cores, num_phys_cores; - - read_cpu_topology(&num_phys_cores, &num_virt_cores); - - printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", - num_phys_cores, num_virt_cores); - - return num_virt_cores; -} - -void get_microcode_info(const void **microcode, int *parallel) -{ - *microcode = intel_microcode_find(); - *parallel = 1; - - /* Make sure BSP is using the microcode from cbfs */ - intel_microcode_load_unlocked(*microcode); -} -#endif - static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { @@ -253,16 +182,4 @@ /* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); -} - -void apollolake_init_cpus(struct device *dev) -{ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - return; - soc_init_cpus(dev->link_list); - - /* Temporarily cache the memory-mapped boot media. */ - if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && - CONFIG(BOOT_DEVICE_SPI_FLASH)) - fast_spi_cache_bios_region(); -} +} \ No newline at end of file diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 38b830a..55eb6b2 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -7,7 +7,6 @@ #include <intelblocks/msr.h> struct device; -void apollolake_init_cpus(struct device *dev); void mainboard_devtree_update(struct device *dev); /* Flush L1D to L2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc5468fdd86f88bc8a09a69bfbc59279d1e3828 Gerrit-Change-Number: 49313 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Add coreboot build system support
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49312 ) Change subject: util/ifdtool: Add coreboot build system support ...................................................................... util/ifdtool: Add coreboot build system support When building as part of the coreboot build system, use the same mechanism as other tools (cbfstool, amdfwtool, ...) so that abuild builds ifdtool once into sharedutils instead of once per board (while avoiding other race conditions, too). Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc A util/ifdtool/Makefile.inc 2 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/49312/1 diff --git a/Makefile.inc b/Makefile.inc index ae61c2e..72f5d24 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -85,6 +85,7 @@ subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu +subdirs-y += util/ifdtool subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security @@ -576,10 +577,6 @@ BINCFG:=$(objutil)/bincfg/bincfg IFDTOOL:=$(objutil)/ifdtool/ifdtool -$(IFDTOOL): - @printf " Compile IFDTOOL\n" - +$(MAKE) -C $(top)/util/ifdtool - cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool diff --git a/util/ifdtool/Makefile.inc b/util/ifdtool/Makefile.inc new file mode 100644 index 0000000..66f099e --- /dev/null +++ b/util/ifdtool/Makefile.inc @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o + +IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror +IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include +IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap +IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h + +$(objutil)/ifdtool/%.o: $(top)/util/ifdtool/%.c + $(HOSTCC) $(IFDTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +$(objutil)/ifdtool/%.o: $(top)/util/cbfstool/flashmap/%.c + $(HOSTCC) $(IFDTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +$(objutil)/ifdtool/ifdtool: $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) + printf " IFDTOOL\n" + $(HOSTCC) $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) -o $@ + -- To view, visit https://review.coreboot.org/c/coreboot/+/49312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Gerrit-Change-Number: 49312 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021