Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49045 )
Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49045/comment/61240602_25c269a3
PS2, Line 32:
> L140CU done
Done
Patchset:
PS5:
will te
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Hello Felix Singer, build bot (Jenkins), Shaunak Saha, Patrick Georgi, Furquan Shaikh, Justin TerAvest, Matt DeVillier, Duncan Laurie, Paul Menzel, Patrick Rudolph, Lance Zhao, Nico Huber, Martin Roth, Tim Wawrzynczak, Shaunak Saha, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49045
to look at the new patch set (#5).
Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table
......................................................................
acpi,soc/intel/common: add support for Intel Low Power Idle Table
Add support for the Intel LPIT table to support reading Low Power Idle
Residency counters by the OS. On platforms supporting S0ix sleep states
there can be two types of residencies:
* CPU package PC10 residency counter (read from MSR via FFH interface)
* PCH SLP_S0 assertion residency counter (read via memory mapped
interface)
With presence of one or both of these counters in the LPIT table, Linux
dynamically adds the corresponding attributes to the cpuidle sysfs
interface, that can be used to read the residency timers:
* /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
* /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
The code in src/acpi implements generic LPIT support. Each SoC or
platform has to implement `acpi_fill_lpit` to fill the table with
platform-specific LPI state entries. This is done in this change for
soc/intel/common, while being added as its own compilation unit, so SoCs
not yet using common acpi code (like Skylake) can use it, too.
Reference:
https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle…
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
boots without crashing with an INTERNAL_POWER_ERROR.
- Windows and Linux tested on google/akemi together with CB:49046
- Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046
Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e
Tested-by: Matt DeVillier <matt.devillier(a)gmail.com>
Tested-by: Michael Niewöhner <foss(a)mniewoehner.de>
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/acpi/Kconfig
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/Makefile.inc
M src/soc/intel/common/block/acpi/acpi.c
A src/soc/intel/common/block/acpi/lpit.c
7 files changed, 182 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/49045/5
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49304 )
Change subject: cpu/mp_init: Fix microcode lock
......................................................................
Patch Set 1: Code-Review+2
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Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads
......................................................................
Patch Set 1: Code-Review+2
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49303 )
Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads
......................................................................
cpu/x86/mpinit: Serialize microcode updates for HT threads
This change affects Intel CPUs only. As most platforms are doing
uCode update using FIT, they aren't affect by this code either.
Update microcode in MP-init using a single spinlock when running on
a Hyper-Threading enabled CPU on pre FIT platforms.
This will slow down the MP-init boot flow.
Intel SDM and various BWGs specify to use a semaphore to update
microcode on one thread per code on Hyper-Threading enabled CPUs.
As complex code would be necessary determining the core #ID,
initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2,
only every use a global spinlock.
Assuming that only pre-FIT platforms with Hyper-Threading enabled and at
most 8 threads will ever run into this condition, the boot delay is
neglectable.
This change is a counterproposal to the previous published patch series
being much more unsophisticated.
Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/cpu/x86/sipi_vector.S
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/braswell/cpu.c
6 files changed, 21 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/49303/1
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index b56d106..ff6cbec 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -33,7 +33,7 @@
static void get_microcode_info(const void **microcode, int *parallel)
{
*microcode = microcode_patch;
- *parallel = 1;
+ *parallel = !intel_ht_supported();
}
/* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index db43353..88e42a5 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -251,7 +251,7 @@
{
microcode_patch = intel_microcode_find();
*microcode = microcode_patch;
- *parallel = 1;
+ *parallel = !intel_ht_supported();
}
static void per_cpu_smm_trigger(void)
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 2afbfee..b08a86f 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -497,7 +497,7 @@
{
microcode_patch = intel_microcode_find();
*microcode = microcode_patch;
- *parallel = 1;
+ *parallel = !intel_ht_supported();
}
static void per_cpu_smm_trigger(void)
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index 02ad0d3..0a963f7 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -102,6 +102,13 @@
/* Save CPU number. */
mov %ecx, %esi
+ /*
+ * The following code only need to run on Intel platforms and thus the caller
+ * doesn't provide a microcode_ptr if not on Intel.
+ * On Intel platforms which update microcode using FIT the version check will
+ * also skip the microcode update.
+ */
+
/* Determine if one should check microcode versions. */
mov microcode_ptr, %edi
test %edi, %edi
@@ -116,6 +123,15 @@
test %edx, %edx
jnz microcode_done
+ /*
+ * Intel SDM and various BWGs specify to use a semaphore to update microcode
+ * on one thread per code on Hyper-Threading enabled CPUs. As complex code would be
+ * necessary determining the core #ID, initializing and picking the right semaphore
+ * out of CONFIG_MAX_CPUS / 2, only every use a global spinlock.
+ * Assuming that only pre-FIT platforms with Hyper-Threading enabled and at
+ * most 8 threads will ever run into this condition, the boot delay is neglectable.
+ */
+
/* Determine if parallel microcode loading is allowed. */
cmpl $0xffffffff, microcode_lock
je load_microcode
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 2029017..e624240 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -149,7 +149,7 @@
const struct pattrs *pattrs = pattrs_get();
*microcode = pattrs->microcode_patch;
- *parallel = 1;
+ *parallel = !intel_ht_supported();
}
static void per_cpu_smm_trigger(void)
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 04bf108..0c6f463 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -152,7 +152,7 @@
const struct pattrs *pattrs = pattrs_get();
*microcode = pattrs->microcode_patch;
- *parallel = 1;
+ *parallel = !intel_ht_supported();
}
static void per_cpu_smm_trigger(void)
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Change subject: soc/intel/skylake/acpi: Add PEP table
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49140/comment/5f12db38_63aefde5
PS3, Line 11:
> Hmm. Not sure what I want to see, but it's probably not "CPU did not enter SLP_S0!!! (S0ix cnt=0). […]
Righht, Slp_S0 is not a requirement, when it's not connected. Does the cpu residency counter increase?
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Change subject: mb/google/volteer: Add CSE Lite SKU support to Copano
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Patch Set 1: Code-Review+1
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