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Change in coreboot[master]: soc/intel/common: Move L1_substates_control to pcie_rp.h
by EricR Lai (Code Review) 11 Jan '21

11 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49295 ) Change subject: soc/intel/common: Move L1_substates_control to pcie_rp.h ...................................................................... soc/intel/common: Move L1_substates_control to pcie_rp.h L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 --- M src/soc/intel/alderlake/chip.h M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 5 files changed, 12 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/49295/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 8e59c9a..f23b9d2 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/pcie_rp.h> #include <soc/gpe.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -136,12 +137,7 @@ uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index ca50b13..0115c4b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -34,4 +34,11 @@ */ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); +enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 37237bb..49af0d0 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -116,12 +116,7 @@ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3b81339..e74d8ce 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -114,12 +114,7 @@ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f38330b..29171a5 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -247,12 +247,7 @@ uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; -- To view, visit https://review.coreboot.org/c/coreboot/+/49295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Gerrit-Change-Number: 49295 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Fix toctree and remove dead links
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49292 ) Change subject: Documentation: Fix toctree and remove dead links ...................................................................... Documentation: Fix toctree and remove dead links Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/drivers/index.md M Documentation/mainboard/index.md M Documentation/soc/intel/icelake/iceLake_coreboot_development.md M Documentation/soc/intel/index.md 4 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/49292/1 diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 508beaf..40d747d 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -4,7 +4,9 @@ and plugin devices, significantly reducing integration complexity and they allow to easily reuse existing code accross platforms. +* [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) * [SMMSTORE](smmstore.md) * [SoundWire](soundwire.md) * [SMMSTOREv2](smmstorev2.md) +* [USB4 Retimer](retimer.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1f8f6bc2..b558760 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -16,6 +16,7 @@ ## ASUS +- [A88XM-E](asus/a88xm-e.md) - [F2A85-M](asus/f2a85-m.md) - [P5Q](asus/p5q.md) - [P8H61-M LX](asus/p8h61-m_lx.md) diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 5f8e279..2147331 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -20,11 +20,6 @@ :doc:`../../../mainboard/intel/icelake_rvp` ``` -3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google - ```eval_rst - :doc:`../../../mainboard/google/dragonegg` - ``` - ### Summary: * SoC is Ice Lake. * Reference platform is icelake_rvp. diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 5c7239a..71e427e 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -11,4 +11,4 @@ - [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) -- [CSE FW Update](cse_fw_update/cse_fw_update_model.md) +- [CSE FW Update](cse_fw_update/cse_fw_update.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/49292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Gerrit-Change-Number: 49292 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sconfig: Emit chip config pointers for PCI devices on root bus
by Furquan Shaikh (Code Review) 11 Jan '21

11 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49214 ) Change subject: sconfig: Emit chip config pointers for PCI devices on root bus ...................................................................... sconfig: Emit chip config pointers for PCI devices on root bus This change emits chip config pointers for PCI devices on root bus in static_devices.h so that the config structure can be accessed directly without having to reference the device structure. This allows the linker to optimize out unused parts of the device tree from early stages like bootblock. Change-Id: I1d42e926dbfae14b889ade6dda363d8607974cae Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/sconfig/main.c 1 file changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/49214/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 175b926..7bce227 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1085,12 +1085,9 @@ fprintf(fil, "\t};\n"); } -static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) +static struct chip_instance *get_chip_instance(const struct device *dev) { - int pin; - struct chip_instance *chip_ins = ptr->chip_instance; - int has_children = dev_has_children(ptr); - + struct chip_instance *chip_ins = dev->chip_instance; /* * If the chip instance of device has base_chip_instance pointer set, then follow that * to update the chip instance for current device. @@ -1098,6 +1095,15 @@ if (chip_ins->base_chip_instance) chip_ins = chip_ins->base_chip_instance; + return chip_ins; +} + +static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) +{ + int pin; + struct chip_instance *chip_ins = get_chip_instance(ptr); + int has_children = dev_has_children(ptr); + /* Emit probe structures. */ if (ptr->probe && (emit_fw_config_probe(fil, ptr) < 0)) { if (head) @@ -1209,12 +1215,19 @@ static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next) { + struct chip_instance *chip_ins = get_chip_instance(ptr); + /* Only devices on root bus here. */ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + + fprintf(head, "extern DEVTREE_CONST void *DEVTREE_CONST __pci_0_%02x_%d_config;\n", + ptr->path_a, ptr->path_b); + fprintf(fil, "DEVTREE_CONST void *DEVTREE_CONST __pci_0_%02x_%d_config = &%s_info_%d;\n", + ptr->path_a, ptr->path_b, chip_ins->chip->name_underscore, chip_ins->id); } if (ptr->bustype == PNP) { -- To view, visit https://review.coreboot.org/c/coreboot/+/49214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d42e926dbfae14b889ade6dda363d8607974cae Gerrit-Change-Number: 49214 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezzane: Add a minimal chipset tree
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49245 ) Change subject: soc/amd/cezzane: Add a minimal chipset tree ...................................................................... soc/amd/cezzane: Add a minimal chipset tree This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc(). Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49245 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/chipset.cb 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 22d0c3a..afee1ef 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -26,6 +26,10 @@ select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H +config CHIPSET_DEVICETREE + string + default "soc/amd/cezanne/chipset.cb" + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb new file mode 100644 index 0000000..49bd0c8 --- /dev/null +++ b/src/soc/amd/cezanne/chipset.cb @@ -0,0 +1,5 @@ +chip soc/amd/cezanne + device domain 0 on + device pci 00.0 alias gnb on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/49245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Gerrit-Change-Number: 49245 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/sconfig: Change __pci*|__pnp* device pointers to const
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49242 ) Change subject: util/sconfig: Change __pci*|__pnp* device pointers to const ...................................................................... util/sconfig: Change __pci*|__pnp* device pointers to const This change updates the device pointers exposed in static_devices.h to const instead of DEVTREE_CONST. The pointer itself doesn't really need to be DEVTREE_CONST. Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49242 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M util/sconfig/main.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 175b926..1af55ac 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1211,16 +1211,16 @@ { /* Only devices on root bus here. */ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { - fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", + fprintf(head, "extern DEVTREE_CONST struct device *const __pci_0_%02x_%d;\n", ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", + fprintf(fil, "DEVTREE_CONST struct device *const __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); } if (ptr->bustype == PNP) { - fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n", + fprintf(head, "extern DEVTREE_CONST struct device *const __pnp_%04x_%02x;\n", ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", + fprintf(fil, "DEVTREE_CONST struct device *const __pnp_%04x_%02x = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/49242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Gerrit-Change-Number: 49242 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/uart: Use simple(_s_) variants of PCI functions
by Furquan Shaikh (Code Review) 11 Jan '21

11 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49213 ) Change subject: soc/intel/common/uart: Use simple(_s_) variants of PCI functions ...................................................................... soc/intel/common/uart: Use simple(_s_) variants of PCI functions This change updates various uart_* functions to use simple(_s_) variants of PCI functions. This is done for a few reasons: * __SIMPLE_DEVICE__ check can be dropped since the same data type can be used in early stages and ramstage. * Removes the requirement on early stage to walk the device tree to get access to the device structure. This allows linker-based device tree optimizations for early stages. As part of this change, uart_get_device() is refactored and a new function uart_console_get_devfn() is added which returns pci_devfn_t in MMCONF format. It is then used directly by the _s_ variants of PCI functions. Change-Id: I344037828118572ae5eb27c82c496d5e7a508a53 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/uart/uart.c 1 file changed, 37 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/49213/1 diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 1cfdb67..8a8582e 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -23,10 +23,10 @@ extern const struct uart_controller_config uart_ctrlr_config[]; extern const int uart_max_index; -static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) +static void uart_lpss_init(pci_devfn_t devfn, uintptr_t baseaddr) { /* Ensure controller is in D0 state */ - lpss_set_power_state(PCI_BDF(dev), STATE_D0); + lpss_set_power_state(devfn, STATE_D0); /* Take UART out of reset */ lpss_reset_release(baseaddr); @@ -58,60 +58,49 @@ return UART_CONSOLE_INVALID_INDEX; } -static void uart_common_init(const struct device *device, uintptr_t baseaddr) +static pci_devfn_t uart_console_get_devfn(void) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_BDF(device); -#else - const struct device *dev = device; -#endif + int devfn; + int index; - /* Set UART base address */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); - - /* Enable memory access and bus master */ - pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); - - uart_lpss_init(device, baseaddr); -} - -const struct device *uart_get_device(void) -{ /* * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE * config option is not selected. * By default return NULL in this case to avoid compilation errors. */ if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + return 0; + + index = uart_get_valid_index(); + if (index == UART_CONSOLE_INVALID_INDEX) + return 0; + + devfn = uart_ctrlr_config[index].devfn; + return PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); +} + +const struct device *uart_get_device(void) +{ + pci_devfn_t devfn = uart_console_get_devfn(); + if (devfn == 0) return NULL; - int console_index = uart_get_valid_index(); - - if (console_index != UART_CONSOLE_INVALID_INDEX) - return pcidev_path_on_root(uart_ctrlr_config[index].devfn); - else - return NULL; + return pcidev_path_on_root(PCI_DEV2DEVFN(devfn)); } bool uart_is_controller_initialized(void) { uintptr_t base; - const struct device *dev_uart = uart_get_device(); + pci_devfn_t devfn = uart_console_get_devfn(); - if (!dev_uart) + if (devfn == 0) return false; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_BDF(dev_uart); -#else - const struct device *dev = dev_uart; -#endif - - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; + base = pci_s_read_config32(devfn, PCI_BASE_ADDRESS_0) & ~0xFFF; if (!base) return false; - if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) + if ((pci_s_read_config16(devfn, PCI_COMMAND) & UART_PCI_ENABLE) != UART_PCI_ENABLE) return false; @@ -129,15 +118,19 @@ void uart_bootblock_init(void) { - const struct device *dev_uart; + const uint32_t baseaddr = CONFIG_CONSOLE_UART_BASE_ADDRESS; + pci_devfn_t devfn = uart_console_get_devfn(); - dev_uart = uart_get_device(); - - if (!dev_uart) + if (devfn == 0) return; - /* Program UART BAR0, command, reset and clock register */ - uart_common_init(dev_uart, CONFIG_CONSOLE_UART_BASE_ADDRESS); + /* Set UART base address */ + pci_s_write_config32(devfn, PCI_BASE_ADDRESS_0, baseaddr); + + /* Enable memory access and bus master */ + pci_s_write_config16(devfn, PCI_COMMAND, UART_PCI_ENABLE); + + uart_lpss_init(devfn, baseaddr); /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); @@ -221,10 +214,11 @@ if (uart_controller_needs_init(dev)) { uintptr_t base; + pci_devfn_t devfn = PCI_BDF(dev); - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; + base = pci_s_read_config32(devfn, PCI_BASE_ADDRESS_0) & ~0xFFF; if (base) - uart_lpss_init(dev, base); + uart_lpss_init(devfn, base); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/49213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I344037828118572ae5eb27c82c496d5e7a508a53 Gerrit-Change-Number: 49213 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49104 ) Change subject: soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S ...................................................................... soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL), and oryp6 (CML). References: - TigerLake FSP Integration Guide - Intel Document Number 337868-002 Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49104 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 73b1bb5..dd9c806 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -524,6 +524,53 @@ params->PeiGraphicsPeimInit = 0; params->PavpEnable = CONFIG(PAVP); + + /* + * Prevent FSP from programming write-once subsystem IDs by providing + * a custom SSID table. Must have at least one entry for the FSP to + * use the table. + */ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; /* Register offset */ + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t :4; + uint64_t segment:16; + uint64_t :16; + }; + uint64_t segbusdevfuncregister; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t reserved; + }; + + /* + * The xHCI and HDA devices have RW/L rather than RW/O registers for + * subsystem IDs and so must be written before FspSiliconInit locks + * them with their default values. + */ + const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA }; + static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)]; + + for (i = 0; i < ARRAY_SIZE(devfn_table); i++) { + ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; + ssid_table[i].device = PCI_SLOT(devfn_table[i]); + ssid_table[i].function = PCI_FUNC(devfn_table[i]); + dev = pcidev_path_on_root(devfn_table[i]); + if (dev) { + ssid_table[i].svid = dev->subsystem_vendor; + ssid_table[i].ssid = dev->subsystem_device; + } + } + + params->SiSsidTablePtr = (uintptr_t)ssid_table; + params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Gerrit-Change-Number: 49104 Gerrit-PatchSet: 12 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Set FORCE_PWR low at boot time
by John Zhao (Code Review) 11 Jan '21

11 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48649 ) Change subject: mb/google/volteer: Set FORCE_PWR low at boot time ...................................................................... mb/google/volteer: Set FORCE_PWR low at boot time While FORCE_PWR is set high, it prevents retimer from entering low power state. S0ix failure occurs while USB4 Gatkex is connected on Port-0. This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be toggled by kernel through DSM method while updating retimer firmware. BUG=b:174166586 TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 --- M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/todor/gpio.c M src/mainboard/google/volteer/variants/voema/gpio.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48649/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 922d3d1..2030f31 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -308,7 +308,7 @@ /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H11 : SRCCLKREQ5# ==> NC */ PAD_NC(GPP_H11, NONE), /* H12 : M2_SKT2_CFG0 ==> NONE */ diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index d5498d0..79722d8 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -139,7 +139,7 @@ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c index 40d25a5..0391964 100644 --- a/src/mainboard/google/volteer/variants/todor/gpio.c +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -147,7 +147,7 @@ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c index d905dae..5bf6fad 100644 --- a/src/mainboard/google/volteer/variants/voema/gpio.c +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -137,7 +137,7 @@ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 Gerrit-Change-Number: 48649 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP wi...
by Subrata Banik (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49291 to look at the new patch set (#2). Change subject: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG ...................................................................... soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG This ENABLE_DISPLAY_OVER_DGPU Kconfig will allow ADLRVP to work with DG over PCIE to get display. Also ensure to turn off running IGD initialization using FSP GOP when ENABLE_DISPLAY_OVER_DGPU is enable. TEST=Able to get Pre-OS splash screen with AMD Radeon RX 5700 PCI-E DGPU when mainboard user selects ENABLE_DISPLAY_OVER_DGPU. Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/Kconfig 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/49291/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Gerrit-Change-Number: 49291 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/picasso: Separate GPIO define into gpio_defs.h
by EricR Lai (Code Review) 11 Jan '21

11 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49216 ) Change subject: soc/amd/picasso: Separate GPIO define into gpio_defs.h ...................................................................... soc/amd/picasso: Separate GPIO define into gpio_defs.h Separate GPIO define into gpio_defs.h, then we can use it in asl include. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: If2a779eae228f621e77610889205853de2fb179a --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/gpio_banks.h A src/soc/amd/common/block/include/amdblocks/gpio_defs.h 3 files changed, 250 insertions(+), 244 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/49216/1 diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 8640cc1..df55cbf 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/iomap.h> - -#define GPIO_INPUT_SHIFT 16 -#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) -#define GPIO_OUTPUT_SHIFT 22 -#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) +#include <amdblocks/gpio_defs.h> /* Get pin control MMIO address */ Method (GPAD, 0x1) diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index b6162d7..6524d05 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -4,6 +4,7 @@ #define AMD_BLOCK_GPIO_BANKS_H #include <types.h> +#include "gpio_defs.h" struct soc_amd_gpio { uint8_t gpio; @@ -17,13 +18,6 @@ uint8_t event; }; -#define GPIO_MASTER_SWITCH 0xFC -#define GPIO_MASK_STS_EN BIT(28) -#define GPIO_INTERRUPT_EN BIT(30) -#define GPIO_WAKE_EN BIT(31) - -#define GPIO_WAKE_STAT_0 0x2F0 -#define GPIO_WAKE_STAT_1 0x2F4 struct gpio_wake_state { uint32_t control_switch; uint32_t wake_stat[2]; @@ -38,59 +32,6 @@ /* Add gpio events to the eventlog. */ void gpio_add_events(const struct gpio_wake_state *state); -#define GPIO_PIN_IN (1 << 0) /* for byte access */ -#define GPIO_PIN_OUT (1 << 6) /* for byte access */ - -/* Pad trigger type - Level or Edge */ -#define GPIO_TRIGGER_EDGE (0 << 8) -#define GPIO_TRIGGER_LEVEL (1 << 8) -#define GPIO_TRIGGER_MASK (1 << 8) - -/* - * Pad polarity: - * Level trigger - High or Low - * Edge trigger - High (Rising), Low (Falling), Both - */ -#define GPIO_ACTIVE_HIGH (0 << 9) -#define GPIO_ACTIVE_LOW (1 << 9) -#define GPIO_ACTIVE_BOTH (2 << 9) -#define GPIO_ACTIVE_MASK (3 << 9) - -/* - * Pad trigger and polarity configuration. - * This determines the filtering applied on the input signal at the pad. - */ -#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) -#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) - -#define GPIO_INT_ENABLE_STATUS (1 << 11) -#define GPIO_INT_ENABLE_DELIVERY (1 << 12) -#define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_INT_ENABLE_MASK (3 << 11) - -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) - -#define GPIO_PIN_STS (1 << 16) -#define GPIO_8KPULLUP_SELECT (1 << 19) -#define GPIO_PULLUP_ENABLE (1 << 20) -#define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (7 << 19) - -#define GPIO_OUTPUT_SHIFT 22 -#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) -#define GPIO_OUTPUT_ENABLE (1 << 23) -#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) - -#define GPIO_INT_STATUS (1 << 28) -#define GPIO_WAKE_STATUS (1 << 29) -#define GPIO_STATUS_MASK (3 << 28) - enum { GEVENT_0, GEVENT_1, @@ -126,39 +67,6 @@ GEVENT_31, }; -#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) -#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE - -#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) -#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE -#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE -#define GPIO_PULL_PULL_NONE 0 - -#define AMD_GPIO_MUX_MASK 0x03 - -/* - * Flags used for GPIO configuration. These provide additional information that does not go - * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. - */ -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) -#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) -#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) -#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) -#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) -#define GPIO_FLAG_SCI (1 << 2) -#define GPIO_FLAG_SMI (1 << 3) - -/* Trigger configuration for GPIO SCI/SMI events. */ -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ - GPIO_FLAG_EVENT_ACTIVE_HIGH) -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ - GPIO_FLAG_EVENT_ACTIVE_LOW) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ - GPIO_FLAG_EVENT_ACTIVE_HIGH) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ - GPIO_FLAG_EVENT_ACTIVE_LOW) - static inline bool is_gpio_event_level_triggered(uint32_t flags) { return (flags & GPIO_FLAG_EVENT_TRIGGER_MASK) == GPIO_FLAG_EVENT_TRIGGER_LEVEL; @@ -179,152 +87,6 @@ return (flags & GPIO_FLAG_EVENT_ACTIVE_MASK) == GPIO_FLAG_EVENT_ACTIVE_LOW; } -#define DEB_GLITCH_SHIFT 5 -#define DEB_GLITCH_LOW 1 -#define DEB_GLITCH_HIGH 2 -#define DEB_GLITCH_NONE 3 -#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) -#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) -#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) - -#define GPIO_TIMEBASE_61uS 0 -#define GPIO_TIMEBASE_183uS (1 << 4) -#define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) -#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) -#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) - -#define GPIO_DEB_MASK 0xff - -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (7 << 13) - -/* - * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` - * Bits that are preserved/untouched: - * - Reserved bits - * - Drive strength bits - * - Read only bits - */ -#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ - GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ - GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) - -/* - * Several macros are available to declare programming of GPIO pins. The defined macros and - * their parameters are: - * PAD_NF Define native alternate function for the pin. - * pin the pin to be programmed - * function the native function - * pull pull up, pull down or no pull - * PAD_GPI The pin is a GPIO input - * pin the pin to be programmed - * pull pull up, pull down or no pull - * PAD_GPO The pin is a GPIO output - * pin the pin to be programmed - * direction high or low - * PAD_INT The pin is regular interrupt that works while booting - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * action STATUS, DELIVER, STATUS_DELIVER - * PAD_SCI The pin is a SCI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH - * PAD_SMI The pin is a SMI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * event trigger LEVEL_LOW, LEVEL_HIGH - * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) - * PAD_DEBOUNCE The input or interrupt will be debounced - * pin the pin to be programmed - * pull pull up, pull down or no pull - * debounce_type preserve low glitch, preserve high glitch, no glitch - * debounce_time the debounce time - */ - -#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ - { \ - .gpio = __pin, \ - .function = __function, \ - .control = __control, \ - .flags = __flags, \ - } - -#define PAD_CFG_STRUCT(__pin, __function, __control) \ - PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) - -#define PAD_PULL(__pull) GPIO_PULL_ ## __pull -#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir -#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig -#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action -#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig -#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake -#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb - -/* Native function pad configuration */ -#define PAD_NF(pin, func, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) - -/* General purpose input pad configuration */ -#define PAD_GPI(pin, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) - -/* General purpose output pad configuration */ -#define PAD_GPO(pin, direction) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) - -/* Legacy interrupt pad configuration */ -#define PAD_INT(pin, pull, trigger, action) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) - -/* SCI pad configuration */ -#define PAD_SCI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ - PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) - -/* SMI pad configuration */ -#define PAD_SMI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ - PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) - -/* WAKE pad configuration */ -#define PAD_WAKE(pin, pull, trigger, type) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) - -/* pin debounce configuration */ -#define PAD_DEBOUNCE(pin, pull, type, time) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) - -/* No-connect pad - configured as input with PULL_DOWN */ -#define PAD_NC(pin) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) - typedef uint32_t gpio_t; /* diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h new file mode 100644 index 0000000..f0c6f66 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_GPIO_DEFS_H +#define AMD_BLOCK_GPIO_DEFS_H + +#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASK_STS_EN BIT(28) +#define GPIO_INTERRUPT_EN BIT(30) +#define GPIO_WAKE_EN BIT(31) + +#define GPIO_WAKE_STAT_0 0x2F0 +#define GPIO_WAKE_STAT_1 0x2F4 + +#define GPIO_PIN_IN (1 << 0) /* for byte access */ +#define GPIO_PIN_OUT (1 << 6) /* for byte access */ + +/* Pad trigger type - Level or Edge */ +#define GPIO_TRIGGER_EDGE (0 << 8) +#define GPIO_TRIGGER_LEVEL (1 << 8) +#define GPIO_TRIGGER_MASK (1 << 8) + +/* + * Pad polarity: + * Level trigger - High or Low + * Edge trigger - High (Rising), Low (Falling), Both + */ +#define GPIO_ACTIVE_HIGH (0 << 9) +#define GPIO_ACTIVE_LOW (1 << 9) +#define GPIO_ACTIVE_BOTH (2 << 9) +#define GPIO_ACTIVE_MASK (3 << 9) + +/* + * Pad trigger and polarity configuration. + * This determines the filtering applied on the input signal at the pad. + */ +#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) +#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) + +#define GPIO_INT_ENABLE_STATUS (1 << 11) +#define GPIO_INT_ENABLE_DELIVERY (1 << 12) +#define GPIO_INT_ENABLE_STATUS_DELIVERY \ + (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) +#define GPIO_INT_ENABLE_MASK (3 << 11) + +#define GPIO_S0I3_WAKE_EN (1 << 13) +#define GPIO_S3_WAKE_EN (1 << 14) +#define GPIO_S4_S5_WAKE_EN (1 << 15) + +#define GPIO_PIN_STS (1 << 16) +#define GPIO_8KPULLUP_SELECT (1 << 19) +#define GPIO_PULLUP_ENABLE (1 << 20) +#define GPIO_PULLDOWN_ENABLE (1 << 21) +#define GPIO_PULL_MASK (7 << 19) + +#define GPIO_INPUT_SHIFT 16 +#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) + +#define GPIO_OUTPUT_SHIFT 22 +#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) +#define GPIO_OUTPUT_ENABLE (1 << 23) +#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) + +#define GPIO_INT_STATUS (1 << 28) +#define GPIO_WAKE_STATUS (1 << 29) +#define GPIO_STATUS_MASK (3 << 28) + +#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) +#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE + +#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) +#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE +#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE +#define GPIO_PULL_PULL_NONE 0 + +#define AMD_GPIO_MUX_MASK 0x03 + +/* + * Flags used for GPIO configuration. These provide additional information that does not go + * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. + */ +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) +#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) +#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) +#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) +#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) +#define GPIO_FLAG_SCI (1 << 2) +#define GPIO_FLAG_SMI (1 << 3) + +/* Trigger configuration for GPIO SCI/SMI events. */ +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ + GPIO_FLAG_EVENT_ACTIVE_HIGH) +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ + GPIO_FLAG_EVENT_ACTIVE_LOW) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ + GPIO_FLAG_EVENT_ACTIVE_HIGH) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ + GPIO_FLAG_EVENT_ACTIVE_LOW) +#define DEB_GLITCH_SHIFT 5 +#define DEB_GLITCH_LOW 1 +#define DEB_GLITCH_HIGH 2 +#define DEB_GLITCH_NONE 3 +#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) +#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) +#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) + +#define GPIO_TIMEBASE_61uS 0 +#define GPIO_TIMEBASE_183uS (1 << 4) +#define GPIO_TIMEBASE_15560uS (1 << 7) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ + GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) +#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) +#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) + +#define GPIO_DEB_MASK 0xff + +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_MASK (7 << 13) + +/* + * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` + * Bits that are preserved/untouched: + * - Reserved bits + * - Drive strength bits + * - Read only bits + */ +#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ + GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ + GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) + +/* + * Several macros are available to declare programming of GPIO pins. The defined macros and + * their parameters are: + * PAD_NF Define native alternate function for the pin. + * pin the pin to be programmed + * function the native function + * pull pull up, pull down or no pull + * PAD_GPI The pin is a GPIO input + * pin the pin to be programmed + * pull pull up, pull down or no pull + * PAD_GPO The pin is a GPIO output + * pin the pin to be programmed + * direction high or low + * PAD_INT The pin is regular interrupt that works while booting + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * action STATUS, DELIVER, STATUS_DELIVER + * PAD_SCI The pin is a SCI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH + * PAD_SMI The pin is a SMI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * event trigger LEVEL_LOW, LEVEL_HIGH + * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) + * PAD_DEBOUNCE The input or interrupt will be debounced + * pin the pin to be programmed + * pull pull up, pull down or no pull + * debounce_type preserve low glitch, preserve high glitch, no glitch + * debounce_time the debounce time + */ + +#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ + { \ + .gpio = __pin, \ + .function = __function, \ + .control = __control, \ + .flags = __flags, \ + } + +#define PAD_CFG_STRUCT(__pin, __function, __control) \ + PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) + +#define PAD_PULL(__pull) GPIO_PULL_ ## __pull +#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir +#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig +#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action +#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig +#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake +#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb + +/* Native function pad configuration */ +#define PAD_NF(pin, func, pull) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) + +/* General purpose input pad configuration */ +#define PAD_GPI(pin, pull) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) + +/* General purpose output pad configuration */ +#define PAD_GPO(pin, direction) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) + +/* Legacy interrupt pad configuration */ +#define PAD_INT(pin, pull, trigger, action) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) + +/* SCI pad configuration */ +#define PAD_SCI(pin, pull, trigger) \ + PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ + PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) + +/* SMI pad configuration */ +#define PAD_SMI(pin, pull, trigger) \ + PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ + PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) + +/* WAKE pad configuration */ +#define PAD_WAKE(pin, pull, trigger, type) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) + +/* pin debounce configuration */ +#define PAD_DEBOUNCE(pin, pull, type, time) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) + +/* No-connect pad - configured as input with PULL_DOWN */ +#define PAD_NC(pin) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) + +#endif /* AMD_BLOCK_GPIO_DEFS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a779eae228f621e77610889205853de2fb179a Gerrit-Change-Number: 49216 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2021