Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49245 )
Change subject: soc/amd/cezzane: Add a minimal chipset tree ......................................................................
soc/amd/cezzane: Add a minimal chipset tree
This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex
This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc().
Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49245 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Jason Glenesk jason.glenesk@gmail.com --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/chipset.cb 2 files changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 22d0c3a..afee1ef 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -26,6 +26,10 @@ select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
+config CHIPSET_DEVICETREE + string + default "soc/amd/cezanne/chipset.cb" + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb new file mode 100644 index 0000000..49bd0c8 --- /dev/null +++ b/src/soc/amd/cezanne/chipset.cb @@ -0,0 +1,5 @@ +chip soc/amd/cezanne + device domain 0 on + device pci 00.0 alias gnb on end + end +end