coreboot-gerrit January 2021

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Change in coreboot[master]: cpu/mp_init: Fix microcode lock
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49304 ) Change subject: cpu/mp_init: Fix microcode lock ...................................................................... cpu/mp_init: Fix microcode lock Fix C code to match comment and assembly implementation. Tested on Prodrive hermes: The microcode spinlock is no longer used. Change-Id: I21441299f538783551d4d5ba2b2e7567e152d718 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49304/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 01c1d5f..c691c48 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -344,9 +344,9 @@ sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) - sp->microcode_lock = 0; - else sp->microcode_lock = ~0; + else + sp->microcode_lock = 0; sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/49304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21441299f538783551d4d5ba2b2e7567e152d718 Gerrit-Change-Number: 49304 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mpinit: Serialize microcode updates for HT threads
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49303 ) Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... cpu/x86/mpinit: Serialize microcode updates for HT threads This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affect by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per code on Hyper-Threading enabled CPUs. As complex code would be necessary determining the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2, only every use a global spinlock. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is neglectable. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/x86/sipi_vector.S M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c 6 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/49303/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index b56d106..ff6cbec 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -33,7 +33,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index db43353..88e42a5 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -251,7 +251,7 @@ { microcode_patch = intel_microcode_find(); *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 2afbfee..b08a86f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -497,7 +497,7 @@ { microcode_patch = intel_microcode_find(); *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 02ad0d3..0a963f7 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -102,6 +102,13 @@ /* Save CPU number. */ mov %ecx, %esi + /* + * The following code only need to run on Intel platforms and thus the caller + * doesn't provide a microcode_ptr if not on Intel. + * On Intel platforms which update microcode using FIT the version check will + * also skip the microcode update. + */ + /* Determine if one should check microcode versions. */ mov microcode_ptr, %edi test %edi, %edi @@ -116,6 +123,15 @@ test %edx, %edx jnz microcode_done + /* + * Intel SDM and various BWGs specify to use a semaphore to update microcode + * on one thread per code on Hyper-Threading enabled CPUs. As complex code would be + * necessary determining the core #ID, initializing and picking the right semaphore + * out of CONFIG_MAX_CPUS / 2, only every use a global spinlock. + * Assuming that only pre-FIT platforms with Hyper-Threading enabled and at + * most 8 threads will ever run into this condition, the boot delay is neglectable. + */ + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 2029017..e624240 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -149,7 +149,7 @@ const struct pattrs *pattrs = pattrs_get(); *microcode = pattrs->microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 04bf108..0c6f463 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -152,7 +152,7 @@ const struct pattrs *pattrs = pattrs_get(); *microcode = pattrs->microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Gerrit-Change-Number: 49303 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voema: Add camera ACPI configuration
by David Wu (Code Review) 11 Jan '21

11 Jan '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49302 ) Change subject: mb/google/volteer/var/voema: Add camera ACPI configuration ...................................................................... mb/google/volteer/var/voema: Add camera ACPI configuration Add camera ACPI configuration for Voema BUG=b:169551066 TEST=Build and boot Voema. Start camera app and able to capture images. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e --- M src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl 1 file changed, 370 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49302/1 diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl index 418f2e0..82d414e 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/voema/include/variant/acpi/mipi_camera.asl @@ -1,3 +1,372 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/mipi_camera.asl> +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 5 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 1 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C2.CAM1, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C3) +{ + /* Reference counter to track power control by RCAM and VCM */ + Name (REFC, 0) + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, 0) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + /* Enable IMG_CLK */ + MCON(3,1) /* Clock 3, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_F15) + + /* Pull SNRPWR_EN high */ + STXS(GPP_H14) + + If (REFC == 0) + { + /* Pull PWREN high */ + STXS(GPP_H20) + } + Sleep(2) /* reset pulse width */ + + REFC++ + + /* Pull RST high */ + STXS(GPP_F15) + + Sleep(1) /* t2 */ + + STA = 1 + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(3) /* Clock 3 */ + + /* Pull RST low */ + CTXS(GPP_F15) + + If (REFC == 1) + { + /* Pull PWREN low */ + CTXS(GPP_H20) + } + REFC-- + + /* Pull SNRPWR_EN low */ + CTXS(GPP_H14) + + STA = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + PowerResource (VCPR, 0x00, 0x0000) + { + Name (STA, 0) + Method (_ON, 0, Serialized) /* VCPR_ON_: VCM Power On */ + { + If (REFC == 0) + { + /* Pull PWREN high */ + STXS(GPP_H20) + } + REFC++ + STA = 1 + } + Method (_OFF, 0, Serialized) /* VCPR_OFF: VCM Power Off */ + { + If (REFC == 1) + { + /* Pull PWREN low */ + CTXS(GPP_H20) + } + REFC-- + STA = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + +} + +Scope (\_SB.PCI0.I2C2) +{ + Name (STA, Zero) + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If (STA == 0) + { + /* Enable IMG_CLK */ + MCON(2,1) /* Clock 2, 19.2MHz */ + + /* Pull RST low */ + CTXS(GPP_D4) + + /* Pull SNRPWR_EN high */ + STXS(GPP_D18) + + /* Pull PWREN high */ + STXS(GPP_D17) + Sleep(10) /* t9 */ + + /* Pull RST high */ + STXS(GPP_D4) + Sleep(1) /* t2 */ + + STA = 1 + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If (STA == 1) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(2) /* Clock 2 */ + + /* Pull RST low */ + CTXS(GPP_D4) + + /* Pull PWREN low */ + CTXS(GPP_D17) + + /* Pull SNRPWR_EN low */ + CTXS(GPP_D18) + + STA = 0 + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "INT3474") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 2740 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "i2c-allow-low-power-probe", + 0x01 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x15752A00 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/49302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e Gerrit-Change-Number: 49302 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Benjamin Doron. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49140/comment/5f12db38_63aefde5 PS3, Line 11: > Hmm. Not sure what I want to see, but it's probably not "CPU did not enter SLP_S0!!! (S0ix cnt=0). […] Righht, Slp_S0 is not a requirement, when it's not connected. Does the cpu residency counter increase? -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 10:39:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add CSE Lite SKU support to Copano
by Zhuohao Lee (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Tim Wawrzynczak, Hao Chou. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49290 ) Change subject: mb/google/volteer: Add CSE Lite SKU support to Copano ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I875f6b32c4053ef6d23ad7606cd35a129a78c306 Gerrit-Change-Number: 49290 Gerrit-PatchSet: 1 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 10:34:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`
by Arthur Heymans (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49282 ) Change subject: soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Gerrit-Change-Number: 49282 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 10:01:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fix toctree and remove dead links
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49292 ) Change subject: Documentation: Fix toctree and remove dead links ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Gerrit-Change-Number: 49292 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 09:57:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PCH ID 0x5182
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49301 ) Change subject: soc/intel/alderlake: Add PCH ID 0x5182 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Gerrit-Change-Number: 49301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 09:55:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PCH ID 0x5182
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, EricR Lai. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49301 ) Change subject: soc/intel/alderlake: Add PCH ID 0x5182 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Gerrit-Change-Number: 49301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 09:43:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: Add Discrete sdparam configs
by Hung-Te Lin (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Xi Chen, Martin Roth. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49298 ) Change subject: soc/mediatek/mt8192: Add Discrete sdparam configs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: 1. Is there an issue already created for tracking these numbers? Please including that in BUG= 2. Please check with alvishsu@ for the real mapping codes. We may want to do grouping. -- To view, visit https://review.coreboot.org/c/coreboot/+/49298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie97ae6d980dbd53b9b1a912252dc125307f13ff8 Gerrit-Change-Number: 49298 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 09:37:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2021