Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Benjamin Doron, Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph, Lance Zhao, Nico Huber, Martin Roth, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/*: drop UART pad configuration from common code
......................................................................
soc/intel/*: drop UART pad configuration from common code
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.
Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.
Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/uart.c
M src/soc/intel/apollolake/uart.c
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/uart.c
M src/soc/intel/common/block/include/intelblocks/uart.h
M src/soc/intel/common/block/uart/Kconfig
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/elkhartlake/uart.c
M src/soc/intel/icelake/uart.c
M src/soc/intel/jasperlake/uart.c
M src/soc/intel/skylake/uart.c
M src/soc/intel/tigerlake/uart.c
12 files changed, 46 insertions(+), 334 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48829/9
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49303 )
Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads
......................................................................
Patch Set 1:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49303/comment/8ee059e4_e80f1b98
PS1, Line 10: affect
> affect*ed*
Done
https://review.coreboot.org/c/coreboot/+/49303/comment/e18ae141_b70dfb6e
PS1, Line 17: code
> co*r*e
Done
https://review.coreboot.org/c/coreboot/+/49303/comment/0f1ed5d1_ddaf832c
PS1, Line 18: determining
> to determine
Done
https://review.coreboot.org/c/coreboot/+/49303/comment/4709fc1d_8c2a153c
PS1, Line 19: initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2,
: only every use a global spinlock.
> I'm afraid I don't understand what this part tries to say.
Ack
https://review.coreboot.org/c/coreboot/+/49303/comment/ab41db41_7967935d
PS1, Line 23: neglectable
> negligible
Done
Patchset:
PS1:
Rephrased the text a bit.
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Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49303
to look at the new patch set (#2).
Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads
......................................................................
cpu/x86/mpinit: Serialize microcode updates for HT threads
This change affects Intel CPUs only. As most platforms are doing
uCode update using FIT, they aren't affected by this code either.
Update microcode in MP-init using a single spinlock when running on
a Hyper-Threading enabled CPU on pre FIT platforms.
This will slow down the MP-init boot flow.
Intel SDM and various BWGs specify to use a semaphore to update
microcode on one thread per core on Hyper-Threading enabled CPUs.
Due to this complex code would be necessary to determining the core #ID,
initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2.
Instead use the existing global spinlock already present in MPinit code.
Assuming that only pre-FIT platforms with Hyper-Threading enabled and at
most 8 threads will ever run into this condition, the boot delay is
negligible.
This change is a counterproposal to the previous published patch series
being much more unsophisticated.
Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/cpu/x86/sipi_vector.S
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/braswell/cpu.c
6 files changed, 22 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/49303/2
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49303 )
Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49303/comment/8cb77800_42c8143c
PS1, Line 13: a Hyper-Threading enabled CPU on pre FIT platforms.
> What about model_106cx (Diamondville, Pineview)? These CPUs can have HyperThreading.
model_106cx uses model_1067x mpinit code.
File src/cpu/intel/model_1067x/mp_init.c:
https://review.coreboot.org/c/coreboot/+/49303/comment/2cae2268_1a64dbc8
PS1, Line 36: *parallel = !intel_ht_supported();
> Hmmm, but 1067x doesn't support HT. […]
Used by model_106cx.
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49296 )
Change subject: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/zork/variants/baseboard/helpers.c:
https://review.coreboot.org/c/coreboot/+/49296/comment/fd48866a_d03c1277
PS5, Line 89: return !!extract_field(FW_CONFIG_MASK_SAR, FW_CONFIG_SHIFT_SAR);
we don't want bool here. !! not needed.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49303 )
Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49303/comment/cbff6d53_d0cd2065
PS1, Line 13: a Hyper-Threading enabled CPU on pre FIT platforms.
What about model_106cx (Diamondville, Pineview)? These CPUs can have HyperThreading.
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