coreboot-gerrit January 2021

coreboot-gerrit@coreboot.org

1 participants
6507 discussions

Change in coreboot[master]: util/board_status/board_status.sh: select the right gnu make binary
by Idwer Vollering (Code Review) 11 Jan '21

11 Jan '21

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49306 ) Change subject: util/board_status/board_status.sh: select the right gnu make binary ...................................................................... util/board_status/board_status.sh: select the right gnu make binary Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: I4523b1b235064f89c01530b47c9cb4c3c11c9761 --- M util/board_status/board_status.sh 1 file changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/49306/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 31c3e7c..ab4a310 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -26,6 +26,13 @@ # Used if nvramtool is not in default $PATH, e.g. not installed or when using `sudo` NVRAMTOOL_PATH="" +case $(uname) in +FreeBSD) + MAKE=gmake;; +*) + MAKE=make;; +esac + # test a command # # $1: 0 ($LOCAL) to run command locally, @@ -302,7 +309,7 @@ exit $EXIT_FAILURE fi else - make -C util/cbfstool/ + $MAKE -C util/cbfstool/ do_clean_cbfstool=1 fi fi @@ -313,7 +320,7 @@ $cbfstool_cmd "$COREBOOT_IMAGE" extract -n config -f "${tmpdir}/config.txt" >/dev/null 2>&1 mv "${tmpdir}/config.txt" "${tmpdir}/config.short.txt" cp "${tmpdir}/config.short.txt" "${tmpcfg}" -yes "" | make "DOTCONFIG=${tmpcfg}" oldconfig 2>/dev/null >/dev/null +yes "" | $MAKE "DOTCONFIG=${tmpcfg}" oldconfig 2>/dev/null >/dev/null mv "${tmpcfg}" "${tmpdir}/config.txt" rm -f "${tmpcfg}.old" $cbfstool_cmd "$COREBOOT_IMAGE" print > "${tmpdir}/cbfs.txt" @@ -329,7 +336,7 @@ md5sum -b "$COREBOOT_IMAGE" > "${tmpdir}/rom_checksum.txt" if test $do_clean_cbfstool -eq 1; then - make -C util/cbfstool clean + $MAKE -C util/cbfstool clean fi # Obtain board and revision info to form the directory structure: -- To view, visit https://review.coreboot.org/c/coreboot/+/49306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4523b1b235064f89c01530b47c9cb4c3c11c9761 Gerrit-Change-Number: 49306 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/mpinit: Serialize microcode updates for HT threads
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49303 ) Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49303/comment/1983f657_6f84e193 PS1, Line 13: a Hyper-Threading enabled CPU on pre FIT platforms. > model_106cx uses model_1067x mpinit code. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/49303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Gerrit-Change-Number: 49303 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 12:41:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by build bot (Jenkins) (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Kyösti Mälkki, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 ) Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/uart/uart.c: https://review.coreboot.org/c/coreboot/+/48829/comment/8384a8cd_6f370ee2 PS9, Line 59: if (CONFIG_UART_FOR_CONSOLE > uart_max_index) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 12:34:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/mpinit: Serialize microcode updates for HT threads
by Arthur Heymans (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Patrick Rudolph, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49303 ) Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... Patch Set 2: (1 comment) File src/cpu/intel/model_1067x/mp_init.c: https://review.coreboot.org/c/coreboot/+/49303/comment/d5717397_3e6fa677 PS1, Line 36: *parallel = !intel_ht_supported(); > Used by model_106cx. Also for model_f4x (and was reported to work with model_f6x). -- To view, visit https://review.coreboot.org/c/coreboot/+/49303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Gerrit-Change-Number: 49303 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 12:34:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: make uart_max_index's value reflect what its name pretends
by Michael Niewöhner (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Kyösti Mälkki, Karthik Ramasubramanian. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49305 ) Change subject: soc/intel: make uart_max_index's value reflect what its name pretends ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/49305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Gerrit-Change-Number: 49305 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 12:29:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`
by Furquan Shaikh (Code Review) 11 Jan '21

11 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49212 ) Change subject: soc/intel/uart: Drop SoC callback `soc_uart_console_to_device` ...................................................................... soc/intel/uart: Drop SoC callback `soc_uart_console_to_device` This change renames `struct uart_gpio_pad_config` to `struct uart_controller_config` and adds a new parameter devfn (which expects devfn for the UART controller corresponding to the index in PCI_DEVFN() format). This gets rid of the SoC callback to get `struct device` pointer to the UART controller device. Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/uart.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c M src/soc/intel/elkhartlake/uart.c M src/soc/intel/icelake/uart.c M src/soc/intel/jasperlake/uart.c M src/soc/intel/skylake/uart.c M src/soc/intel/tigerlake/uart.c 10 files changed, 49 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/49212/1 diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index a3bdc4a..46f6220 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -17,9 +17,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ @@ -27,6 +28,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -34,6 +36,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -41,23 +44,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 4e35ee5..28ad71a 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -11,11 +11,11 @@ #include <soc/gpio.h> #include <soc/pci_devs.h> -/* UART pad configuration. Support RXD and TXD for now. */ -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { #if CONFIG(SOC_INTEL_GEMINILAKE) { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ @@ -26,6 +26,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ @@ -36,6 +37,7 @@ #else { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */ @@ -43,6 +45,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ @@ -50,6 +53,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ @@ -58,25 +62,4 @@ #endif }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - case 3: - return pcidev_path_on_root(PCH_DEVFN_UART3); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index cc0e3a8..c0d0e49 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -11,9 +11,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index fd65f4c..4f7ac57 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -10,8 +10,10 @@ #define MAX_GPIO_PAD_PER_UART 2 -struct uart_gpio_pad_config { +struct uart_controller_config { int console_index; + /* devfn in PCI_DEVFN() format */ + int devfn; struct pad_config gpios[MAX_GPIO_PAD_PER_UART]; }; @@ -55,21 +57,4 @@ */ const struct device *uart_get_device(void); -/**************************** SoC callbacks ***********************************/ - -/* - * SoC should implement soc_uart_console_to_device() function to - * get UART debug controller device structure based on console number - * Caller needs to check proper UART console index supported by SoC. - * If wrong UART console index is passed to function, it'll return NULL. - * - * Input: - * UART console index selected in config - * - * Returns: - * Pointer to device structure = If device has a UART debug controller. - * NULL = otherwise - */ -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console); - #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 1e205ef..1cfdb67 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -20,7 +20,7 @@ #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) #define UART_CONSOLE_INVALID_INDEX 0xFF -extern const struct uart_gpio_pad_config uart_gpio_pads[]; +extern const struct uart_controller_config uart_ctrlr_config[]; extern const int uart_max_index; static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) @@ -50,7 +50,7 @@ int index; for (index = 0; index < uart_max_index; index++) { - if (uart_gpio_pads[index].console_index == + if (uart_ctrlr_config[index].console_index == CONFIG_UART_FOR_CONSOLE) return index; } @@ -88,7 +88,7 @@ int console_index = uart_get_valid_index(); if (console_index != UART_CONSOLE_INVALID_INDEX) - return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE); + return pcidev_path_on_root(uart_ctrlr_config[index].devfn); else return NULL; } @@ -123,7 +123,7 @@ int index = uart_get_valid_index(); if (index != UART_CONSOLE_INVALID_INDEX) - gpio_configure_pads(uart_gpio_pads[index].gpios, + gpio_configure_pads(uart_ctrlr_config[index].gpios, MAX_GPIO_PAD_PER_UART); } diff --git a/src/soc/intel/elkhartlake/uart.c b/src/soc/intel/elkhartlake/uart.c index cc0e3a8..c0d0e49 100644 --- a/src/soc/intel/elkhartlake/uart.c +++ b/src/soc/intel/elkhartlake/uart.c @@ -11,9 +11,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index cc0e3a8..c0d0e49 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -11,9 +11,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c index cc0e3a8..c0d0e49 100644 --- a/src/soc/intel/jasperlake/uart.c +++ b/src/soc/intel/jasperlake/uart.c @@ -11,9 +11,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 28ede6f..9e2dcb3 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -10,10 +10,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -/* UART pad configuration. Support RXD and TXD for now. */ -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +21,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +29,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +37,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c index 08bfa54..5ae54d5 100644 --- a/src/soc/intel/tigerlake/uart.c +++ b/src/soc/intel/tigerlake/uart.c @@ -17,9 +17,10 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -27,6 +28,7 @@ }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -34,6 +36,7 @@ }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -41,23 +44,4 @@ } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/49212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5 Gerrit-Change-Number: 49212 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: soc/intel/apl: move UART pad config to boards
by build bot (Jenkins) (Code Review) 11 Jan '21

11 Jan '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48800 ) Change subject: soc/intel/apl: move UART pad config to boards ...................................................................... Patch Set 13: (4 comments) File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/48800/comment/de64f0f0_296e98af PS13, Line 297: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ line over 96 characters https://review.coreboot.org/c/coreboot/+/48800/comment/8c6aed85_aa40709f PS13, Line 298: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ line over 96 characters File src/mainboard/intel/glkrvp/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/48800/comment/ec7466a2_090a04fb PS13, Line 240: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_UART2_RXD */ line over 96 characters https://review.coreboot.org/c/coreboot/+/48800/comment/93cc2395_4371bdda PS13, Line 241: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/* LPSS_UART2_TXD */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/48800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a0375a0a27ddaa758498473e37af38821fdd52 Gerrit-Change-Number: 48800 Gerrit-PatchSet: 13 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 11 Jan 2021 12:28:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by Michael Niewöhner (Code Review) 11 Jan '21

11 Jan '21

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Benjamin Doron, Paul Menzel, Subrata Banik, Andrey Petrov, Patrick Rudolph, Lance Zhao, Nico Huber, Martin Roth, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48829 to look at the new patch set (#9). Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... soc/intel/*: drop UART pad configuration from common code UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Since all boards do pad setup on their own now, finally drop the pad configuration from SoC common code. Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/uart.c M src/soc/intel/apollolake/uart.c M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Kconfig M src/soc/intel/common/block/uart/uart.c M src/soc/intel/elkhartlake/uart.c M src/soc/intel/icelake/uart.c M src/soc/intel/jasperlake/uart.c M src/soc/intel/skylake/uart.c M src/soc/intel/tigerlake/uart.c 12 files changed, 46 insertions(+), 334 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/48829/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/x86/mpinit: Serialize microcode updates for HT threads
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49303 ) Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49303/comment/8ee059e4_e80f1b98 PS1, Line 10: affect > affect*ed* Done https://review.coreboot.org/c/coreboot/+/49303/comment/e18ae141_b70dfb6e PS1, Line 17: code > co*r*e Done https://review.coreboot.org/c/coreboot/+/49303/comment/0f1ed5d1_ddaf832c PS1, Line 18: determining > to determine Done https://review.coreboot.org/c/coreboot/+/49303/comment/4709fc1d_8c2a153c PS1, Line 19: initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2, : only every use a global spinlock. > I'm afraid I don't understand what this part tries to say. Ack https://review.coreboot.org/c/coreboot/+/49303/comment/ab41db41_7967935d PS1, Line 23: neglectable > negligible Done Patchset: PS1: Rephrased the text a bit. -- To view, visit https://review.coreboot.org/c/coreboot/+/49303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Gerrit-Change-Number: 49303 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 12:24:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/mpinit: Serialize microcode updates for HT threads
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49303 to look at the new patch set (#2). Change subject: cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... cpu/x86/mpinit: Serialize microcode updates for HT threads This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affected by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per core on Hyper-Threading enabled CPUs. Due to this complex code would be necessary to determining the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2. Instead use the existing global spinlock already present in MPinit code. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is negligible. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/x86/sipi_vector.S M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c 6 files changed, 22 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/49303/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Gerrit-Change-Number: 49303 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2021