coreboot-gerrit January 2021

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Change in coreboot[master]: soc/intel/alderlake: Add PCH ID 0x5182
by Subrata Banik (Code Review) 11 Jan '21

11 Jan '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49301 ) Change subject: soc/intel/alderlake: Add PCH ID 0x5182 ...................................................................... soc/intel/alderlake: Add PCH ID 0x5182 TEST=Able to build and boot ADLRVP. Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/lpc/lpc.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/49301/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8ac29c5..0b78c9f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2959,6 +2959,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32 0x5181 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33 0x5182 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index f0d8f2b..8cc81c1 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -79,6 +79,7 @@ { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" }, }; static struct { diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 369b6b1..af8331e 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -306,6 +306,7 @@ PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/49301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Gerrit-Change-Number: 49301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3
by shkim (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: SH Kim, Karthik Ramasubramanian. Hello Patrick Georgi, SH Kim, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49300 to look at the new patch set (#2). Change subject: mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3 ...................................................................... mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3 This change disables unused PCIE RP8 and CLKSRC3. Without this change sasuke cannot enter into s0ix properly. BUG=b:176862270 TEST=Built and verified entering s0ix Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/sasuke/overridetree.cb 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49300/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Gerrit-Change-Number: 49300 Gerrit-PatchSet: 2 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3
by shkim (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: SH Kim. Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49300 to review the following change. Change subject: mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3 ...................................................................... mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3 This change disables unused PCIE RP8 and CLKSRC3. Without this sasuke cannot enter into s0ix properly. BUG=b:176862270 TEST=Built and verified entering s0ix Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/sasuke/overridetree.cb 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49300/1 diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index d3b0dd7..987e331 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/jasperlake + # Disable PCIe Root Port 8 (index 7) + register "PcieRpEnable[7]" = "0" + # Disable PCIe Clock Source 4 (index 3) + register "PcieClkSrcUsage[3]" = "0xff" # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera @@ -73,7 +77,7 @@ end end # I2C 0 device pci 15.2 on end - device pci 1c.7 on end + device pci 1c.7 off end # PCI Express Root Port 8 device pci 19.0 on chip drivers/i2c/da7219 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" -- To view, visit https://review.coreboot.org/c/coreboot/+/49300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Gerrit-Change-Number: 49300 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Add Discrete sdparam configs
by Xi Chen (Code Review) 11 Jan '21

11 Jan '21

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49298 ) Change subject: soc/mediatek/mt8192: Add Discrete sdparam configs ...................................................................... soc/mediatek/mt8192: Add Discrete sdparam configs - H9HCNNNCPMMLXR-4GB - K4UBE3D4AA-MGCR-4GB - MT53E1G32D2-4GB - H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB - K4UCE3Q4AA-MGCR-BYTE-MODE-8GB - MT53E2G32D4-8GB Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: Ie97ae6d980dbd53b9b1a912252dc125307f13ff8 --- M src/mainboard/google/asurada/sdram_configs.c M src/mainboard/google/asurada/sdram_params/Makefile.inc A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UCE3Q4AA-MGCR-BYTE-MODE-8GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E1G32D2-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E2G32D4-8GB.c M src/soc/mediatek/mt8192/include/soc/dramc_param.h 9 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/49298/1 diff --git a/src/mainboard/google/asurada/sdram_configs.c b/src/mainboard/google/asurada/sdram_configs.c index acefada..ad11763 100644 --- a/src/mainboard/google/asurada/sdram_configs.c +++ b/src/mainboard/google/asurada/sdram_configs.c @@ -10,6 +10,12 @@ [1] = "sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB", [2] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", [3] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + [4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-4GB", + [5] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [6] = "sdram-lpddr4x-MT53E1G32D2-4GB", + [7] = "sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB", + [8] = "sdram-lpddr4x-K4UCE3Q4AA-MGCR-BYTE-MODE-8GB", + [9] = "sdram-lpddr4x-MT53E2G32D4-8GB", }; static struct sdram_info params; diff --git a/src/mainboard/google/asurada/sdram_params/Makefile.inc b/src/mainboard/google/asurada/sdram_params/Makefile.inc index 7a591f4..8d52290 100644 --- a/src/mainboard/google/asurada/sdram_params/Makefile.inc +++ b/src/mainboard/google/asurada/sdram_params/Makefile.inc @@ -3,6 +3,12 @@ sdram-params += sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB +sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-4GB +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB +sdram-params += sdram-lpddr4x-MT53E1G32D2-4GB +sdram-params += sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB +sdram-params += sdram-lpddr4x-K4UCE3Q4AA-MGCR-BYTE-MODE-8GB +sdram-params += sdram-lpddr4x-MT53E2G32D4-8GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-4GB.c new file mode 100644 index 0000000..5735df5 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB.c new file mode 100644 index 0000000..51e8a6f --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-BYTE-MODE-8GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c new file mode 100644 index 0000000..5735df5 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UCE3Q4AA-MGCR-BYTE-MODE-8GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UCE3Q4AA-MGCR-BYTE-MODE-8GB.c new file mode 100644 index 0000000..51e8a6f --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-K4UCE3Q4AA-MGCR-BYTE-MODE-8GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E1G32D2-4GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E1G32D2-4GB.c new file mode 100644 index 0000000..aef8512 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E1G32D2-4GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4_0, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E2G32D4-8GB.c b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E2G32D4-8GB.c new file mode 100644 index 0000000..3d12588 --- /dev/null +++ b/src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT53E2G32D4-8GB.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_info params = { + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, + .ddr_type = DDR_TYPE_DISCRETE, +}; diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h index 30ac4d4..0b67bed 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -43,9 +43,10 @@ enum DRAMC_PARAM_GEOMETRY_TYPE { DDR_TYPE_2CH_2RK_4GB_2_2, DDR_TYPE_2CH_2RK_6GB_3_3, - DDR_TYPE_2CH_2RK_8GB_4_4, + DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, DDR_TYPE_2CH_1RK_4GB_4_0, DDR_TYPE_2CH_2RK_6GB_2_4, + DDR_TYPE_2CH_2RK_8GB_4_4, }; enum DRAM_PARAM_VOLTAGE_TYPE { -- To view, visit https://review.coreboot.org/c/coreboot/+/49298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie97ae6d980dbd53b9b1a912252dc125307f13ff8 Gerrit-Change-Number: 49298 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz
by Frank Wu (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Frank Wu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49296 to look at the new patch set (#5). Change subject: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz ...................................................................... mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/49296/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: SAR config
by Frank Wu (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Frank Wu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49296 to look at the new patch set (#4). Change subject: mb/google/zork/var/vilboz: SAR config ...................................................................... mb/google/zork/var/vilboz: SAR config BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/49296/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: SAR config
by build bot (Jenkins) (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Frank Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49296 ) Change subject: mb/google/zork/var/vilboz: SAR config ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/zork/variants/vilboz/variant.c: https://review.coreboot.org/c/coreboot/+/49296/comment/0787d714_059bbccd PS3, Line 67: switch (sar_config) { switch and case should be at the same indent -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 09:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/vilboz: SAR config
by Frank Wu (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Frank Wu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49296 to look at the new patch set (#3). Change subject: mb/google/zork/var/vilboz: SAR config ...................................................................... mb/google/zork/var/vilboz: SAR config BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/49296/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Add CSE Lite SKU support to Copano
by Hao Chou (Code Review) 11 Jan '21

11 Jan '21

Hao Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49290 ) Change subject: mb/google/volteer: Add CSE Lite SKU support to Copano ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I875f6b32c4053ef6d23ad7606cd35a129a78c306 Gerrit-Change-Number: 49290 Gerrit-PatchSet: 1 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 09:02:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/vilboz: SAR config
by Frank Wu (Code Review) 11 Jan '21

11 Jan '21

Frank Wu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/49296 ) Change subject: mb/google/zork/var/vilboz: SAR config ...................................................................... mb/google/zork/var/vilboz: SAR config BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/49296/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2021