Attention is currently required from: SH Kim. Hello SH Kim,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/49300
to review the following change.
Change subject: mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3 ......................................................................
mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3
This change disables unused PCIE RP8 and CLKSRC3. Without this sasuke cannot enter into s0ix properly.
BUG=b:176862270 TEST=Built and verified entering s0ix
Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Signed-off-by: Seunghwan Kim sh_.kim@samsung.corp-partner.google.com --- M src/mainboard/google/dedede/variants/sasuke/overridetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/49300/1
diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index d3b0dd7..987e331 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/jasperlake + # Disable PCIe Root Port 8 (index 7) + register "PcieRpEnable[7]" = "0" + # Disable PCIe Clock Source 4 (index 3) + register "PcieClkSrcUsage[3]" = "0xff"
# USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera @@ -73,7 +77,7 @@ end end # I2C 0 device pci 15.2 on end - device pci 1c.7 on end + device pci 1c.7 off end # PCI Express Root Port 8 device pci 19.0 on chip drivers/i2c/da7219 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"