coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/volteer: Set FORCE_PWR low at boot time
by John Zhao (Code Review) 11 Jan '21

11 Jan '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48649 ) Change subject: mb/google/volteer: Set FORCE_PWR low at boot time ...................................................................... mb/google/volteer: Set FORCE_PWR low at boot time While FORCE_PWR is set high, it prevents retimer from entering low power state. S0ix failure occurs while USB4 Gatkex is connected on Port-0. This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be toggled by kernel through DSM method while updating retimer firmware. BUG=b:174166586 TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 --- M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/todor/gpio.c M src/mainboard/google/volteer/variants/voema/gpio.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48649/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 922d3d1..2030f31 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -308,7 +308,7 @@ /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H11 : SRCCLKREQ5# ==> NC */ PAD_NC(GPP_H11, NONE), /* H12 : M2_SKT2_CFG0 ==> NONE */ diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index d5498d0..79722d8 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -139,7 +139,7 @@ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c index 40d25a5..0391964 100644 --- a/src/mainboard/google/volteer/variants/todor/gpio.c +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -147,7 +147,7 @@ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c index d905dae..5bf6fad 100644 --- a/src/mainboard/google/volteer/variants/voema/gpio.c +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -137,7 +137,7 @@ /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 Gerrit-Change-Number: 48649 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP wi...
by Subrata Banik (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49291 to look at the new patch set (#2). Change subject: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG ...................................................................... soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG This ENABLE_DISPLAY_OVER_DGPU Kconfig will allow ADLRVP to work with DG over PCIE to get display. Also ensure to turn off running IGD initialization using FSP GOP when ENABLE_DISPLAY_OVER_DGPU is enable. TEST=Able to get Pre-OS splash screen with AMD Radeon RX 5700 PCI-E DGPU when mainboard user selects ENABLE_DISPLAY_OVER_DGPU. Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/Kconfig 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/49291/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Gerrit-Change-Number: 49291 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Separate GPIO define into gpio_defs.h
by EricR Lai (Code Review) 11 Jan '21

11 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49216 ) Change subject: soc/amd/picasso: Separate GPIO define into gpio_defs.h ...................................................................... soc/amd/picasso: Separate GPIO define into gpio_defs.h Separate GPIO define into gpio_defs.h, then we can use it in asl include. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: If2a779eae228f621e77610889205853de2fb179a --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/gpio_banks.h A src/soc/amd/common/block/include/amdblocks/gpio_defs.h 3 files changed, 250 insertions(+), 244 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/49216/1 diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 8640cc1..df55cbf 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/iomap.h> - -#define GPIO_INPUT_SHIFT 16 -#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) -#define GPIO_OUTPUT_SHIFT 22 -#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) +#include <amdblocks/gpio_defs.h> /* Get pin control MMIO address */ Method (GPAD, 0x1) diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index b6162d7..6524d05 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -4,6 +4,7 @@ #define AMD_BLOCK_GPIO_BANKS_H #include <types.h> +#include "gpio_defs.h" struct soc_amd_gpio { uint8_t gpio; @@ -17,13 +18,6 @@ uint8_t event; }; -#define GPIO_MASTER_SWITCH 0xFC -#define GPIO_MASK_STS_EN BIT(28) -#define GPIO_INTERRUPT_EN BIT(30) -#define GPIO_WAKE_EN BIT(31) - -#define GPIO_WAKE_STAT_0 0x2F0 -#define GPIO_WAKE_STAT_1 0x2F4 struct gpio_wake_state { uint32_t control_switch; uint32_t wake_stat[2]; @@ -38,59 +32,6 @@ /* Add gpio events to the eventlog. */ void gpio_add_events(const struct gpio_wake_state *state); -#define GPIO_PIN_IN (1 << 0) /* for byte access */ -#define GPIO_PIN_OUT (1 << 6) /* for byte access */ - -/* Pad trigger type - Level or Edge */ -#define GPIO_TRIGGER_EDGE (0 << 8) -#define GPIO_TRIGGER_LEVEL (1 << 8) -#define GPIO_TRIGGER_MASK (1 << 8) - -/* - * Pad polarity: - * Level trigger - High or Low - * Edge trigger - High (Rising), Low (Falling), Both - */ -#define GPIO_ACTIVE_HIGH (0 << 9) -#define GPIO_ACTIVE_LOW (1 << 9) -#define GPIO_ACTIVE_BOTH (2 << 9) -#define GPIO_ACTIVE_MASK (3 << 9) - -/* - * Pad trigger and polarity configuration. - * This determines the filtering applied on the input signal at the pad. - */ -#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) -#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) - -#define GPIO_INT_ENABLE_STATUS (1 << 11) -#define GPIO_INT_ENABLE_DELIVERY (1 << 12) -#define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_INT_ENABLE_MASK (3 << 11) - -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) - -#define GPIO_PIN_STS (1 << 16) -#define GPIO_8KPULLUP_SELECT (1 << 19) -#define GPIO_PULLUP_ENABLE (1 << 20) -#define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (7 << 19) - -#define GPIO_OUTPUT_SHIFT 22 -#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) -#define GPIO_OUTPUT_ENABLE (1 << 23) -#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) - -#define GPIO_INT_STATUS (1 << 28) -#define GPIO_WAKE_STATUS (1 << 29) -#define GPIO_STATUS_MASK (3 << 28) - enum { GEVENT_0, GEVENT_1, @@ -126,39 +67,6 @@ GEVENT_31, }; -#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) -#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE - -#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) -#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE -#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE -#define GPIO_PULL_PULL_NONE 0 - -#define AMD_GPIO_MUX_MASK 0x03 - -/* - * Flags used for GPIO configuration. These provide additional information that does not go - * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. - */ -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) -#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) -#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) -#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) -#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) -#define GPIO_FLAG_SCI (1 << 2) -#define GPIO_FLAG_SMI (1 << 3) - -/* Trigger configuration for GPIO SCI/SMI events. */ -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ - GPIO_FLAG_EVENT_ACTIVE_HIGH) -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ - GPIO_FLAG_EVENT_ACTIVE_LOW) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ - GPIO_FLAG_EVENT_ACTIVE_HIGH) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ - GPIO_FLAG_EVENT_ACTIVE_LOW) - static inline bool is_gpio_event_level_triggered(uint32_t flags) { return (flags & GPIO_FLAG_EVENT_TRIGGER_MASK) == GPIO_FLAG_EVENT_TRIGGER_LEVEL; @@ -179,152 +87,6 @@ return (flags & GPIO_FLAG_EVENT_ACTIVE_MASK) == GPIO_FLAG_EVENT_ACTIVE_LOW; } -#define DEB_GLITCH_SHIFT 5 -#define DEB_GLITCH_LOW 1 -#define DEB_GLITCH_HIGH 2 -#define DEB_GLITCH_NONE 3 -#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) -#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) -#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) - -#define GPIO_TIMEBASE_61uS 0 -#define GPIO_TIMEBASE_183uS (1 << 4) -#define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) -#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) -#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) - -#define GPIO_DEB_MASK 0xff - -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (7 << 13) - -/* - * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` - * Bits that are preserved/untouched: - * - Reserved bits - * - Drive strength bits - * - Read only bits - */ -#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ - GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ - GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) - -/* - * Several macros are available to declare programming of GPIO pins. The defined macros and - * their parameters are: - * PAD_NF Define native alternate function for the pin. - * pin the pin to be programmed - * function the native function - * pull pull up, pull down or no pull - * PAD_GPI The pin is a GPIO input - * pin the pin to be programmed - * pull pull up, pull down or no pull - * PAD_GPO The pin is a GPIO output - * pin the pin to be programmed - * direction high or low - * PAD_INT The pin is regular interrupt that works while booting - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * action STATUS, DELIVER, STATUS_DELIVER - * PAD_SCI The pin is a SCI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH - * PAD_SMI The pin is a SMI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * event trigger LEVEL_LOW, LEVEL_HIGH - * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) - * PAD_DEBOUNCE The input or interrupt will be debounced - * pin the pin to be programmed - * pull pull up, pull down or no pull - * debounce_type preserve low glitch, preserve high glitch, no glitch - * debounce_time the debounce time - */ - -#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ - { \ - .gpio = __pin, \ - .function = __function, \ - .control = __control, \ - .flags = __flags, \ - } - -#define PAD_CFG_STRUCT(__pin, __function, __control) \ - PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) - -#define PAD_PULL(__pull) GPIO_PULL_ ## __pull -#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir -#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig -#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action -#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig -#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake -#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb - -/* Native function pad configuration */ -#define PAD_NF(pin, func, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) - -/* General purpose input pad configuration */ -#define PAD_GPI(pin, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) - -/* General purpose output pad configuration */ -#define PAD_GPO(pin, direction) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) - -/* Legacy interrupt pad configuration */ -#define PAD_INT(pin, pull, trigger, action) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) - -/* SCI pad configuration */ -#define PAD_SCI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ - PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) - -/* SMI pad configuration */ -#define PAD_SMI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ - PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) - -/* WAKE pad configuration */ -#define PAD_WAKE(pin, pull, trigger, type) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) - -/* pin debounce configuration */ -#define PAD_DEBOUNCE(pin, pull, type, time) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) - -/* No-connect pad - configured as input with PULL_DOWN */ -#define PAD_NC(pin) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) - typedef uint32_t gpio_t; /* diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h new file mode 100644 index 0000000..f0c6f66 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_GPIO_DEFS_H +#define AMD_BLOCK_GPIO_DEFS_H + +#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASK_STS_EN BIT(28) +#define GPIO_INTERRUPT_EN BIT(30) +#define GPIO_WAKE_EN BIT(31) + +#define GPIO_WAKE_STAT_0 0x2F0 +#define GPIO_WAKE_STAT_1 0x2F4 + +#define GPIO_PIN_IN (1 << 0) /* for byte access */ +#define GPIO_PIN_OUT (1 << 6) /* for byte access */ + +/* Pad trigger type - Level or Edge */ +#define GPIO_TRIGGER_EDGE (0 << 8) +#define GPIO_TRIGGER_LEVEL (1 << 8) +#define GPIO_TRIGGER_MASK (1 << 8) + +/* + * Pad polarity: + * Level trigger - High or Low + * Edge trigger - High (Rising), Low (Falling), Both + */ +#define GPIO_ACTIVE_HIGH (0 << 9) +#define GPIO_ACTIVE_LOW (1 << 9) +#define GPIO_ACTIVE_BOTH (2 << 9) +#define GPIO_ACTIVE_MASK (3 << 9) + +/* + * Pad trigger and polarity configuration. + * This determines the filtering applied on the input signal at the pad. + */ +#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) +#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) + +#define GPIO_INT_ENABLE_STATUS (1 << 11) +#define GPIO_INT_ENABLE_DELIVERY (1 << 12) +#define GPIO_INT_ENABLE_STATUS_DELIVERY \ + (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) +#define GPIO_INT_ENABLE_MASK (3 << 11) + +#define GPIO_S0I3_WAKE_EN (1 << 13) +#define GPIO_S3_WAKE_EN (1 << 14) +#define GPIO_S4_S5_WAKE_EN (1 << 15) + +#define GPIO_PIN_STS (1 << 16) +#define GPIO_8KPULLUP_SELECT (1 << 19) +#define GPIO_PULLUP_ENABLE (1 << 20) +#define GPIO_PULLDOWN_ENABLE (1 << 21) +#define GPIO_PULL_MASK (7 << 19) + +#define GPIO_INPUT_SHIFT 16 +#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) + +#define GPIO_OUTPUT_SHIFT 22 +#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) +#define GPIO_OUTPUT_ENABLE (1 << 23) +#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) + +#define GPIO_INT_STATUS (1 << 28) +#define GPIO_WAKE_STATUS (1 << 29) +#define GPIO_STATUS_MASK (3 << 28) + +#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) +#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE + +#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) +#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE +#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE +#define GPIO_PULL_PULL_NONE 0 + +#define AMD_GPIO_MUX_MASK 0x03 + +/* + * Flags used for GPIO configuration. These provide additional information that does not go + * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. + */ +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) +#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) +#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) +#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) +#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) +#define GPIO_FLAG_SCI (1 << 2) +#define GPIO_FLAG_SMI (1 << 3) + +/* Trigger configuration for GPIO SCI/SMI events. */ +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ + GPIO_FLAG_EVENT_ACTIVE_HIGH) +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ + GPIO_FLAG_EVENT_ACTIVE_LOW) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ + GPIO_FLAG_EVENT_ACTIVE_HIGH) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ + GPIO_FLAG_EVENT_ACTIVE_LOW) +#define DEB_GLITCH_SHIFT 5 +#define DEB_GLITCH_LOW 1 +#define DEB_GLITCH_HIGH 2 +#define DEB_GLITCH_NONE 3 +#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) +#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) +#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) + +#define GPIO_TIMEBASE_61uS 0 +#define GPIO_TIMEBASE_183uS (1 << 4) +#define GPIO_TIMEBASE_15560uS (1 << 7) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ + GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) +#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) +#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) + +#define GPIO_DEB_MASK 0xff + +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_MASK (7 << 13) + +/* + * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` + * Bits that are preserved/untouched: + * - Reserved bits + * - Drive strength bits + * - Read only bits + */ +#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ + GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ + GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) + +/* + * Several macros are available to declare programming of GPIO pins. The defined macros and + * their parameters are: + * PAD_NF Define native alternate function for the pin. + * pin the pin to be programmed + * function the native function + * pull pull up, pull down or no pull + * PAD_GPI The pin is a GPIO input + * pin the pin to be programmed + * pull pull up, pull down or no pull + * PAD_GPO The pin is a GPIO output + * pin the pin to be programmed + * direction high or low + * PAD_INT The pin is regular interrupt that works while booting + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * action STATUS, DELIVER, STATUS_DELIVER + * PAD_SCI The pin is a SCI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH + * PAD_SMI The pin is a SMI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * event trigger LEVEL_LOW, LEVEL_HIGH + * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) + * PAD_DEBOUNCE The input or interrupt will be debounced + * pin the pin to be programmed + * pull pull up, pull down or no pull + * debounce_type preserve low glitch, preserve high glitch, no glitch + * debounce_time the debounce time + */ + +#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ + { \ + .gpio = __pin, \ + .function = __function, \ + .control = __control, \ + .flags = __flags, \ + } + +#define PAD_CFG_STRUCT(__pin, __function, __control) \ + PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) + +#define PAD_PULL(__pull) GPIO_PULL_ ## __pull +#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir +#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig +#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action +#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig +#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake +#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb + +/* Native function pad configuration */ +#define PAD_NF(pin, func, pull) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) + +/* General purpose input pad configuration */ +#define PAD_GPI(pin, pull) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) + +/* General purpose output pad configuration */ +#define PAD_GPO(pin, direction) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) + +/* Legacy interrupt pad configuration */ +#define PAD_INT(pin, pull, trigger, action) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) + +/* SCI pad configuration */ +#define PAD_SCI(pin, pull, trigger) \ + PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ + PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) + +/* SMI pad configuration */ +#define PAD_SMI(pin, pull, trigger) \ + PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ + PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) + +/* WAKE pad configuration */ +#define PAD_WAKE(pin, pull, trigger, type) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) + +/* pin debounce configuration */ +#define PAD_DEBOUNCE(pin, pull, type, time) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) + +/* No-connect pad - configured as input with PULL_DOWN */ +#define PAD_NC(pin) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) + +#endif /* AMD_BLOCK_GPIO_DEFS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a779eae228f621e77610889205853de2fb179a Gerrit-Change-Number: 49216 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49246 ) Change subject: vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release ...................................................................... vc/intel/FSP2_0/CPX-SP: update to FSP ww01 release With Intel CPX-SP FSP ww01 release, CidBitMap field is added to DimmDevice struct in hob_memmap.h. The copyright statements were updated to accomodate year 2021. gpio_fsp.h is not needed any more as coreboot takes over GPIO configuration. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49246 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h 10 files changed, 10 insertions(+), 214 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h index 98a16d7..1ea5b07 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h @@ -2,7 +2,7 @@ Header file for Firmware Version Information @copyright - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h index 21b84a3..a42410c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h @@ -2,7 +2,7 @@ Intel FSP definition from Intel Firmware Support Package External Architecture Specification v2.0. - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved. + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved. This file and the accompanying materials are licensed and made available under the terms and conditions of the BSD License. The full text of the license may be found at diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h index 7491aca..7a4373e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index b4d4cad..8abff09 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h index fc08084..02e36ea 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h index b3c9661..e41d079 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h deleted file mode 100644 index be9d33f..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h +++ /dev/null @@ -1,205 +0,0 @@ -/** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef _GPIO_FSP_H_ -#define _GPIO_FSP_H_ - -// -// Below defines are based on GPIO_CONFIG structure fields -// -#define GPIO_CONF_PAD_MODE_MASK 0xF -#define GPIO_CONF_PAD_MODE_BIT_POS 0 -#define GPIO_CONF_HOST_OWN_MASK 0x3 -#define GPIO_CONF_HOST_OWN_BIT_POS 0 -#define GPIO_CONF_DIR_MASK 0x7 -#define GPIO_CONF_DIR_BIT_POS 0 -#define GPIO_CONF_INV_MASK 0x18 -#define GPIO_CONF_INV_BIT_POS 3 -#define GPIO_CONF_OUTPUT_MASK 0x3 -#define GPIO_CONF_OUTPUT_BIT_POS 0 -#define GPIO_CONF_INT_ROUTE_MASK 0x1F -#define GPIO_CONF_INT_ROUTE_BIT_POS 0 -#define GPIO_CONF_INT_TRIG_MASK 0xE0 -#define GPIO_CONF_INT_TRIG_BIT_POS 5 -#define GPIO_CONF_RESET_MASK 0x7 -#define GPIO_CONF_RESET_BIT_POS 0 -#define GPIO_CONF_TERM_MASK 0x1F -#define GPIO_CONF_TERM_BIT_POS 0 -#define GPIO_CONF_PADTOL_MASK 0x60 -#define GPIO_CONF_PADTOL_BIT_POS 5 -#define GPIO_CONF_LOCK_MASK 0x7 -#define GPIO_CONF_LOCK_BIT_POS 0 -#define GPIO_CONF_RXRAW_MASK 0x3 -#define GPIO_CONF_RXRAW_BIT_POS 0 - -typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; - -/// -/// GPIO Pad Mode -/// -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9 -} GPIO_PAD_MODE; - -/// -/// Host Software Pad Ownership modes -/// -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI - GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = - (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and - ///input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/// -/// GPIO Output State -/// -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/// -/// GPIO interrupt configuration -/// This setting is applicable only if GPIO is in input mode. -/// GPIO_INT_CONFIG allows to choose which interrupt is generated -/// (IOxAPIC/SCI/SMI/NMI) -/// and how it is triggered (edge or level). -/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to -/// GpioIntBothEdgecan -/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel -/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. -/// Not all GPIO are capable of generating an SMI or NMI interrupt -/// - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of - ///edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -/// -/// GPIO Power Configuration -/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified -/// Pad Register fields). -/// -typedef enum { - GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified - GpioResetPwrGood = 0x1, ///< Powergood reset - GpioResetDeep = 0x3, ///< Deep GPIO Reset - GpioResetNormal = 0x5, ///< GPIO Reset - GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) -} GPIO_RESET_CONFIG; - -/// -/// GPIO Electrical Configuration -/// Set GPIO termination and Pad Tolerance (applicable only for some pads) -/// Field from GpioTermDefault to GpioTermNative can be OR'ed with -/// GpioTolerance1v8. -/// -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - GpioTermNative = 0x1F, ///< Native function controls pads termination - GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance - GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance -} GPIO_ELECTRICAL_CONFIG; - -/// -/// GPIO LockConfiguration -/// Set GPIO configuration lock and output state lock -/// GpioLockPadConfig and GpioLockOutputState can be OR'ed -/// -typedef enum { - GpioLockDefault = 0x0, ///< Leave lock setting unmodified - GpioPadConfigLock = 0x3, ///< Lock Pad Configuration - GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value -} GPIO_LOCK_CONFIG; - -/// -/// Other GPIO Configuration -/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions -/// Supported settings: -/// - RX raw override to '1' - allows to override input value to '1' -/// This setting is applicable only if in input mode (both in GPIO and -/// native usage). -/// The override takes place at the internal pad state directly from buffer -/// and before the RXINV. -/// -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -// -// Possible values of Pad Ownership -// -typedef enum { - GpioPadOwnHost = 0x0, - GpioPadOwnCsme = 0x1, - GpioPadOwnIsh = 0x2, -} GPIO_PAD_OWN; - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 9900a12..3c6f9a7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +Copyright (c) 2019-2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 598d78c..52f3307 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +Copyright (c) 2019-2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -127,6 +127,7 @@ UINT8 EnergyType; UINT8 reserved10[1]; UINT16 SPDRegVen; // Register Vendor ID in SPD + UINT8 CidBitMap; // SubRankPer CS for DIMM device } MEMMAP_DIMM_DEVICE_INFO_STRUCT; struct ChannelDevice { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h index 9241692..93a1f9a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved. +Copyright (c) 2019-2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -- To view, visit https://review.coreboot.org/c/coreboot/+/49246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc Gerrit-Change-Number: 49246 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49243 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers ...................................................................... vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: John Zhao <john.zhao(a)intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 20 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified John Zhao: Looks good to me, but someone else must approve Srinidhi N Kaushik: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 276ac79..e791115 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved. +Copyright (c) 2021, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -931,7 +931,17 @@ /** Offset 0x04BA - Reserved **/ - UINT8 Reserved20[7]; + UINT8 Reserved20[2]; + +/** Offset 0x04BC - Disable TC code On USB Connect + Enable(default) or Disable TC cold On Usb Connected + $EN_DIS +**/ + UINT8 DisableTccoldOnUsbConnected; + +/** Offset 0x04BD - Reserved +**/ + UINT8 Reserved21[4]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -965,7 +975,7 @@ /** Offset 0x04C6 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; /** Offset 0x04C7 - VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) @@ -975,7 +985,7 @@ /** Offset 0x04C8 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved23; /** Offset 0x04C9 - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH @@ -985,7 +995,7 @@ /** Offset 0x04CA - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved24; /** Offset 0x04CB - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH @@ -1001,7 +1011,7 @@ /** Offset 0x04CD - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved25; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -1048,9 +1058,11 @@ **/ UINT8 VccSt; -/** Offset 0x04DD - Reserved +/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable + Used by IOM FW to skip powering down the PHY at the end of disconnect flow + $EN_DIS **/ - UINT8 Reserved25; + UINT8 Usb3ComplModeEnable; /** Offset 0x04DE - ITBT DMA LTR TCSS DMA1, DMA2 LTR value -- To view, visit https://review.coreboot.org/c/coreboot/+/49243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b32730293fc83b5088074f71fa215220574748 Gerrit-Change-Number: 49243 Gerrit-PatchSet: 4 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu: Copy page tables to DRAM in assembly
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49228 ) Change subject: mb/emulation/qemu: Copy page tables to DRAM in assembly ...................................................................... mb/emulation/qemu: Copy page tables to DRAM in assembly To work around various bugs running KVM enabled, copy page tables to DRAM in assembly before jumping to x86_64 mode. Tested on QEMU using KVM, no more stange bugs happen: Tested on host - CPU Intel(R) Core(TM) i7-7700HQ - Linux 5.9 - qemu 4.2.1 Used to crash on emulating MMX instructions and failed to translate some addresses using the virtual MMU when running in long mode. Tested on host - CPU AMD EPYC 7401P 24-Core Processor - Linux 5.4 - qemu 4.2.1 Used to crash on jumping to long mode. Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49228 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Makefile.inc M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/mainboard.c 6 files changed, 91 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index fb560d6..3f27e8b 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c +bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_64) += $(top)/src/arch/x86/walkcbfs.S romstage-y += ../intel/car/romstage.c diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index e3a26b0..07f848a 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -2,7 +2,14 @@ #include <cpu/x86/post_code.h> +#define CBFS_FILE_MAGIC 0 +#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) +#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) +#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) +#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) + .section .init, "ax", @progbits +.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -24,12 +31,55 @@ post_code(0x21) +#if defined(__x86_64__) + /* + * Copy page tables to final location in DRAM. This prevents some strange + * bugs when running KVM enabled: + * Accessing MMX instructions in long mode causes an abort + * Some physical addresses aren't properly translated + * Emulation fault on every instruction fetched due to page tables in ROM + * Enabling or disabling paging causes a fault + * + * First, find page tables in CBFS: + */ + lea pagetables_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmpl $0, %eax + je .Lhlt + + /* Test if page tables are memory-mapped and skip relocation */ + cmpl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + je pages_done + + movl CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + addl %eax, %ebx + movl %ebx, %esi + + movl CBFS_FILE_LEN(%eax), %ecx + bswap %ecx + shr $2, %ecx + + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %edi + +loop: + movl (%esi), %eax + movl %eax, (%edi) + addl $4, %esi + addl $4, %edi + decl %ecx + jnz loop +pages_done: +#endif + movl $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ + /* entry64.inc preserves ebx. */ #include <cpu/x86/64bit/entry64.inc> /* Restore the BIST result and timestamps. */ @@ -60,3 +110,6 @@ post_code(POST_DEAD_CODE) hlt jmp .Lhlt + +pagetables_name: + .string "pagetables" diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 62c23ca..1b61871 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -27,6 +27,15 @@ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP +if ARCH_BOOTBLOCK_X86_64 +# Need to install page tables in DRAM as the virtual MMU has problems translating paging +# request when the page table resides in emulated ROM. This causes undefined behaviour +# when handling data requests, as well as fetching and decoding instructions +# Real hardware didn't show any problems until now. +config ARCH_X86_64_PGTBL_LOC + default 0x8000 +endif + if VBOOT config VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 929743a..bc97554 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -28,8 +28,19 @@ pci_assign_irqs(pcidev_on_root(i, 0), qemu_i440fx_irqs + (i % 4)); } +static void qemu_nb_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ + reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, + (6 * 0x1000) / KiB); + } +} + static struct device_operations nb_operations = { - .read_resources = pci_dev_read_resources, + .read_resources = qemu_nb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = qemu_nb_init, diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c..d88d0da 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -32,6 +32,15 @@ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB +if ARCH_BOOTBLOCK_X86_64 +# Need to install page tables in DRAM as the virtual MMU has problems translating paging +# request when the page table resides in emulated ROM. This causes undefined behaviour +# when handling data requests, as well as fetching and decoding instructions +# Real hardware didn't show any problems until now. +config ARCH_X86_64_PGTBL_LOC + default 0x8000 +endif + if VBOOT config VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index d329e5a..c88874f 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -44,6 +44,12 @@ /* reserve mmconfig */ fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10, IORESOURCE_RESERVE); + + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ + reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, + (6 * 0x1000) / KiB); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/49228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4 Gerrit-Change-Number: 49228 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu: Copy page tables to DRAM in assembly
by Patrick Rudolph (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Martin Roth. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49228 ) Change subject: mb/emulation/qemu: Copy page tables to DRAM in assembly ...................................................................... Patch Set 1: (1 comment) File src/mainboard/emulation/qemu-i440fx/Kconfig: https://review.coreboot.org/c/coreboot/+/49228/comment/084e0cd7_6b4e5244 PS1, Line 35: ARCH_X86_64_PGTBL_LOC > Once you can migrate it to cbmem, could use the CAR symbols exposed with CONFIG_PAGING_IN_CACHE_AS_R […] Only if page tables are generated in assembly, as the linked address isn't known at compile time. This would also need at least 24KiB of space in CAR. You could however use two page tables, one in ROM for bringing up C bootblock and then generate new page tables in C with whatever layout you want. -- To view, visit https://review.coreboot.org/c/coreboot/+/49228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4 Gerrit-Change-Number: 49228 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 11 Jan 2021 07:34:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP wi...
by Subrata Banik (Code Review) 11 Jan '21

11 Jan '21

Attention is currently required from: Nico Huber, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49291 ) Change subject: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @Nico, Angel: can you please suggest me something how i can enable this feature -- To view, visit https://review.coreboot.org/c/coreboot/+/49291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Gerrit-Change-Number: 49291 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 11 Jan 2021 07:33:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Remove the unused touch controller
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49221 ) Change subject: mb/google/dedede/var/magolor: Remove the unused touch controller ...................................................................... mb/google/dedede/var/magolor: Remove the unused touch controller Remove unused touch controller - Goodix BUG=None BRANCH=dedede TEST=build firmware Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Reviewed-on: https://review.coreboot.org/c/coreboot/+/49221 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 0 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 0a92402..78d5dde 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -152,21 +152,6 @@ end # I2C 0 device pci 15.2 on chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "2" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x5d on end - end - chip drivers/i2c/hid register "generic.hid" = ""ELAN6915"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" -- To view, visit https://review.coreboot.org/c/coreboot/+/49221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Gerrit-Change-Number: 49221 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Enable wake from USB in S4
by Patrick Georgi (Code Review) 11 Jan '21

11 Jan '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49224 ) Change subject: soc/intel/cannonlake: Enable wake from USB in S4 ...................................................................... soc/intel/cannonlake: Enable wake from USB in S4 The xHCI controller supports waking the system from S1-S4. Thus specify that the deepest sleep state is S4 in _PRW. Tested on Prodrive/hermes. The board now wakes from S4 as well by pressing a key on the USB keyboard. Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224 Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/acpi/xhci.asl 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 7d89665..50c0cb8 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -67,7 +67,7 @@ { Name (_ADR, 0x00140000) - Name (_PRW, Package () { GPE0_PME_B0, 3 }) + Name (_PRW, Package () { GPE0_PME_B0, 4 }) Method (_DSW, 3) { @@ -79,6 +79,9 @@ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ + Name (_S4D, 3) /* D3 supported in S4 */ + Name (_S4W, 3) /* D3 can wake system from S4 */ + OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { -- To view, visit https://review.coreboot.org/c/coreboot/+/49224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Gerrit-Change-Number: 49224 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2021