coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using...
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41880 ) Change subject: mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using gen_part_id.go ...................................................................... mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledoo and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:F Byte# Current New Explanation 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Waddledoo started assigning DRAM part IDs from 1. So, this change fills in Nanya part as ID 0 (though it is currently unused). Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc A src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41880/1 diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc new file mode 100644 index 0000000..267cd0d --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +MEM_TYPE = lp4x +SPD_SOURCES = +SPD_SOURCES += spd-9.hex # ID = 0(0b0000) Parts = NT6AP256T32AV-J2 +SPD_SOURCES += spd-8.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt new file mode 100644 index 0000000..4c76adf --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +NT6AP256T32AV-J2 0 (0000) +MT53E512M32D2NP-046 WT:F 1 (0001) diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt new file mode 100644 index 0000000..9f146d4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt @@ -0,0 +1,2 @@ +NT6AP256T32AV-J2 +MT53E512M32D2NP-046 WT:F -- To view, visit https://review.coreboot.org/c/coreboot/+/41880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Gerrit-Change-Number: 41880 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/dedede: Switch to using auto-generated SPDs
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41881 ) Change subject: mb/google/dedede: Switch to using auto-generated SPDs ...................................................................... mb/google/dedede: Switch to using auto-generated SPDs This change switches dedede and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/Makefile.inc M src/mainboard/google/dedede/spd/Makefile.inc M src/mainboard/google/dedede/variants/waddledee/Makefile.inc M src/mainboard/google/dedede/variants/waddledoo/Makefile.inc D src/mainboard/google/dedede/variants/wheelie/Makefile.inc 5 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/41881/1 diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index 9af93dd..591c4fc 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -19,4 +19,5 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/$(VARIANT_DIR) +subdirs-y += variants/$(VARIANT_DIR)/memory CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc index 24c3465..886460c 100644 --- a/src/mainboard/google/dedede/spd/Makefile.inc +++ b/src/mainboard/google/dedede/spd/Makefile.inc @@ -3,7 +3,7 @@ ifneq ($(SPD_SOURCES),) SPD_BIN = $(obj)/spd.bin -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/soc/intel/jasperlake/spd/$(MEM_TYPE)/$(f).spd.hex) # Include spd ROM data $(SPD_BIN): $(SPD_DEPS) diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc index 1813377..eda535c 100644 --- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -SPD_SOURCES = SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0000 -SPD_SOURCES += SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 #0b0001 - romstage-y += memory.c ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc index 11bbbd6..eda535c 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc +++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc @@ -1,8 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -SPD_SOURCES = empty #0b0000 -SPD_SOURCES += SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0001 - romstage-y += memory.c ramstage-y += variant.c diff --git a/src/mainboard/google/dedede/variants/wheelie/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/Makefile.inc deleted file mode 100644 index 6c8c913..0000000 --- a/src/mainboard/google/dedede/variants/wheelie/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/41881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51 Gerrit-Change-Number: 41881 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 07 Jun '20

07 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40806 ) Change subject: sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register ...................................................................... sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb800/late.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/40806/1 diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e4a1795..0993d2d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -99,7 +99,7 @@ } dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_write_config16(dev, PCI_COMMAND, dev->command); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345 Gerrit-Change-Number: 40806 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: [WIP] drivers/pc80/rtc: Drop ARCH_X86 guard in header
by Kyösti Mälkki (Code Review) 07 Jun '20

07 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38197 ) Change subject: [WIP] drivers/pc80/rtc: Drop ARCH_X86 guard in header ...................................................................... [WIP] drivers/pc80/rtc: Drop ARCH_X86 guard in header Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/elog/boot_count.c M src/drivers/elog/elog.c M src/include/pc80/mc146818rtc.h M src/lib/bootblock.c 4 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/38197/1 diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index a6efb01..6823a93 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -13,7 +13,6 @@ #include <console/console.h> #include <ip_checksum.h> -#include <pc80/mc146818rtc.h> #include <stddef.h> #include <stdint.h> #include <elog.h> diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 11cbfba..7f6c75b 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -17,9 +17,6 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#if CONFIG(ARCH_X86) -#include <pc80/mc146818rtc.h> -#endif #include <bcd.h> #include <boot_device.h> #include <commonlib/region.h> diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 8cc2ed4..f6359f1 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -1,14 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef PC80_MC146818RTC_H #define PC80_MC146818RTC_H -#if CONFIG(ARCH_X86) - #include <arch/io.h> #include <types.h> -#ifndef RTC_BASE_PORT #define RTC_BASE_PORT 0x70 -#endif #define RTC_PORT(x) (RTC_BASE_PORT + (x)) @@ -181,8 +190,4 @@ int cmos_checksum_valid(int range_start, int range_end, int cks_loc); void cmos_set_checksum(int range_start, int range_end, int cks_loc); -#endif /* CONFIG_ARCH_X86 */ - -void cmos_post_init(void); - #endif /* PC80_MC146818RTC_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 386f4e3..166b3fe 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <delay.h> #include <option.h> -#include <pc80/mc146818rtc.h> #include <program_loading.h> #include <symbols.h> #include <timestamp.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a Gerrit-Change-Number: 38197 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: soc/intel/tigerlake: Add CPU ID for TGL B0
by Jamie Ryu (Code Review) 07 Jun '20

07 Jun '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41516 ) Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0 ...................................................................... soc/intel/tigerlake: Add CPU ID for TGL B0 BRANCH=none BUG=none TEST=build and boot tglrvp Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41516/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 5cd0134..90bae16 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -73,6 +73,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0}, { 0, 0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c15c323..e03d8bd 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -41,6 +41,7 @@ #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 #define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 #define CPUID_TIGERLAKE_A0 0x806c0 +#define CPUID_TIGERLAKE_B0 0x806c1 #define CPUID_ELKHARTLAKE_A0 0x90660 /* diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index d6d9f36..a64738d 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_TIGERLAKE_B0, "Tigerlake B0" }, }; static struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/41516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e Gerrit-Change-Number: 41516 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/amd/picasso: Remove call to setup_bsp_ramtop
by Raul Rangel (Code Review) 07 Jun '20

07 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42086 ) Change subject: soc/amd/picasso: Remove call to setup_bsp_ramtop ...................................................................... soc/amd/picasso: Remove call to setup_bsp_ramtop We don't use amd_setup_mtrrs in picasso. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1941934975dfea4f189347811b003a33996c887a --- M src/soc/amd/picasso/chip.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42086/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index dc661d2..e2b45b4 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cpu/amd/mtrr.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -149,7 +148,6 @@ data_fabric_set_mmio_np(); southbridge_init(chip_info); - setup_bsp_ramtop(); } static void soc_final(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/42086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1941934975dfea4f189347811b003a33996c887a Gerrit-Change-Number: 42086 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: src: Remove unused '#include <cpu/x86/smm.h>'
by HAOUAS Elyes (Code Review) 07 Jun '20

07 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41685 ) Change subject: src: Remove unused '#include <cpu/x86/smm.h>' ...................................................................... src: Remove unused '#include <cpu/x86/smm.h>' Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell_init.c M src/drivers/elog/gsmi.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/spi/spi_flash.c M src/mainboard/google/stout/ec.c M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/cpu.c M src/southbridge/intel/common/pmutil.c 16 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41685/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4d1a536..4778943 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -13,7 +13,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <delay.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index cd69d4f..ebdde19 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <cpu/x86/smm.h> #include <elog.h> #define GSMI_RET_SUCCESS 0x00 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 5185e20..9b47e71 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index f59f4f5..cd4a1e6 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <acpi/acpi.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <fsp/ramstage.h> #include <fsp/util.h> #include <lib.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3ffb87e..da2e868 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -4,7 +4,6 @@ #include <boot_device.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index d80e225..6e9b490 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -4,7 +4,6 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a728e0e..c282aea 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -11,7 +11,6 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <boot/tables.h> #include "chip.h" diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a2d5188..595e6a2 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -8,7 +8,6 @@ #include <assert.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 09537a1..bdd6e8c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <cpu/x86/pae.h> #include <delay.h> -#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b4bad8a..582308a 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 03f77c6..094e1c2 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -8,7 +8,6 @@ #include <bootstate.h> #include "chip.h" #include <console/console.h> -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 1923301..859db7f 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <delay.h> #include <intelblocks/cpulib.h> #include <soc/cpu.h> diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 35ce010..b85b663 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,7 +3,6 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> -#include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 59f76cc..abfd3de 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -6,7 +6,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index bfa59fe..89b7cb6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -13,7 +13,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 305aef0..d0eeb04 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -3,7 +3,6 @@ #include <types.h> #include <console/console.h> #include <device/pci_def.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Gerrit-Change-Number: 41685 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Use MSR_CSTATE_ADDRESS
by Raul Rangel (Code Review) 07 Jun '20

07 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42087 ) Change subject: soc/amd/picasso: Use MSR_CSTATE_ADDRESS ...................................................................... soc/amd/picasso: Use MSR_CSTATE_ADDRESS This is a standard MSR. No reason for picasso to define its own. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/southbridge.c 2 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/42087/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 99b31c3..fd9c5fe 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__ -#define CSTATE_BASE_REG 0xc0010073 - int get_cpu_count(void); void check_mca(void); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 123eca7..a18f5a3 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/mmio.h> #include <bootstate.h> +#include <cpu/amd/msr.h> #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> #include <device/device.h> @@ -318,7 +319,7 @@ /* CpuControl is in \_SB.CP00, 6 bytes */ cst_addr.hi = 0; cst_addr.lo = ACPI_CPU_CONTROL; - wrmsr(CSTATE_BASE_REG, cst_addr); + wrmsr(MSR_CSTATE_ADDRESS, cst_addr); if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 Gerrit-Change-Number: 42087 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Add support for RT 1308
by Shaunak Saha (Code Review) 07 Jun '20

07 Jun '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41808 ) Change subject: mb/intel/tglrvp: Add support for RT 1308 ...................................................................... mb/intel/tglrvp: Add support for RT 1308 Add support for RT 1308 audio amplifier in TGLRVP. We are using the i2c generic driver here to generate the SSDT file. Datasheet:ALC-1308-CG-version-08. BUG=none BRANCH=none TEST=Build and boot tglrvp successfully. In kernel console use the "aplay -l" command to check souncard is listed. Change-Id: I41d205a3ab87db85baf49e9e8a582c226ba5832d Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/41808/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 7669b18..e06032d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -187,6 +187,12 @@ end device pci 15.0 on # I2C0 0xA0E8 + chip drivers/i2c/generic + register "hid" = ""10EC1308"" + register "name" = ""RTAM"" + register "desc" = ""Realtek RT1308 Codec"" + device i2c 10 on end + end chip drivers/i2c/max98373 register "vmon_slot_no" = "4" register "imon_slot_no" = "5" -- To view, visit https://review.coreboot.org/c/coreboot/+/41808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41d205a3ab87db85baf49e9e8a582c226ba5832d Gerrit-Change-Number: 41808 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/garg: Add G2Touch touchscreen support
by Tony Huang (Code Review) 07 Jun '20

07 Jun '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42036 ) Change subject: mb/google/octopus/variants/garg: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/garg: Add G2Touch touchscreen support BUG=b:156564296 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I99b04fec88da481e21b7a05807a4f1edeb3a5bdf Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/garg/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42036/1 diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index 0230a29..a91a730 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -172,6 +172,20 @@ register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/42036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99b04fec88da481e21b7a05807a4f1edeb3a5bdf Gerrit-Change-Number: 42036 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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