Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42087 )
Change subject: soc/amd/picasso: Use MSR_CSTATE_ADDRESS ......................................................................
soc/amd/picasso: Use MSR_CSTATE_ADDRESS
This is a standard MSR. No reason for picasso to define its own.
BUG=b:147042464 TEST=Boot to OS on trembyle
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/southbridge.c 2 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/42087/1
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 99b31c3..fd9c5fe 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__
-#define CSTATE_BASE_REG 0xc0010073 - int get_cpu_count(void); void check_mca(void);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 123eca7..a18f5a3 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/mmio.h> #include <bootstate.h> +#include <cpu/amd/msr.h> #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> #include <device/device.h> @@ -318,7 +319,7 @@ /* CpuControl is in _SB.CP00, 6 bytes */ cst_addr.hi = 0; cst_addr.lo = ACPI_CPU_CONTROL; - wrmsr(CSTATE_BASE_REG, cst_addr); + wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42087 )
Change subject: soc/amd/picasso: Use MSR_CSTATE_ADDRESS ......................................................................
Patch Set 1: Code-Review+2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42087 )
Change subject: soc/amd/picasso: Use MSR_CSTATE_ADDRESS ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42087 )
Change subject: soc/amd/picasso: Use MSR_CSTATE_ADDRESS ......................................................................
soc/amd/picasso: Use MSR_CSTATE_ADDRESS
This is a standard MSR. No reason for picasso to define its own.
BUG=b:147042464 TEST=Boot to OS on trembyle
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087 Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/southbridge.c 2 files changed, 2 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 99b31c3..fd9c5fe 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__
-#define CSTATE_BASE_REG 0xc0010073 - int get_cpu_count(void); void check_mca(void);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 123eca7..a18f5a3 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/mmio.h> #include <bootstate.h> +#include <cpu/amd/msr.h> #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> #include <device/device.h> @@ -318,7 +319,7 @@ /* CpuControl is in _SB.CP00, 6 bytes */ cst_addr.hi = 0; cst_addr.lo = ACPI_CPU_CONTROL; - wrmsr(CSTATE_BASE_REG, cst_addr); + wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42087 )
Change subject: soc/amd/picasso: Use MSR_CSTATE_ADDRESS ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/5034 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5033 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5032 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/5031
Please note: This test is under development and might not be accurate at all!