HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41685 )
Change subject: src: Remove unused '#include <cpu/x86/smm.h>' ......................................................................
src: Remove unused '#include <cpu/x86/smm.h>'
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/haswell_init.c M src/drivers/elog/gsmi.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/spi/spi_flash.c M src/mainboard/google/stout/ec.c M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/cpu.c M src/southbridge/intel/common/pmutil.c 16 files changed, 0 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/41685/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4d1a536..4778943 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -13,7 +13,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <delay.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index cd69d4f..ebdde19 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> -#include <cpu/x86/smm.h> #include <elog.h>
#define GSMI_RET_SUCCESS 0x00 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 5185e20..9b47e71 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index f59f4f5..cd4a1e6 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <acpi/acpi.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <fsp/ramstage.h> #include <fsp/util.h> #include <lib.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3ffb87e..da2e868 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -4,7 +4,6 @@ #include <boot_device.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index d80e225..6e9b490 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -4,7 +4,6 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a728e0e..c282aea 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -11,7 +11,6 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <boot/tables.h>
#include "chip.h" diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a2d5188..595e6a2 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -8,7 +8,6 @@ #include <assert.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 09537a1..bdd6e8c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <cpu/x86/pae.h> #include <delay.h> -#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b4bad8a..582308a 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 03f77c6..094e1c2 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -8,7 +8,6 @@ #include <bootstate.h> #include "chip.h" #include <console/console.h> -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 1923301..859db7f 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <delay.h> #include <intelblocks/cpulib.h> #include <soc/cpu.h> diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 35ce010..b85b663 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,7 +3,6 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> -#include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 59f76cc..abfd3de 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -6,7 +6,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index bfa59fe..89b7cb6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -13,7 +13,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 305aef0..d0eeb04 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -3,7 +3,6 @@ #include <types.h> #include <console/console.h> #include <device/pci_def.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h>
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41685 )
Change subject: src: Remove unused '#include <cpu/x86/smm.h>' ......................................................................
Patch Set 4: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41685 )
Change subject: src: Remove unused '#include <cpu/x86/smm.h>' ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41685 )
Change subject: src: Remove unused '#include <cpu/x86/smm.h>' ......................................................................
src: Remove unused '#include <cpu/x86/smm.h>'
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685 Reviewed-by: David Guckian Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/haswell_init.c M src/drivers/elog/gsmi.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/spi/spi_flash.c M src/mainboard/google/stout/ec.c M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/cpu.c M src/southbridge/intel/common/pmutil.c 16 files changed, 0 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4d1a536..4778943 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -13,7 +13,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <delay.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index cd69d4f..ebdde19 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h> -#include <cpu/x86/smm.h> #include <elog.h>
#define GSMI_RET_SUCCESS 0x00 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 5185e20..9b47e71 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index f59f4f5..cd4a1e6 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -3,7 +3,6 @@ #include <bootmode.h> #include <acpi/acpi.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <fsp/ramstage.h> #include <fsp/util.h> #include <lib.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 3ffb87e..da2e868 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -4,7 +4,6 @@ #include <boot_device.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index d80e225..6e9b490 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -4,7 +4,6 @@ #include <bootmode.h> #include <types.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <ec/quanta/it8518/ec.h> #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a728e0e..c282aea 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -11,7 +11,6 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <boot/tables.h>
#include "chip.h" diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a2d5188..595e6a2 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -8,7 +8,6 @@ #include <assert.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <cpu/x86/smm.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 09537a1..bdd6e8c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <cpu/x86/pae.h> #include <delay.h> -#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index bb01844..32b1385 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 03f77c6..094e1c2 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -8,7 +8,6 @@ #include <bootstate.h> #include "chip.h" #include <console/console.h> -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 1923301..859db7f 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -14,7 +14,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <delay.h> #include <intelblocks/cpulib.h> #include <soc/cpu.h> diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 35ce010..b85b663 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -3,7 +3,6 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> -#include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 59f76cc..abfd3de 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -6,7 +6,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index bfa59fe..89b7cb6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -13,7 +13,6 @@ #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> -#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 305aef0..d0eeb04 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -3,7 +3,6 @@ #include <types.h> #include <console/console.h> #include <device/pci_def.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h>
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41685 )
Change subject: src: Remove unused '#include <cpu/x86/smm.h>' ......................................................................
Patch Set 7:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/5040 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5039 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5038 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/5037
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
David Guckian (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)