coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by 9elements QA (Code Review) 07 Jun '20

07 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42072 ) Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4943 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4942 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4941 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4940 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 07 Jun 2020 17:36:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add section about 'hidden' devices to 4.13 release notes
by Tim Wawrzynczak (Code Review) 07 Jun '20

07 Jun '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41563 ) Change subject: Documentation: Add section about 'hidden' devices to 4.13 release notes ...................................................................... Documentation: Add section about 'hidden' devices to 4.13 release notes CB:41384 added some new functionality to devicetree files ("hidden PCI devices"). It's a decent enough semantic change that it should be added to the release notes for the 4.13 release. Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M Documentation/releases/coreboot-4.13-relnotes.md 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/41563/1 diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 94e93bb..0175250 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -13,4 +13,17 @@ Significant changes ------------------- -### Add significant changes here +### Hidden PCI devices + +This new functionality takes advantage of the existing 'hidden' keyword in the +devicetree. Since no existing boards were using the keyword, its usage was +repurposed to make dealing with some unique PCI devices easier. The particular +case here is Intel's PMC (Power Management Controller). During the FSP-S run, +the PMC device is made hidden, meaning that its config space looks as if there +is no device there (Vendor ID reads as 0xFFFF_FFFF). However, the device does +have fixed resources, both MMIO and I/O. These were previously recorded in +different places (MMIO was typically an SA fixed resource, and I/O was treated +as an LPC resource). With this change, when a device in the tree is marked as +'hidden', it is not probed (`pci_probe_dev()`) but rather assumed to exist so +that its resources can be placed in a more natural location. This also adds the +ability for the device to participate in SSDT generation. -- To view, visit https://review.coreboot.org/c/coreboot/+/41563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33 Gerrit-Change-Number: 41563 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/trogdor: Remove RO_FSG region
by Julius Werner (Code Review) 07 Jun '20

07 Jun '20

Hello Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41980 to review the following change. Change subject: google/trogdor: Remove RO_FSG region ...................................................................... google/trogdor: Remove RO_FSG region We decided to store the FSG on eMMC instead of SPI flash, so we don't need this region anymore. Getting rid of it allows us to put more space into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining amount to keep the FMAP alignment reasonable. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c --- M src/mainboard/google/trogdor/chromeos.fmd 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41980/1 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 2f93712..3aa0473 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -2,17 +2,16 @@ FLASH@0x0 8M { WP_RO 4M { - RO_SECTION 0x204000 { + RO_SECTION 0x3c4000 { BOOTBLOCK 96K COREBOOT(CBFS) - FMAP@0x200000 0x1000 + FMAP@0x3c0000 0x1000 GBB 0x2f00 RO_FRID 0x100 } - RO_VPD(PRESERVE) 16K + RO_VPD(PRESERVE) 228K RO_DDR_TRAINING(PRESERVE) 8K RO_LIMITS_CFG(PRESERVE) 4K - RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K -- To view, visit https://review.coreboot.org/c/coreboot/+/41980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c Gerrit-Change-Number: 41980 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/spi: add and use define for last FIFO position
by Felix Held (Code Review) 07 Jun '20

07 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42076 ) Change subject: soc/amd/common/spi: add and use define for last FIFO position ...................................................................... soc/amd/common/spi: add and use define for last FIFO position The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but turned out to be correct. Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/spi.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42076/1 diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index fec099d..6854a1a 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -55,7 +55,8 @@ #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_FIFO 0x80 -#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) +#define SPI_FIFO_LAST_BYTE 0xc7 +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO) struct spi_config { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98 Gerrit-Change-Number: 42076 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devices
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42067 ) Change subject: soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devices ...................................................................... soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devices This change adds a helper function set_mmio_dev_ops() in chip.c which is used for setting the dev->ops for MMIO devices based on the comparison of MMIO address in device tree to the pre-defined base addresses in iomap.h. Call to i2c_acpi_name() is replaced with set_mmio_dev_ops and scope of i2c_acpi_name is restricted to i2c.c since it is not required to be exposed out of that file. Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/i2c.c 2 files changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42067/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index dc661d2..ed39b53 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -8,6 +8,7 @@ #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/data_fabric.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include "chip.h" @@ -15,7 +16,6 @@ /* Supplied by i2c.c */ extern struct device_operations picasso_i2c_mmio_ops; -extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, @@ -119,6 +119,17 @@ .acpi_fill_ssdt = acpi_device_write_pci_dev, }; +static void set_mmio_dev_ops(struct device *dev) +{ + switch (dev->path.mmio.addr) { + case APU_I2C2_BASE: + case APU_I2C3_BASE: + case APU_I2C4_BASE: + dev->ops = &picasso_i2c_mmio_ops; + break; + } +} + static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -136,8 +147,7 @@ } sb_enable(dev); } else if (dev->path.type == DEVICE_PATH_MMIO) { - if (i2c_acpi_name(dev) != NULL) - dev->ops = &picasso_i2c_mmio_ops; + set_mmio_dev_ops(dev); } } diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 4c8c669..fa59b99 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -13,9 +13,6 @@ #include <soc/southbridge.h> #include "chip.h" -/* Global to provide access to chip.c */ -const char *i2c_acpi_name(const struct device *dev); - /* * We don't have addresses for I2C0-1. */ @@ -48,7 +45,7 @@ return &config->i2c[bus]; } -const char *i2c_acpi_name(const struct device *dev) +static const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { case APU_I2C2_BASE: -- To view, visit https://review.coreboot.org/c/coreboot/+/42067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6 Gerrit-Change-Number: 42067 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Remove dead code
by Angel Pons (Code Review) 07 Jun '20

07 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42013 ) Change subject: sb/intel/bd82x6x: Remove dead code ...................................................................... sb/intel/bd82x6x: Remove dead code Drop functions that are not being used. Change-Id: If406601f3bb7a98a621c1339b2f3413a43b8cc9f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 0 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42013/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b319c28..c60b673 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -112,39 +112,6 @@ return 0; } -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - printk(BIOS_NOTICE, "ME: Requesting global reset\n"); - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - #ifdef __SIMPLE_DEVICE__ static void intel_me7_finalize_smm(void) diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 12b3a46..0d51f6f 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -324,21 +324,6 @@ (me.buffer_depth - 1); } -#if 0 -/* This function is not yet being used, keep it in for the future. */ -static u32 host_to_me_words_room(void) -{ - struct mei_csr csr; - - read_me_csr(&csr); - if (!csr.ready) - return 0; - - read_host_csr(&csr); - return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & - (csr.buffer_depth - 1); -} -#endif /* * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. -- To view, visit https://review.coreboot.org/c/coreboot/+/42013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If406601f3bb7a98a621c1339b2f3413a43b8cc9f Gerrit-Change-Number: 42013 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register
by HAOUAS Elyes (Code Review) 07 Jun '20

07 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40835 ) Change subject: nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register ...................................................................... nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/iommu.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/1 diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4d88e36..a0f85f9 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -37,9 +37,9 @@ pci_devfn_t igd = PCI_DEV(0, 2, 0); /* setup somewhere */ - u8 cmd = pci_read_config8(igd, PCI_COMMAND); + u16 cmd = pci_read_config16(igd, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); /* clear GTT, 2MB is enough (and should be safe) */ @@ -47,7 +47,7 @@ /* and now disable again */ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by Paul Menzel (Code Review) 07 Jun '20

07 Jun '20

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Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by Paul Menzel (Code Review) 07 Jun '20

07 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... Patch Set 51: (18 comments) https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@7 PS51, Line 7: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F > mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@15 PS51, Line 15: DevTree I’d spell it devicetree. https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@16 PS51, Line 16: Linux What version (and what payload)? https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@17 PS51, Line 17: Slots slots https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@21 PS51, Line 21: * Proper ACPI Tables What does this mean? https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@22 PS51, Line 22: * Windows Support What version, and what payload (with version)? https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@25 PS51, Line 25: Tested with Intel Xeon E-2186G and 64 GB ECC RAM. How long does coreboot take to execute? https://review.coreboot.org/c/coreboot/+/37441/51//COMMIT_MSG@26 PS51, Line 26: Please mention, why the code can’t be shared with the x11-lga1151 series code. https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/i… File Documentation/mainboard/index.md: https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/i… PS51, Line 150: LGA1151V2 v2 https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md: https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 1: LGA1151V2 v2? https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 3: series series boards https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 18: - [Intel FSP2.0] can not be removed as long as there is no free replacement Please add a dot at the end of sentences. https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 29: - MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0]) 1. Please add a dot/period at the end of sentences. 2. Please mention the result: The full RAM training of 64 GB ECC RAM lasts X seconds. https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 52: https://www.supermicro.com/en/products/motherboards?pro=cpu%3DUP%26processo… That URL does not work for me. https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 52: LGA1151 v2 https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 3: This section details how to run coreboot on the [Supermicro X11SCH-F]. … The -F denotes that a BMC is part of the device. https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 30: - TPM on TPM expansion header Mention the patching of IFD as written in the commit message? https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… PS51, Line 34: See general issue section. Where is that section? Maybe link to it? -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 51 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 07 Jun 2020 14:58:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by Angel Pons (Code Review) 07 Jun '20

07 Jun '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... Patch Set 51: (1 comment) https://review.coreboot.org/c/coreboot/+/37441/51/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg: PS51: That looks rather small to be a flash chip. Is it in a 150 mil SOIC-8 package, as opposed to the usual 200 mil packages for flash chips? -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 51 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-Comment-Date: Sun, 07 Jun 2020 14:08:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2020