coreboot-gerrit June 2020

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Change in coreboot[master]: soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G
by Furquan Shaikh (Code Review) 06 Jun '20

06 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41155 ) Change subject: soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G ...................................................................... soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G This change sets the base for MMIO above 4G to TOUDD. It matches what is used by resource allocator if MMIO resources are allocated above 4G and also matches the expectation in northbridge.asl. BUG=b:149186922 TEST=Verified that kernel does not complain about MMIO windows above 4G. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383 --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 31 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41155/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d0e171d..9354c25 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -42,34 +42,6 @@ } /* - * This function will get above 4GB mmio enable config specific to soc. - * - * Return values: - * 0 = Above 4GB memory is not enable - * 1 = Above 4GB memory is enable - */ -static int get_enable_above_4GB_mmio(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->enable_above_4GB_mmio; -} - -/* Fill MMIO resource above 4GB into GNVS */ -void sa_fill_gnvs(global_nvs_t *gnvs) -{ - if (get_enable_above_4GB_mmio()) { - gnvs->e4gm = 1; - gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS; - gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; - printk(BIOS_DEBUG, - "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", - gnvs->a4gb, gnvs->a4gs); - } -} - -/* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ @@ -125,6 +97,37 @@ *result = value; } +/* + * This function will get above 4GB mmio enable config specific to soc. + * + * Return values: + * 0 = Above 4GB memory is not enable + * 1 = Above 4GB memory is enable + */ +static int get_enable_above_4GB_mmio(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->enable_above_4GB_mmio; +} + +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs) +{ + if (!get_enable_above_4GB_mmio()) + return; + + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + + gnvs->e4gm = 1; + sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); + gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gb, gnvs->a4gs); +} + + static void sa_get_mem_map(struct device *dev, uint64_t *values) { int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/41155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383 Gerrit-Change-Number: 41155 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP
by Eugene Myers (Code Review) 05 Jun '20

05 Jun '20

Eugene Myers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41829 ) Change subject: [WIP] cpu/x86/smm: Enable SMM support for Xeon-SP ...................................................................... Patch Set 3: (2 comments) > Patch Set 3: > > (18 comments) > > > Patch Set 2: > > > > > Patch Set 2: > > > > > > (3 comments) > > > > > > This change is ready for review. > > > > Fat finger - needs changes first. > > Eugene, > Thank you for the review. I've uploaded patch set 3 with your feedback. I also updated the SMRAM layout map (described on top of smm_load_module). STM stays as is. Moved stacks to the start of SMRAM since stacks grow downward and they can't corrupt any SMM code. SMM GDT (global descriptor table) is set for flat code and flat data, so there are no protections. By having stacks on top, in theory they could grow downward enough to corrupt code and data, though we have a canary in place, it could still cause problems. That is my reasoning for moving stacks to the bottom for better protection (unless we change the descriptor for stack segment and make it bound, then it can be anywhere in SMRAM). Rocky, I've ported your code to my test system and realized that there were a couple of issues. The first is the location of the fxsave area, the calculation placed the area outside of SMRAM. The second is that the algorithm to place the entrypoints has to account for the SMM save state areas. I've borrowed some documentation to help give you a start. gene https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… PS3, Line 96: When building these segments the algorithm needs to account for the SMM save state size and location. This area includes the SMM save state and the TXT Processor SMM Descriptor. That layout is as follows: SMBASE+0xFC00 SMM Save state map SMBASE+0xFB00 TXT Processor SMM Descriptor SMBASE+0x8000 Entry point SMBASE I believe what you are trying to do is something like this: (note: this diagram is from - https://github.com/jyao1/STM/blob/master/Bios/StmCpuPkg/PiSmmCpuDxeSmm/PiSm… ) // // The CPU save state and code for the SMI entry point are tiled within an SMRAM // allocated buffer. The minimum size of this buffer for a uniprocessor system // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area // just below SMBASE + 64KB. If more than one CPU is present in the platform, // then the SMI entry point and the CPU save state areas can be tiles to minimize // the total amount SMRAM required for all the CPUs. The tile size can be computed // by adding the // CPU save state size, any extra CPU specific context, and // the size of code that must be placed at the SMI entry point to transfer // control to a C function in the native SMM execution mode. This size is // rounded up to the nearest power of 2 to give the tile size for a each CPU. // The total amount of memory required is the maximum number of CPUs that // platform supports times the tile size. The picture below shows the tiling, // where m is the number of tiles that fit in 32KB. // // +-----------------------------+ <-- 2^n offset from Base of allocated buffer // | CPU m+1 Save State | // +-----------------------------+ // | CPU m+1 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU 2m SMI Entry | // +#############################+ <-- Base of allocated buffer + 64 KB // | CPU m-1 Save State | // +-----------------------------+ // | CPU m-1 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU 2m-1 SMI Entry | // +=============================+ <-- 2^n offset from Base of allocated buffer // | . . . . . . . . . . . . | // +=============================+ <-- 2^n offset from Base of allocated buffer // | CPU 2 Save State | // +-----------------------------+ // | CPU 2 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU m+1 SMI Entry | // +=============================+ <-- Base of allocated buffer + 32 KB // | CPU 1 Save State | // +-----------------------------+ // | CPU 1 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU m SMI Entry | // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB // | CPU 0 Save State | // +-----------------------------+ // | CPU 0 Extra Data | // +-----------------------------+ // | Padding | // +-----------------------------+ // | CPU m-1 SMI Entry | // +=============================+ <-- 2^n offset from Base of allocated buffer // | . . . . . . . . . . . . | // +=============================+ <-- 2^n offset from Base of allocated buffer // | Padding | // +-----------------------------+ // | CPU 1 SMI Entry | // +=============================+ <-- 2^n offset from Base of allocated buffer // | Padding | // +-----------------------------+ // | CPU 0 SMI Entry | // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB https://review.coreboot.org/c/coreboot/+/41829/3/src/cpu/x86/smm/smm_module… PS3, Line 573: fxsave_area -= total_stack_size + fxsave_size; This calculation can place the location of the fxsave_area below the bottom of the TSEG. deleting the above line will place the fxsave_area above the stack. If you use base at this point for the location it will be below the MSEG + BIOS resource list -- To view, visit https://review.coreboot.org/c/coreboot/+/41829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd74c11ca42fb430f63711b5ec87d4bfe6ca2a Gerrit-Change-Number: 41829 Gerrit-PatchSet: 3 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 05 Jun 2020 20:46:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Refactor code to allow for additional CPUs
by Andrey Petrov (Code Review) 05 Jun '20

05 Jun '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39601 ) Change subject: soc/intel/xeon_sp: Refactor code to allow for additional CPUs ...................................................................... soc/intel/xeon_sp: Refactor code to allow for additional CPUs Refactor the code and split it into common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. Also, some minor cosmetic clean-ups like include reordering. Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/dsdt.asl M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc R src/soc/intel/xeon_sp/bootblock.c M src/soc/intel/xeon_sp/include/soc/iomap.h M src/soc/intel/xeon_sp/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/skx/Kconfig A src/soc/intel/xeon_sp/skx/Makefile.inc R src/soc/intel/xeon_sp/skx/acpi.c R src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl R src/soc/intel/xeon_sp/skx/acpi/iiostack.asl R src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl R src/soc/intel/xeon_sp/skx/acpi/uncore.asl R src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl R src/soc/intel/xeon_sp/skx/chip.c R src/soc/intel/xeon_sp/skx/chip.h R src/soc/intel/xeon_sp/skx/cpu.c R src/soc/intel/xeon_sp/skx/hob_display.c R src/soc/intel/xeon_sp/skx/include/soc/acpi.h R src/soc/intel/xeon_sp/skx/include/soc/cpu.h R src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h R src/soc/intel/xeon_sp/skx/include/soc/irq.h R src/soc/intel/xeon_sp/skx/include/soc/msr.h R src/soc/intel/xeon_sp/skx/include/soc/nvs.h R src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h R src/soc/intel/xeon_sp/skx/include/soc/pm.h R src/soc/intel/xeon_sp/skx/include/soc/pmc.h R src/soc/intel/xeon_sp/skx/include/soc/ramstage.h R src/soc/intel/xeon_sp/skx/include/soc/soc_util.h R src/soc/intel/xeon_sp/skx/lpc.c A src/soc/intel/xeon_sp/skx/romstage.c R src/soc/intel/xeon_sp/skx/soc_util.c R src/soc/intel/xeon_sp/skx/spi.c R src/soc/intel/xeon_sp/skx/upd_display.c M src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/util.c 41 files changed, 344 insertions(+), 222 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39601/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 87e2760..d6b4459 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -21,9 +21,8 @@ def_bool y select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES - select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 - select FSP_CAR + select SOC_INTEL_SKYLAKE_SP config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 46311d9..902ea80 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip soc/intel/xeon_sp +chip soc/intel/xeon_sp/skx register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index aca6c4d..076457e 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -30,12 +30,12 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/xeon_sp/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> // Xeon-SP ACPI tables Scope (\_SB) { - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } } diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 94c0ac4..3dcb302 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -1,28 +1,17 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 - 2020 Intel Corporation -## Copyright (C) 2019 - 2020 Facebook Inc -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +source "src/soc/intel/xeon_sp/skx/Kconfig" -config SOC_INTEL_XEON_SP +config XEON_SP_COMMON_BASE bool + +config SOC_INTEL_SKYLAKE_SP + bool + select XEON_SP_COMMON_BASE help - Intel Xeon SP support + Intel Skylake-SP support -if SOC_INTEL_XEON_SP +if XEON_SP_COMMON_BASE -config CPU_SPECIFIC_OPTIONS +config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 @@ -69,11 +58,6 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" - config MAX_SOCKET int default 2 @@ -90,14 +74,6 @@ help This option allows you to select MMIO Base Address of sideband bus. -config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x200000 - config DCACHE_BSP_STACK_SIZE hex default 0x10000 @@ -106,14 +82,6 @@ hex default 0x80000000 -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - config C_ENV_BOOTBLOCK_SIZE hex default 0xC000 @@ -122,5 +90,4 @@ hex default 0x80000 - -endif ## SOC_INTEL_XEON_SP +endif diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 9ad3e77..a48a2f3 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -15,45 +15,15 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y) +ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx -bootblock-y += bootblock/bootblock.c -bootblock-y += spi.c - -postcar-y += soc_util.c -postcar-y += spi.c - -romstage-y += soc_util.c -romstage-y += reset.c -romstage-y += romstage.c -romstage-y += soc_util.c -romstage-y += spi.c -romstage-y += hob_display.c -romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c - -ramstage-y += soc_util.c -ramstage-y += uncore.c -ramstage-y += reset.c -ramstage-y += chip.c -ramstage-y += soc_util.c -ramstage-y += lpc.c -ramstage-y += cpu.c -ramstage-y += spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += hob_display.c +bootblock-y += bootblock.c +romstage-y += romstage.c reset.c util.c +ramstage-y += uncore.c reset.c util.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) -endif ## CONFIG_SOC_INTEL_XEON_SP +endif ## XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c similarity index 99% rename from src/soc/intel/xeon_sp/bootblock/bootblock.c rename to src/soc/intel/xeon_sp/bootblock.c index 482f5b5..96f55ac 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -15,11 +15,11 @@ */ #include <bootblock_common.h> +#include <console/console.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> -#include <console/console.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 7c825a4..066a2db 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -30,18 +28,18 @@ #define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_) // SPI BAR0 MMIO base address -#define SPI_BASE_ADDRESS 0xfe010000 -#define SPI_BASE_SIZE 0x1000 +#define SPI_BASE_ADDRESS 0xfe010000 +#define SPI_BASE_SIZE 0x1000 -#define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_ADDRESS 0x500 /* Video RAM */ -#define VGA_BASE_ADDRESS 0xa0000 -#define VGA_BASE_SIZE 0x20000 +#define VGA_BASE_ADDRESS 0xa0000 +#define VGA_BASE_SIZE 0x20000 /* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_ADDRESS 0xfed00000 -#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS #endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h index c679692..cf3e737 100644 --- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -17,7 +15,7 @@ #ifndef _PCR_IDS_H_ #define _PCR_IDS_H_ -#define PID_ITSS 0xC4 -#define PID_RTC 0xC3 +#define PID_ITSS 0xc4 +#define PID_RTC 0xc3 #endif /* _PCR_IDS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 623306f..fa70bcd 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 - 2020 Intel Corporation. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h new file mode 100644 index 0000000..dc63140 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XEON_SP_SOC_UTIL_H_ +#define _XEON_SP_SOC_UTIL_H_ + +#include <console/console.h> + +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); +void unlock_pam_regions(void); +void get_stack_busnos(uint32_t *bus); + +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) + +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +#endif diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index dc94dc6..bb86683 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -17,12 +17,11 @@ #include <arch/romstage.h> #include <cbmem.h> -#include <intelblocks/rtc.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <intelblocks/rtc.h> #include <soc/romstage.h> -#include <soc/soc_util.h> -#include "chip.h" +#include <soc/util.h> asmlinkage void car_stage_entry(void) { @@ -57,27 +56,3 @@ run_postcar_phase(&pcf); } - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) -{ -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const config_t *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - mupd->FspmUpdVersion = FSP_UPD_VERSION; - - // ErrorLevel - 0 (disable) to 8 (verbose) - m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; - m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; - - soc_memory_init_params(m_cfg); - - mainboard_memory_init_params(mupd); - - m_cfg->VTdConfig.VTdSupport = config->vtd_support; - m_cfg->VTdConfig.CoherencySupport = config->coherency_support; - m_cfg->VTdConfig.ATS = config->ats_support; -} diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig new file mode 100644 index 0000000..1ce5ea6 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -0,0 +1,81 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if SOC_INTEL_SKYLAKE_SP + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" + +config MAX_SOCKET + int + default 2 + +# For 2S config, the number of cpus could be as high as +# 2 threads * 20 cores * 2 sockets +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x200000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + +endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc new file mode 100644 index 0000000..144a5c7 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) + +subdirs-y += ../../../../cpu/intel/microcode +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/x86/lapic +subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/x86/cache +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm + +bootblock-y += spi.c + +postcar-y += soc_util.c +postcar-y += spi.c + +romstage-y += soc_util.c +romstage-y += romstage.c +romstage-y += soc_util.c +romstage-y += spi.c +romstage-y += hob_display.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + +ramstage-y += soc_util.c +ramstage-y += chip.c +ramstage-y += soc_util.c +ramstage-y += lpc.c +ramstage-y += cpu.c +ramstage-y += spi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-y += hob_display.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include + +endif ## CONFIG_SOC_INTEL_SKYLAKE_SP diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c similarity index 99% rename from src/soc/intel/xeon_sp/acpi.c rename to src/soc/intel/xeon_sp/skx/acpi.c index 37dd420..6f9987f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -881,7 +881,7 @@ acpi_slit_t *slit; acpi_dmar_t *dmar; - const struct soc_intel_xeon_sp_config *const config = config_of(device); + const struct soc_intel_xeon_sp_skx_config *const config = config_of(device); /* SRAT */ current = ALIGN(current, 8); diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/globalnvs.asl rename to src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/iiostack.asl rename to src/soc/intel/xeon_sp/skx/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/pci_irq.asl rename to src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/uncore.asl rename to src/soc/intel/xeon_sp/skx/acpi/uncore.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/uncore_irq.asl rename to src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/chip.c b/src/soc/intel/xeon_sp/skx/chip.c similarity index 99% rename from src/soc/intel/xeon_sp/chip.c rename to src/soc/intel/xeon_sp/skx/chip.c index 832f98e..228ec42 100644 --- a/src/soc/intel/xeon_sp/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -591,8 +591,8 @@ mainboard_silicon_init_params(silupd); } -struct chip_operations soc_intel_xeon_sp_ops = { - CHIP_NAME("Intel Xeon-SP SOC") +struct chip_operations soc_intel_xeon_sp_skx_ops = { + CHIP_NAME("Intel Skylake-SP") .enable_dev = soc_enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/skx/chip.h similarity index 95% rename from src/soc/intel/xeon_sp/chip.h rename to src/soc/intel/xeon_sp/skx/chip.h index 72f2445..de54fc0 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -23,7 +23,7 @@ #include <intelblocks/cfg.h> #include <soc/irq.h> -struct soc_intel_xeon_sp_config { +struct soc_intel_xeon_sp_skx_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; @@ -82,6 +82,6 @@ extern struct chip_operations soc_intel_xeon_sp_ops; -typedef struct soc_intel_xeon_sp_config config_t; +typedef struct soc_intel_xeon_sp_skx_config config_t; #endif diff --git a/src/soc/intel/xeon_sp/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c similarity index 100% rename from src/soc/intel/xeon_sp/cpu.c rename to src/soc/intel/xeon_sp/skx/cpu.c diff --git a/src/soc/intel/xeon_sp/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c similarity index 99% rename from src/soc/intel/xeon_sp/hob_display.c rename to src/soc/intel/xeon_sp/skx/hob_display.c index 1508011..65b54a6 100644 --- a/src/soc/intel/xeon_sp/hob_display.c +++ b/src/soc/intel/xeon_sp/skx/hob_display.c @@ -15,12 +15,12 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <console/console.h> #include <fsp/util.h> -#include <lib.h> -#include <assert.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <lib.h> static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/acpi.h rename to src/soc/intel/xeon_sp/skx/include/soc/acpi.h diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/cpu.h rename to src/soc/intel/xeon_sp/skx/include/soc/cpu.h diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h rename to src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/skx/include/soc/irq.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/irq.h rename to src/soc/intel/xeon_sp/skx/include/soc/irq.h diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/msr.h rename to src/soc/intel/xeon_sp/skx/include/soc/msr.h diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/nvs.h rename to src/soc/intel/xeon_sp/skx/include/soc/nvs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pci_devs.h rename to src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/skx/include/soc/pm.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pm.h rename to src/soc/intel/xeon_sp/skx/include/soc/pm.h diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/skx/include/soc/pmc.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pmc.h rename to src/soc/intel/xeon_sp/skx/include/soc/pmc.h diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/skx/include/soc/ramstage.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/ramstage.h rename to src/soc/intel/xeon_sp/skx/include/soc/ramstage.h diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h similarity index 60% rename from src/soc/intel/xeon_sp/include/soc/soc_util.h rename to src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 8b5e1a2..735581a 100644 --- a/src/soc/intel/xeon_sp/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -21,31 +21,7 @@ #include <hob_iiouds.h> #include <hob_memmap.h> #include <arch/acpi.h> - -#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size_kb: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ - (base_kb << 10) + (size_kb << 10) - 1, size_kb) - -#define LOG_IO_RESOURCE(type, dev, index, base, size) \ - printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ - "end: 0x%llx, size: 0x%llx\n", \ - __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) - -#define DEV_FUNC_ENTER(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ - __FILE__, __func__, __LINE__, dev_path(dev)) - -#define DEV_FUNC_EXIT(dev) \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ - __func__, __LINE__, dev_path(dev)) - -#define FUNC_ENTER() \ - printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) - -#define FUNC_EXIT() \ - printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) +#include <soc/util.h> struct iiostack_resource { uint8_t no_of_stacks; @@ -59,8 +35,6 @@ uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); -void get_stack_busnos(uint32_t *bus); -void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); void get_iiostack_info(struct iiostack_resource *info); @@ -72,7 +46,6 @@ void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); -void unlock_pam_regions(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/skx/lpc.c similarity index 100% rename from src/soc/intel/xeon_sp/lpc.c rename to src/soc/intel/xeon_sp/skx/lpc.c diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c new file mode 100644 index 0000000..a98fd07 --- /dev/null +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <intelblocks/rtc.h> +#include <soc/romstage.h> +#include <soc/soc_util.h> + +#include "chip.h" + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + mupd->FspmUpdVersion = FSP_UPD_VERSION; + + // ErrorLevel - 0 (disable) to 8 (verbose) + m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + + mainboard_memory_init_params(mupd); + + m_cfg->VTdConfig.VTdSupport = config->vtd_support; + m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + m_cfg->VTdConfig.ATS = config->ats_support; +} diff --git a/src/soc/intel/xeon_sp/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c similarity index 90% rename from src/soc/intel/xeon_sp/soc_util.c rename to src/soc/intel/xeon_sp/skx/soc_util.c index 6310bac..f6b581b 100644 --- a/src/soc/intel/xeon_sp/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -18,20 +18,17 @@ #include <assert.h> #include <commonlib/sort.h> #include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> #include <delay.h> #include <device/pci.h> -#include <hob_iiouds.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcr.h> -#include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_util.h> -#include <stdlib.h> +#include <soc/util.h> #include <timer.h> /* @@ -71,24 +68,6 @@ return addr; } -/* - * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh) - * TODO: D0h - */ -void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) -{ - uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, - UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); - if (bus0) - *bus0 = (bus & 0xff); - if (bus1) - *bus1 = (bus >> 8) & 0xff; - if (bus2) - *bus2 = (bus >> 16) & 0xff; - if (bus3) - *bus3 = (bus >> 24) & 0xff; -} - uint32_t top_of_32bit_ram(void) { uintptr_t mmcfg, tolm; @@ -155,42 +134,6 @@ return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; } -/* bus needs to be of size 6 (MAX_IIO_STACK) */ -void get_stack_busnos(uint32_t *bus) -{ - uint32_t reg1, reg2; - - reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xcc); - reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xd0); - - for (int i = 0; i < 4; ++i) - bus[i] = ((reg1 >> (i * 8)) & 0xff); - for (int i = 0; i < 2; ++i) - bus[4+i] = ((reg2 >> (i * 8)) & 0xff); -} - -void unlock_pam_regions(void) -{ - uint32_t bus1 = 0; - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - - get_cpubusnos(NULL, &bus1, NULL, NULL); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} - /* return 1 if command timed out else 0 */ static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, uint32_t target) diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/skx/spi.c similarity index 100% rename from src/soc/intel/xeon_sp/spi.c rename to src/soc/intel/xeon_sp/skx/spi.c diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c similarity index 100% rename from src/soc/intel/xeon_sp/upd_display.c rename to src/soc/intel/xeon_sp/skx/upd_display.c diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index adf3e3e..ebdd3d7 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -20,10 +20,13 @@ #include <cpu/x86/lapic.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <soc/soc_util.h> +#include <soc/util.h> struct map_entry { uint32_t reg; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c new file mode 100644 index 0000000..6f1e28d --- /dev/null +++ b/src/soc/intel/xeon_sp/util.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <soc/pci_devs.h> +#include <soc/util.h> + +void get_stack_busnos(uint32_t *bus) +{ + uint32_t reg1, reg2; + + reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xcc); + reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xd0); + + for (int i = 0; i < 4; ++i) + bus[i] = ((reg1 >> (i * 8)) & 0xff); + for (int i = 0; i < 2; ++i) + bus[4+i] = ((reg2 >> (i * 8)) & 0xff); +} + +void unlock_pam_regions(void) +{ + uint32_t bus1 = 0; + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + + get_cpubusnos(NULL, &bus1, NULL, NULL); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) +{ + uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, + UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); + if (bus0) + *bus0 = (bus & 0xff); + if (bus1) + *bus1 = (bus >> 8) & 0xff; + if (bus2) + *bus2 = (bus >> 16) & 0xff; + if (bus3) + *bus3 = (bus >> 24) & 0xff; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Gerrit-Change-Number: 39601 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by Angel Pons (Code Review) 05 Jun '20

05 Jun '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... Patch Set 49: Code-Review+1 (22 comments) https://review.coreboot.org/c/coreboot/+/37441/49/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md: https://review.coreboot.org/c/coreboot/+/37441/49/Documentation/mainboard/s… PS49, Line 19: - Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) Any consequences? Crippling the ME firmware usually breaks things. https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/Kconfig: PS49: No license header https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 6: # select HAVE_ACPI_RESUME Hmm? https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 22: Supermicro_X11_LGA1151V2_SERIES This doesn't need underscores https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 39: : config MAINBOARD_VENDOR : string : default "Supermicro" Not needed (if it is, then check src/mainboard/supermicro/Kconfig) https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 56: config CONSOLE_POST : bool : default n Isn't this default already? https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/acpi_tables.c: PS49: I think this file is no longer required https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 28: garbeled garbled https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: PS49: No license header https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 10: device pci 02.0 on end # Integrated Graphics Device Is it really on? https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 11: device pci 04.0 on end # SA Thermal device : device pci 04.0 on end # Intel Xeon E3 Um, this is duplicated https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 62: empty line https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 13: // Some generic macros Please drop this comment https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 19: Scope (\_SB) { : Device (PCI0) Device (\_SB.PCI0) https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 27: // Chipset specific sleep states Not chipset specific, this should also be dropped https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/memory.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 29: /* : * Baseboard Rcomp target values. : */ This fits in a single line https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 44: const struct cnl_mb_cfg * variant_memcfg_config(void) > "foo * bar" should be "foo *bar" Should be fixed https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 10: size_t num = 0; > please, no spaces at the start of a line Please fix the indentation https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 18: params->PchHdaVcType = 0x1; Make this common then? https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/gpio.h: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 3: PCH_GPIO_H Um, not PCH? https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 15: Do we need so many spaces? https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 68: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" I think we can drop one tab here -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 49 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-Comment-Date: Fri, 05 Jun 2020 14:55:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by build bot (Jenkins) (Code Review) 05 Jun '20

05 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... Patch Set 49: (5 comments) https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 18: const struct pad_config * early_gpio_table = get_early_gpio_table(&num); "foo * bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/memory.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 44: const struct cnl_mb_cfg * variant_memcfg_config(void) "foo * bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c: https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 10: size_t num = 0; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 11: const struct pad_config * gpio_table = get_gpio_table(&num); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37441/49/src/mainboard/supermicro/… PS49, Line 11: const struct pad_config * gpio_table = get_gpio_table(&num); "foo * bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 49 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-Comment-Date: Fri, 05 Jun 2020 14:26:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by Christian Walter (Code Review) 05 Jun '20

05 Jun '20

Hello wouter.eckhardt(a)prodrive-technologies.com, Philipp Deppenwiese, build bot (Jenkins), Guido Beyer @ Prodrive Technologies, Justin van Son, Nico Huber, Patrick Georgi, Martin Roth, Patrick Rudolph, Patrick Rudolph, Stef van Os, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37441 to look at the new patch set (#49). Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F This commit adds initial support for the Supermicro X11SCH-F. What is working: * Aspeed AST2500 Graphics Output * Serial Console * SuperIO DevTree Config * Boots into Linux * SATA Slots * USB Slots * IPMI KCS * LinuxBoot * Proper ACPI Tables * Windows Support * TPM Support (w/ patched IFD) - Patch IFD at 0x235=03 and 0x13E=84 Tested with Intel Xeon E-2186G and 64 GB ECC RAM. Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/acpi_tables.c A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/memory.c A src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 21 files changed, 1,027 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/49 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 49 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F
by build bot (Jenkins) (Code Review) 05 Jun '20

05 Jun '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: src/mainboard/supermicro/x11-lga1151v2-series: Add Support for X11SCH-F ...................................................................... Patch Set 48: (6 comments) https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c: https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… PS48, Line 18: const struct pad_config * early_gpio_table = get_early_gpio_table(&num); "foo * bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/memory.c: https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… PS48, Line 44: const struct cnl_mb_cfg * variant_memcfg_config(void) "foo * bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c: https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… PS48, Line 10: size_t num = 0; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… PS48, Line 11: const struct pad_config * gpio_table = get_gpio_table(&num); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… PS48, Line 11: const struct pad_config * gpio_table = get_gpio_table(&num); "foo * bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/variants.h: https://review.coreboot.org/c/coreboot/+/37441/48/src/mainboard/supermicro/… PS48, Line 6: const struct cnl_mb_cfg *variant_memcfg_config(void); adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 48 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Jun 2020 14:15:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add FSP 2.2 specific support
by Angel Pons (Code Review) 05 Jun '20

05 Jun '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41728 ) Change subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support ...................................................................... Patch Set 11: (4 comments) https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… PS11, Line 27: impacts impact https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… PS11, Line 33: size_t multi_phase_si_init_entry_offset; Doesn't this make the struct layout incompatible with FSP 2.1? https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… PS11, Line 36: uint32_t phase_index Are these phase indices enumerated? If so, I'd use an enum for this https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/41728/11/src/drivers/intel/fsp2_0/… PS11, Line 57: BIOS_SPEW BIOS_EMERG Or just have a single line: die_with_post_code(postcode, "FspSiliconInit returned with error 0x%08x\n", status); -- To view, visit https://review.coreboot.org/c/coreboot/+/41728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Gerrit-Change-Number: 41728 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 05 Jun 2020 12:59:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/ipmi: drop redundant option `wait_for_bmc`
by Angel Pons (Code Review) 05 Jun '20

05 Jun '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42020 ) Change subject: drivers/ipmi: drop redundant option `wait_for_bmc` ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/42020/2/src/drivers/ipmi/ipmi_kcs_… File src/drivers/ipmi/ipmi_kcs_ops.c: https://review.coreboot.org/c/coreboot/+/42020/2/src/drivers/ipmi/ipmi_kcs_… PS2, Line 87: Get IPMI version for ACPI and SMBIOS > that comment is a lie \o/ we don't get *anything* here This block is actually checking if the BMC is alive, or that is what it looks like... https://review.coreboot.org/c/coreboot/+/42020/2/src/drivers/ipmi/ipmi_kcs_… PS2, Line 107: retry_count < conf->bmc_boot_timeout > Comparing u8 < u16 is a potential endless loop. Yes, should we change retry_count or bmc_boot_timeout's type? -- To view, visit https://review.coreboot.org/c/coreboot/+/42020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26f85e82a13f53a3731ab88035f2ae4bbffac00 Gerrit-Change-Number: 42020 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Comment-Date: Fri, 05 Jun 2020 12:28:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/ipmi: drop redundant option `wait_for_bmc`
by Michael Niewöhner (Code Review) 05 Jun '20

05 Jun '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42020 ) Change subject: drivers/ipmi: drop redundant option `wait_for_bmc` ...................................................................... Patch Set 2: Code-Review-1 (1 comment) this needs great rework..... https://review.coreboot.org/c/coreboot/+/42020/2/src/drivers/ipmi/ipmi_kcs_… File src/drivers/ipmi/ipmi_kcs_ops.c: https://review.coreboot.org/c/coreboot/+/42020/2/src/drivers/ipmi/ipmi_kcs_… PS2, Line 87: Get IPMI version for ACPI and SMBIOS that comment is a lie \o/ we don't get *anything* here -- To view, visit https://review.coreboot.org/c/coreboot/+/42020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26f85e82a13f53a3731ab88035f2ae4bbffac00 Gerrit-Change-Number: 42020 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Comment-Date: Fri, 05 Jun 2020 12:18:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2020