coreboot-gerrit June 2020

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Change in coreboot[master]: lp4x: Add two new parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41989 ) Change subject: lp4x: Add two new parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR ...................................................................... lp4x: Add two new parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR This change adds two parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR to global_lp4x_mem_parts.json.txt and generates SPD files for TGL and JSL for these parts. BUG=b:157862308 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt 3 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/41989/1 diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt index 67f9669..a5e19bf 100644 --- a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt +++ b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt @@ -7,3 +7,5 @@ MT53E1G64D4SQ-046 WT:A,spd-7.hex MT53E512M32D2NP-046 WT:F,spd-8.hex NT6AP256T32AV-J2,spd-9.hex +K4U6E3S4AA-MGCR,spd-3.hex +MT53E512M32D2NP-046 WT:E,spd-8.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt index 37d04ee..2d554c5 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt @@ -7,3 +7,5 @@ MT53E1G64D4SQ-046 WT:A,spd-6.hex MT53E512M32D2NP-046 WT:F,spd-7.hex NT6AP256T32AV-J2,spd-8.hex +K4U6E3S4AA-MGCR,spd-1.hex +MT53E512M32D2NP-046 WT:E,spd-7.hex diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt index a9c13b0..7d82be7 100644 --- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt @@ -109,6 +109,30 @@ "tckMaxPs": 1250, "casLatencies": "14 20 24 28 32" } - } + }, + { + "name": "K4U6E3S4AA-MGCR", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 1, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "MT53E512M32D2NP-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 1, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/41989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Gerrit-Change-Number: 41989 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using ...
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41617 ) Change subject: mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using gen_part_id.go ...................................................................... mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by volteer and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x05 As per datasheet, this is a single die device. So, value should be 0x05. 19 0x00 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Part: K4UBE3D4AA-MGCL Byte# Current New Explanation 6 0xB5 0x95 As per datasheet, this is a dual die device. So, value should be 0x95. 19 0x00 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. Part: H9HCNNNBKMMLXR-NEE Byte# Current New Explanation 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: H9HCNNNFAMMLXR-NEE Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G32D2NP-046 WT:A Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB5 0x95 As per datasheet, this is a dual die device. So, value should be 0x95. 12 0x0A 0x02 As per datasheet, this is 1rank and 16-bit wide channel. So, value should be 0x02. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to 380ns in MTB units which is 0x0BE0. 31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to 190ns in MTB units which is 0x05F0. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc A src/mainboard/google/volteer/variants/volteer/memory/mem_list_variant.txt 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/41617/1 diff --git a/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc new file mode 100644 index 0000000..5a06dd6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +SPD_SOURCES = +SPD_SOURCES += spd-3.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL +SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += spd-1.hex # ID = 2(0b0010) Parts = H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += spd-5.hex # ID = 4(0b0100) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/volteer/variants/volteer/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/volteer/memory/mem_list_variant.txt new file mode 100644 index 0000000..fc84614 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +K4U6E3S4AA-MGCL +K4UBE3D4AA-MGCL +H9HCNNNBKMMLXR-NEE +H9HCNNNFAMMLXR-NEE +MT53E1G32D2NP-046 WT:A -- To view, visit https://review.coreboot.org/c/coreboot/+/41617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe Gerrit-Change-Number: 41617 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: src: Use pci_dev_ops_pci where applicable
by Angel Pons (Code Review) 07 Jun '20

07 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41944 ) Change subject: src: Use pci_dev_ops_pci where applicable ...................................................................... src: Use pci_dev_ops_pci where applicable Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/drivers/generic/bayhub/bh720.c M src/drivers/intel/wifi/wifi.c M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/pi/00630F01/iommu.c M src/northbridge/amd/pi/00730F01/iommu.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/gma.c M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/usb.c M src/soc/amd/stoneyridge/usb.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/braswell/pcie.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/ide.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/ide.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/pci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_xhci.c 87 files changed, 89 insertions(+), 435 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/41944/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index dca4e0a..1e0cf2f 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -241,14 +241,10 @@ } } -struct pci_operations azalia_audio_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - struct device_operations default_azalia_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_audio_init, - .ops_pci = &azalia_audio_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 98193b0..cdac9fe 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -46,15 +46,11 @@ board_bh720(dev); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations bh720_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, .init = bh720_init, }; diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 2dd3543..9fcd7ba 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -73,10 +73,6 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -85,7 +81,7 @@ #if CONFIG(GENERATE_SMBIOS_TABLES) .get_smbios_data = smbios_write_wifi, #endif - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = generic_wifi_acpi_name, .acpi_fill_ssdt = intel_wifi_fill_ssdt, diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index a7adfee..7af6538 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -36,15 +36,11 @@ pci_write_config32(dev, 0x44, res->base | (1 << 0)); } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver iommu_driver __pci_driver = { diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c index 08486cc..0902243 100644 --- a/src/northbridge/amd/pi/00630F01/iommu.c +++ b/src/northbridge/amd/pi/00630F01/iommu.c @@ -36,15 +36,11 @@ pci_write_config32(dev, 0x44, res->base | (1 << 0)); } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver iommu_driver __pci_driver = { diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index fa0932a..ef478dd 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -26,15 +26,11 @@ pci_dev_set_resources(dev); } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver iommu_driver __pci_driver = { diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index ee6ec5a..fc771b3 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -61,15 +61,11 @@ assign_resources(dev->link_list); } -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .scan_bus = pci_domain_scan_bus, - .ops_pci = &intel_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static void cpu_bus_init(struct device *dev) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 6a51dae..3d48ca2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -200,17 +200,13 @@ return "GFX0"; } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = gma_acpi_name, }; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 19341d4..68072ff 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -502,17 +502,13 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index f8a16e2..71ca1e6 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -85,16 +85,12 @@ } } -static struct pci_operations minihd_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations minihd_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = minihd_init, - .ops_pci = &minihd_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a728e0e..7d105da 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -448,17 +448,13 @@ MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &intel_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short mc_pci_device_ids[] = { diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index 74f11dd..a47a2f5 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -47,10 +47,6 @@ } #endif -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -59,7 +55,7 @@ .reset_bus = pci_bus_reset, .disable = pcie_disable, .init = pci_dev_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, #endif diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 183c8f5..34d129d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -746,10 +746,6 @@ return "GFX0"; } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = gma_func0_read_resources, .set_resources = pci_dev_set_resources, @@ -757,7 +753,7 @@ .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, .disable = gma_func0_disable, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = gma_acpi_name, }; @@ -767,7 +763,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func1_init, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short i945_gma_func0_ids[] = { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 56cad7a..0e8ea7e 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -174,16 +174,12 @@ } } -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &intel_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 5ccf8a6..8baccb2 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -191,17 +191,13 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index d98af9e..f53b03e 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -227,17 +227,13 @@ } -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &intel_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver mc_driver_ard __pci_driver = { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 2f4b629..e46bd7c 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -263,16 +263,12 @@ return "GFX0"; } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = gma_acpi_name, }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 150b61c..aa66f4a 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -646,10 +646,6 @@ dev->enabled = 0; } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -657,7 +653,7 @@ .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, .disable = gma_func0_disable, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = gma_acpi_name, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ce28c05..1d20a4b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -425,16 +425,12 @@ pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); } -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .ops_pci = &intel_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_fill_ssdt = generate_cpu_entries, }; diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index f2b75d6..d0b7fd5 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -50,10 +50,6 @@ } #endif -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -62,7 +58,7 @@ .reset_bus = pci_bus_reset, .disable = pcie_disable, .init = pci_dev_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, #endif diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index ecbd63e..d2d2bb0 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -67,17 +67,13 @@ return "GFX0"; } -static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .ops_pci = &gma_pci_ops, + .ops_pci = &pci_dev_ops_pci, .disable = gma_func0_disable, .acpi_name = gma_acpi_name, }; diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index bf0b600..c870972 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -21,15 +21,11 @@ res->flags = IORESOURCE_MEM; } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 2f37a91..c7e5e1e 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -71,16 +71,13 @@ .write_byte = lsmbus_write_byte, }; -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; static struct device_operations smbus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver smbus_driver __pci_driver = { diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index e0b369d..cbe5d86 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -41,15 +41,11 @@ sb_clk_output_48Mhz(); /* Internal connection to I2S */ } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations acp_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = enable, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver acp_driver __pci_driver = { diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index a507956..7b8c18c 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -18,10 +18,6 @@ printk(BIOS_DEBUG, "%s\n", __func__); } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -29,7 +25,7 @@ .init = picasso_usb_init, .scan_bus = scan_static_bus, .acpi_name = soc_acpi_name, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 921823a..c83f1e1 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -41,10 +41,6 @@ return -1; } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations usb_ops = { .read_resources = pci_ehci_read_resources, .set_resources = pci_dev_set_resources, @@ -52,7 +48,7 @@ .init = set_usb_over_current, .scan_bus = scan_static_bus, .acpi_name = soc_acpi_name, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index bac8d58..c257ce0 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -227,10 +227,6 @@ do_pci_scan_bridge(dev, pciexp_scan_bus); } -static struct pci_operations pcie_root_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -238,7 +234,7 @@ .init = byt_pcie_init, .scan_bus = byt_pciexp_scan_bridge, .enable = byt_pcie_enable, - .ops_pci = &pcie_root_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index d8e423b..c0cf5e4 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -142,10 +142,6 @@ southcluster_enable_dev(dev); } -static struct pci_operations pcie_root_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -153,7 +149,7 @@ .init = pcie_init, .scan_bus = pciexp_scan_bridge, .enable = pcie_enable, - .ops_pci = &pcie_root_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 094da2a..a15b045 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -10,16 +10,12 @@ { } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver hdaaudio_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index 3b18bd4..8ba7a12 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -9,16 +9,12 @@ { } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver ide_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 8a1f250..89c9a6b 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -333,10 +333,6 @@ } } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, @@ -347,7 +343,7 @@ .init = lpc_init, .final = lpc_final, .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, .acpi_name = lpc_acpi_name, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 9f14908..b8511fa 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -130,16 +130,13 @@ { } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; static struct device_operations smbus_ops = { .read_resources = hudson_sm_read_resources, .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver smbus_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index ff691cf..1175f08 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -6,10 +6,6 @@ #include <device/pci_ehci.h> #include "hudson.h" -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void usb_init(struct device *dev) { } @@ -19,7 +15,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver usb_0_driver __pci_driver = { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 1cf3ae8..e3ba4a5 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -102,10 +102,6 @@ printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); @@ -154,7 +150,7 @@ #endif .init = lpc_init, .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 3c98c66..f11eee5 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -16,16 +16,12 @@ { } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver hdaaudio_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index 3b18bd4..8ba7a12 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -9,16 +9,12 @@ { } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver ide_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index ebc9de5..c884f20 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -349,10 +349,6 @@ } } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, @@ -363,7 +359,7 @@ .init = lpc_init, .final = lpc_final, .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index ee30b7f..cba2d80 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -95,16 +95,13 @@ { } -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; static struct device_operations smbus_ops = { .read_resources = hudson_sm_read_resources, .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver smbus_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index 3318349..fecae74 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -6,10 +6,6 @@ #include <device/pci_ehci.h> #include "hudson.h" -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void usb_init(struct device *dev) { } @@ -19,7 +15,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 0b460d9b..2ed88c2 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -323,16 +323,12 @@ return "HDEF"; } -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .ops_pci = &azalia_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = azalia_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 55e2573..89327b4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -861,10 +861,6 @@ memcpy(spi_config, &config->spi, sizeof(*spi_config)); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -877,7 +873,7 @@ .final = lpc_final, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index e1a1edc..9557094 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -711,16 +711,12 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver intel_me __pci_driver = { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 56303e1..79e542b 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -669,16 +669,12 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver intel_me __pci_driver = { diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 6b36a4b..e61c60c 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -44,17 +44,13 @@ pci_write_config16(dev, SECSTS, reg16); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver pch_pci __pci_driver = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 15c79ba..c32738e 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -294,10 +294,6 @@ return NULL; } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -306,7 +302,7 @@ .enable = pch_pcie_enable, .scan_bus = pch_pciexp_scan_bridge, .acpi_name = pch_pcie_acpi_name, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 27b4d16..1974e2b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -279,10 +279,6 @@ generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); } -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations sata_ops = { .read_resources = sata_read_resources, .set_resources = sata_set_resources, @@ -290,7 +286,7 @@ .acpi_fill_ssdt = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, - .ops_pci = &sata_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = sata_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 6e5be9b..1b72ea5 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -56,10 +56,6 @@ .write_byte = lsmbus_write_byte, }; -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); @@ -85,7 +81,7 @@ .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = smbus_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index db925e0..5a5b418 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -43,16 +43,12 @@ return "XHC"; } -static struct pci_operations xhci_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations usb_xhci_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, - .ops_pci = &xhci_pci_ops, + .ops_pci = &pci_dev_ops_pci, .acpi_name = xhci_acpi_name, }; diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 67426c7..cc6e376 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -234,17 +234,13 @@ } } -static struct pci_operations ac97_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations ac97_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ac97_audio_init, .enable = i82801gx_enable, - .ops_pci = &ac97_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static struct device_operations ac97_modem_ops = { @@ -253,7 +249,7 @@ .enable_resources = pci_dev_enable_resources, .init = ac97_modem_init, .enable = i82801gx_enable, - .ops_pci = &ac97_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index f835e68..205fb0d 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -282,17 +282,13 @@ } } -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, .enable = i82801gx_enable, - .ops_pci = &azalia_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 5c4c96d..7fb489d 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -78,17 +78,13 @@ printk(BIOS_DEBUG, "\n"); } -static struct pci_operations ide_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, .enable = i82801gx_enable, - .ops_pci = &ide_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7e2b5a7..5bbb8e4 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -651,10 +651,6 @@ intel_acpi_gen_def_acpi_pirq(device); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -666,7 +662,7 @@ .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, .final = lpc_final, }; diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index f75e3fc..7472438 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -42,17 +42,13 @@ pci_write_config16(dev, SECSTS, reg16); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* Desktop */ diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 7a49e52..adf0e49 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -232,10 +232,6 @@ root_port_commit_config(dev); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -243,7 +239,7 @@ .init = pci_init, .enable = ich_pcie_enable, .scan_bus = pci_scan_bridge, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short i82801gx_pcie_ids[] = { diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index bca0251..c98a645 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -211,17 +211,13 @@ pci_write_config32(dev, SATA_IR, reg32); } -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = i82801gx_enable, - .ops_pci = &sata_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short sata_ids[] = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 88b6e13..e1e53c2 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -65,10 +65,6 @@ .block_write = lsmbus_block_write, }; -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); @@ -86,7 +82,7 @@ .scan_bus = scan_smbus, .enable = i82801gx_enable, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 6689fb8..8ce57df 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -27,17 +27,13 @@ printk(BIOS_DEBUG, "done.\n"); } -static struct pci_operations usb_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, .enable = i82801gx_enable, - .ops_pci = &usb_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7..0d9a7be 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -57,17 +57,13 @@ pci_write_config8(dev, 0x80, access_cntl); } -static struct pci_operations lops_pci = { - .set_subsystem = &usb_ehci_set_subsystem, -}; - static struct device_operations usb_ehci_ops = { .read_resources = pci_ehci_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, .enable = i82801gx_enable, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */ diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index b78cdd5..5eb907e 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -272,16 +272,12 @@ } } -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .ops_pci = &azalia_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 37f9852..855d7cc 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -502,10 +502,6 @@ intel_acpi_gen_def_acpi_pirq(device); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = i82801ix_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -516,7 +512,7 @@ .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c index e558f2f..fff58fe 100644 --- a/src/southbridge/intel/i82801ix/pci.c +++ b/src/southbridge/intel/i82801ix/pci.c @@ -30,10 +30,6 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -41,7 +37,7 @@ .init = pci_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a10f35f..c5c332c 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -91,17 +91,13 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pch_pciexp_scan_bridge, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 834ed86..390c677 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -247,17 +247,13 @@ pci_write_config16(dev, 0x90, map); } -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .ops_pci = &sata_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 6ae62c1..6d69226 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -50,10 +50,6 @@ .write_byte = lsmbus_write_byte, }; -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); @@ -74,7 +70,7 @@ .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver pch_smbus __pci_driver = { diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 83a1583..810da90 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -36,16 +36,12 @@ pci_write_config32(dev, 0x10, 0); } -static struct pci_operations thermal_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .ops_pci = &thermal_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver ich9_thermal __pci_driver = { diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 2a0182f..dc4c82e 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -272,16 +272,12 @@ } } -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .ops_pci = &azalia_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ae98fdd..2b526d8 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -660,10 +660,6 @@ intel_acpi_gen_def_acpi_pirq(device); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = i82801jx_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -674,7 +670,7 @@ .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c index 6789437..020ecde 100644 --- a/src/southbridge/intel/i82801jx/pci.c +++ b/src/southbridge/intel/i82801jx/pci.c @@ -30,10 +30,6 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -41,7 +37,7 @@ .init = pci_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index f29e576..3817d88 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -91,17 +91,13 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pch_pciexp_scan_bridge, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; /* 82801lJx, ICH10 */ diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index a1e762f..b79b2be 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -241,17 +241,13 @@ pci_write_config16(dev, 0x90, map); } -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .ops_pci = &sata_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 7ebd99f..4f45d8a 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -77,10 +77,6 @@ .block_write = lsmbus_block_write, }; -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); @@ -101,7 +97,7 @@ .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 9dd7067..70a9838 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -36,16 +36,12 @@ pci_write_config32(dev, 0x10, 0); } -static struct pci_operations thermal_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .ops_pci = &thermal_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 2fdb073..59a384a 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -297,16 +297,12 @@ pci_write_config8(dev, 0x43, reg8); } -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .ops_pci = &azalia_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 54b2621..8a555be 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -737,10 +737,6 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -753,7 +749,7 @@ .final = lpc_final, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 3d8a84e..2c9c87c 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -590,16 +590,12 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 4343830..357ad5f 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -217,10 +217,6 @@ generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); } -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -228,7 +224,7 @@ .init = sata_init, .enable = sata_enable, .acpi_fill_ssdt = sata_fill_ssdt, - .ops_pci = &sata_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index a4cdbd2..7e9aa57 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -56,10 +56,6 @@ .write_byte = lsmbus_write_byte, }; -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); @@ -80,7 +76,7 @@ .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index a1e6b0b..0b496da 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -30,16 +30,12 @@ printk(BIOS_DEBUG, "Thermal init done.\n"); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations thermal_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver pch_thermal __pci_driver = { diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 7ad9929..6237598 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -66,17 +66,12 @@ pci_write_config8(dev, 0x80, access_cntl); } - -static struct pci_operations lops_pci = { - .set_subsystem = &usb_ehci_set_subsystem, -}; - static struct device_operations usb_ehci_ops = { .read_resources = pci_ehci_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 4122dbb..f415170 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -137,16 +137,12 @@ } } -static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .ops_pci = &azalia_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { 0x8c20, 0x9c20, 0 }; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a..6664c4f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -926,10 +926,6 @@ outb(APM_CNT_FINALIZE, APM_CNT); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -942,7 +938,7 @@ .final = lpc_final, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 8914edf..5c07262 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -848,10 +848,6 @@ */ } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void intel_me_enable(struct device *dev) { /* Avoid talking to the device in S3 path */ @@ -867,7 +863,7 @@ .enable_resources = pci_dev_enable_resources, .enable = intel_me_enable, .init = intel_me_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index e11a0b7..d957e8d 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -708,10 +708,6 @@ root_port_commit_config(); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -719,7 +715,7 @@ .init = pci_init, .enable = pch_pcie_enable, .scan_bus = pciexp_scan_bridge, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ab96d62..47e6f9b 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -310,17 +310,13 @@ pci_write_config16(dev, 0x90, map); } -static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .ops_pci = &sata_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index e093508..e7f2596 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -220,16 +220,12 @@ } } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = serialio_init, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index e78d85d..39003f6 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -55,10 +55,6 @@ .write_byte = lsmbus_write_byte, }; -static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); @@ -79,7 +75,7 @@ .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &smbus_pci_ops, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 49a6cfc..8684aa9 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -360,16 +360,12 @@ } } -static struct pci_operations lops_pci = { - .set_subsystem = &pci_dev_set_subsystem, -}; - static struct device_operations usb_xhci_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, - .ops_pci = &lops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Gerrit-Change-Number: 41944 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/google/volteer: Drop spd/ folders from variants/
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41619 ) Change subject: mb/google/volteer: Drop spd/ folders from variants/ ...................................................................... mb/google/volteer: Drop spd/ folders from variants/ Now that volteer is moved to using the auto-generated SPDs, we no longer need the spd/ folder under each variant. Hence, this change drops the spd/ folders and the SPD files within them. Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex D src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex D src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex D src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex D src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex D src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex D src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex D src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex D src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex 9 files changed, 0 insertions(+), 288 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41619/1 diff --git a/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex deleted file mode 100644 index 921ecf8..0000000 --- a/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 16 21 B9 08 00 00 00 00 02 01 00 00 -00 00 04 0F 92 54 05 00 87 00 90 A8 90 E0 0B F0 -05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex deleted file mode 100644 index 921ecf8..0000000 --- a/src/mainboard/google/volteer/variants/halvor/spd/SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 16 21 B9 08 00 00 00 00 02 01 00 00 -00 00 04 0F 92 54 05 00 87 00 90 A8 90 E0 0B F0 -05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex deleted file mode 100644 index 94f258e..0000000 --- a/src/mainboard/google/volteer/variants/malefor/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex deleted file mode 100644 index 94f258e..0000000 --- a/src/mainboard/google/volteer/variants/ripto/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex deleted file mode 100644 index 9ec70a9..0000000 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex deleted file mode 100644 index f2c52e2..0000000 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex deleted file mode 100644 index df96e70..0000000 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 29 F9 08 00 00 00 00 09 01 00 00 -48 00 04 FF 92 55 00 00 8C 00 90 A8 90 E0 0B F0 -05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex deleted file mode 100644 index 94f258e..0000000 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex deleted file mode 100644 index 90202f9..0000000 --- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 -48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/41619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f Gerrit-Change-Number: 41619 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: soc,southbridge/intel: Control SMI related FADT entries
by Kyösti Mälkki (Code Review) 07 Jun '20

07 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41909 ) Change subject: soc,southbridge/intel: Control SMI related FADT entries ...................................................................... soc,southbridge/intel: Control SMI related FADT entries When no SMI is installed, FADT should not advertise a trigger mechanism that does respond. Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 78 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41909/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 66cdc3d..66263e6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -128,11 +128,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -150,7 +151,6 @@ fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index a3025c2..4e3795e 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -132,11 +132,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -154,7 +155,6 @@ fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 316b85a..9df7dee 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -184,11 +184,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -206,7 +207,6 @@ fadt->gpe0_blk_len = 32; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 70a9cac..c4a0698 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -100,11 +100,12 @@ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 4041ca2..15d2e66 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -121,13 +121,6 @@ { u16 pmbase = get_pmbase(); - /* System Management */ - if (!CONFIG(HAVE_SMI_HANDLER)) { - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - } - /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -139,7 +132,7 @@ fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c5d709f..34aed02 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -225,11 +225,12 @@ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -248,7 +249,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 334b1b7..d6d847b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -152,16 +152,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0; - fadt->pstate_cnt = 0; - fadt->cst_cnt = 0; - } else { - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0; - fadt->pstate_cnt = 0; - fadt->cst_cnt = 0; } /* General-Purpose Event Registers */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 71119c0..9818508 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -227,13 +227,6 @@ { uint16_t pmbase = ACPI_BASE_ADDRESS; - /* System Management */ - if (!CONFIG(HAVE_SMI_HANDLER)) { - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - } - /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -246,7 +239,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ @@ -345,17 +337,13 @@ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); - /* - TODO: enabled SMM mode switch when SMM handlers are set up. - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - */ - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + /* TODO: enabled SMM mode switch when SMM handlers are set up. */ + if (0 && CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -374,7 +362,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 55e2573..45215f1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -697,11 +697,12 @@ fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -719,7 +720,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 921edf3..26a1856 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -35,11 +35,12 @@ fadt->dsdt = (uintptr_t)dsdt; fadt->preferred_pm_profile = 0; /* unspecified */ fadt->sci_int = 9; - fadt->smi_cmd = 0; /* smi command port */ - fadt->acpi_enable = 0; /* acpi enable smi command */ - fadt->acpi_disable = 0; /* acpi disable smi command */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = ACPI_SMI_CTL_PORT; + fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; + fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; + } fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1b_evt_blk = 0x0; @@ -60,7 +61,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7e2b5a7..86c3e58 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -521,13 +521,15 @@ fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ae98fdd..b3aeda2 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -532,13 +532,15 @@ fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 54b2621..1209f9b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -591,11 +591,12 @@ fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -613,7 +614,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a..da744bf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -740,11 +740,12 @@ u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -775,7 +776,6 @@ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/41909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Gerrit-Change-Number: 41909 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using...
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41878 ) Change subject: mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using gen_part_id.go ...................................................................... mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledee and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:F Byte# Current New Explanation 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Manufacturer name bytes are set to 0. Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc A src/mainboard/google/dedede/variants/waddledee/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/waddledee/memory/mem_list_variant.txt 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/41878/1 diff --git a/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc new file mode 100644 index 0000000..80bea09 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +MEM_TYPE = lp4x +SPD_SOURCES = +SPD_SOURCES += spd-8.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F +SPD_SOURCES += spd-9.hex # ID = 1(0b0001) Parts = NT6AP256T32AV-J2 diff --git a/src/mainboard/google/dedede/variants/waddledee/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/waddledee/memory/dram_id.generated.txt new file mode 100644 index 0000000..9d5ced3 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:F 0 (0000) +NT6AP256T32AV-J2 1 (0001) diff --git a/src/mainboard/google/dedede/variants/waddledee/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/waddledee/memory/mem_list_variant.txt new file mode 100644 index 0000000..08daad4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/memory/mem_list_variant.txt @@ -0,0 +1,2 @@ +MT53E512M32D2NP-046 WT:F +NT6AP256T32AV-J2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c Gerrit-Change-Number: 41878 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using g...
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41879 ) Change subject: mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using gen_part_id.go ...................................................................... mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by wheelie and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:F Byte# Current New Explanation 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc A src/mainboard/google/dedede/variants/wheelie/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/wheelie/memory/mem_list_variant.txt 3 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/41879/1 diff --git a/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc b/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc new file mode 100644 index 0000000..add0919 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/memory/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +MEM_TYPE = lp4x +SPD_SOURCES = +SPD_SOURCES += spd-8.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/dedede/variants/wheelie/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/wheelie/memory/dram_id.generated.txt new file mode 100644 index 0000000..93934ae --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:F 0 (0000) diff --git a/src/mainboard/google/dedede/variants/wheelie/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/wheelie/memory/mem_list_variant.txt new file mode 100644 index 0000000..08daad4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/memory/mem_list_variant.txt @@ -0,0 +1,2 @@ +MT53E512M32D2NP-046 WT:F +NT6AP256T32AV-J2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd Gerrit-Change-Number: 41879 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/google/dedede: Drop selection of GENERIC_SPD_BIN
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42054 ) Change subject: mb/google/dedede: Drop selection of GENERIC_SPD_BIN ...................................................................... mb/google/dedede: Drop selection of GENERIC_SPD_BIN GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it already provides its own rules for SPD inclusion. In follow up changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool to use similar suffixes and allowing different paths to be provided for SPD by mainboard. Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42054/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index d9f5ada..1ec4941 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -8,7 +8,6 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES -- To view, visit https://review.coreboot.org/c/coreboot/+/42054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da Gerrit-Change-Number: 42054 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/volteer: Drop .spd.hex files from spd/
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41882 ) Change subject: mb/google/volteer: Drop .spd.hex files from spd/ ...................................................................... mb/google/volteer: Drop .spd.hex files from spd/ Now that dedede is moved to using the auto-generated SPDs, we no longer need the .spd.hex files in spd/ folder. Hence, this change drops the files. Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex D src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex D src/mainboard/google/dedede/spd/empty.spd.hex 3 files changed, 0 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/41882/1 diff --git a/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex deleted file mode 100644 index ab171f2..0000000 --- a/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 14 19 90 08 00 00 00 00 02 22 00 00 -00 00 05 0A 80 54 01 00 89 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 FB 00 A6 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex deleted file mode 100644 index 71e5456..0000000 --- a/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 -00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/dedede/spd/empty.spd.hex b/src/mainboard/google/dedede/spd/empty.spd.hex deleted file mode 100644 index 67b46cd..0000000 --- a/src/mainboard/google/dedede/spd/empty.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/41882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add Gerrit-Change-Number: 41882 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using...
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41880 ) Change subject: mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using gen_part_id.go ...................................................................... mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by waddledoo and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all dedede variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: MT53E512M32D2NP-046 WT:F Byte# Current New Explanation 9 0x40 0x00 Unused by MRC. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xFF as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Additionally, manufacturer name bytes are set to 0. Part: NT6AP256T32AV-J2 Waddledoo started assigning DRAM part IDs from 1. So, this change fills in Nanya part as ID 0 (though it is currently unused). Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc A src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41880/1 diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc new file mode 100644 index 0000000..267cd0d --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +MEM_TYPE = lp4x +SPD_SOURCES = +SPD_SOURCES += spd-9.hex # ID = 0(0b0000) Parts = NT6AP256T32AV-J2 +SPD_SOURCES += spd-8.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt new file mode 100644 index 0000000..4c76adf --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +NT6AP256T32AV-J2 0 (0000) +MT53E512M32D2NP-046 WT:F 1 (0001) diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt new file mode 100644 index 0000000..9f146d4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/memory/mem_list_variant.txt @@ -0,0 +1,2 @@ +NT6AP256T32AV-J2 +MT53E512M32D2NP-046 WT:F -- To view, visit https://review.coreboot.org/c/coreboot/+/41880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd Gerrit-Change-Number: 41880 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 10

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