Change in coreboot[master]: lp4x: Add two new parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add two new parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR
......................................................................

lp4x: Add two new parts MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR

This change adds two parts MT53E512M32D2NP-046 WT:E and
K4U6E3S4AA-MGCR to global_lp4x_mem_parts.json.txt and generates SPD
files for TGL and JSL for these parts.

BUG=b:157862308

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh 
---
M src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
3 files changed, 29 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/41989/1

diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
index 67f9669..a5e19bf 100644
--- a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
+++ b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
@@ -7,3 +7,5 @@
 MT53E1G64D4SQ-046 WT:A,spd-7.hex
 MT53E512M32D2NP-046 WT:F,spd-8.hex
 NT6AP256T32AV-J2,spd-9.hex
+K4U6E3S4AA-MGCR,spd-3.hex
+MT53E512M32D2NP-046 WT:E,spd-8.hex
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
index 37d04ee..2d554c5 100644
--- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
@@ -7,3 +7,5 @@
 MT53E1G64D4SQ-046 WT:A,spd-6.hex
 MT53E512M32D2NP-046 WT:F,spd-7.hex
 NT6AP256T32AV-J2,spd-8.hex
+K4U6E3S4AA-MGCR,spd-1.hex
+MT53E512M32D2NP-046 WT:E,spd-7.hex
diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
index a9c13b0..7d82be7 100644
--- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
@@ -109,6 +109,30 @@
                 "tckMaxPs": 1250,
                 "casLatencies": "14 20 24 28 32"
             }
-         }
+        },
+        {
+            "name": "K4U6E3S4AA-MGCR",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 1,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "MT53E512M32D2NP-046 WT:E",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 1,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        }
     ]
 }

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41989

to look at the new patch set (#2).

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

lp4x: Add new memory parts and generate SPDs

This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR

BUG=b:157862308, b:157732528

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh 
---
A src/soc/intel/jasperlake/spd/lp4x/spd-10.hex
M src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
4 files changed, 89 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/41989/2

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41989

to look at the new patch set (#4).

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

lp4x: Add new memory parts and generate SPDs

This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR

BUG=b:157862308, b:157732528

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh 
---
M src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
3 files changed, 57 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/41989/4

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41989/6/util/spd_tools/intel/lp4x/g... 
File util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt:

https://review.coreboot.org/c/coreboot/+/41989/6/util/spd_tools/intel/lp4x/g... 
PS6, Line 131: 1
It is a DDP and not a SDP. D2 indicates a DDP.

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41989

to look at the new patch set (#7).

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

lp4x: Add new memory parts and generate SPDs

This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR

BUG=b:157862308, b:157732528

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh 
---
M src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
3 files changed, 57 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/41989/7

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

Patch Set 8: Code-Review+2

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41989/6/util/spd_tools/intel/lp4x/g... 
File util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt:

https://review.coreboot.org/c/coreboot/+/41989/6/util/spd_tools/intel/lp4x/g... 
PS6, Line 131: 1
> It is a DDP and not a SDP. D2 indicates a DDP.

diesPerPackage as per JESD209-4C seems to be calculated differently. See: https://review.coreboot.org/c/coreboot/+/41612/19/util/spd_tools/intel/lp4x/...

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

Patch Set 8: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/41989/6/util/spd_tools/intel/lp4x/g... 
File util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt:

https://review.coreboot.org/c/coreboot/+/41989/6/util/spd_tools/intel/lp4x/g... 
PS6, Line 131: 1
> diesPerPackage as per JESD209-4C seems to be calculated differently. See: https://review.coreboot. […]

Missed the explanation in the README file. Makes sense.

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

lp4x: Add new memory parts and generate SPDs

This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR

BUG=b:157862308, b:157732528

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989
Reviewed-by: Nick Vaccaro 
Reviewed-by: Karthik Ramasubramanian 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
3 files changed, 57 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
index e916733..564322e 100644
--- a/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
+++ b/src/soc/intel/jasperlake/spd/lp4x/spd_manifest.generated.txt
@@ -7,3 +7,7 @@
 MT53E1G64D4SQ-046 WT:A,spd-6.hex
 MT53E512M32D2NP-046 WT:F,spd-1.hex
 NT6AP256T32AV-J2,spd-7.hex
+K4U6E3S4AA-MGCR,spd-1.hex
+MT53E512M32D2NP-046 WT:E,spd-1.hex
+H9HCNNNCPMMLXR-NEE,spd-3.hex
+K4UBE3D4AA-MGCR,spd-3.hex
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
index d11e93d..49fe445 100644
--- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
+++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt
@@ -7,3 +7,7 @@
 MT53E1G64D4SQ-046 WT:A,spd-4.hex
 MT53E512M32D2NP-046 WT:F,spd-1.hex
 NT6AP256T32AV-J2,spd-5.hex
+K4U6E3S4AA-MGCR,spd-1.hex
+MT53E512M32D2NP-046 WT:E,spd-1.hex
+H9HCNNNCPMMLXR-NEE,spd-3.hex
+K4UBE3D4AA-MGCR,spd-3.hex
diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
index 5635158..b9dd4b3 100644
--- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
+++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt
@@ -109,6 +109,54 @@
                 "tckMaxPs": 1250,
                 "casLatencies": "14 20 24 28 32"
             }
-         }
+        },
+        {
+            "name": "K4U6E3S4AA-MGCR",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 1,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "MT53E512M32D2NP-046 WT:E",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 1,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "H9HCNNNCPMMLXR-NEE",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 4267
+            }
+        },
+        {
+            "name": "K4UBE3D4AA-MGCR",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 2,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 4267
+            }
+        }
     ]
 }

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41989 )

Change subject: lp4x: Add new memory parts and generate SPDs
......................................................................

Patch Set 10:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/5118
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5117
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5116
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/5115

Please note: This test is under development and might not be accurate at all!