Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41909 )
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
soc,southbridge/intel: Control SMI related FADT entries
When no SMI is installed, FADT should not advertise a trigger mechanism that does respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 78 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41909/1
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 66cdc3d..66263e6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -128,11 +128,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -150,7 +151,6 @@ fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index a3025c2..4e3795e 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -132,11 +132,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -154,7 +155,6 @@ fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 316b85a..9df7dee 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -184,11 +184,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -206,7 +207,6 @@ fadt->gpe0_blk_len = 32; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 70a9cac..c4a0698 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -100,11 +100,12 @@ fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 4041ca2..15d2e66 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -121,13 +121,6 @@ { u16 pmbase = get_pmbase();
- /* System Management */ - if (!CONFIG(HAVE_SMI_HANDLER)) { - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - } - /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -139,7 +132,7 @@ fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c5d709f..34aed02 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -225,11 +225,12 @@ fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -248,7 +249,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 334b1b7..d6d847b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -152,16 +152,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0; - fadt->pstate_cnt = 0; - fadt->cst_cnt = 0; - } else { - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0; - fadt->pstate_cnt = 0; - fadt->cst_cnt = 0; }
/* General-Purpose Event Registers */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 71119c0..9818508 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -227,13 +227,6 @@ { uint16_t pmbase = ACPI_BASE_ADDRESS;
- /* System Management */ - if (!CONFIG(HAVE_SMI_HANDLER)) { - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - } - /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -246,7 +239,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ @@ -345,17 +337,13 @@ fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq(); - /* - TODO: enabled SMM mode switch when SMM handlers are set up. - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - */ - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + /* TODO: enabled SMM mode switch when SMM handlers are set up. */ + if (0 && CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -374,7 +362,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 55e2573..45215f1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -697,11 +697,12 @@ fadt->reserved = 0;
fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -719,7 +720,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 921edf3..26a1856 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -35,11 +35,12 @@ fadt->dsdt = (uintptr_t)dsdt; fadt->preferred_pm_profile = 0; /* unspecified */ fadt->sci_int = 9; - fadt->smi_cmd = 0; /* smi command port */ - fadt->acpi_enable = 0; /* acpi enable smi command */ - fadt->acpi_disable = 0; /* acpi disable smi command */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = ACPI_SMI_CTL_PORT; + fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; + fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; + }
fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1b_evt_blk = 0x0; @@ -60,7 +61,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4;
- fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7e2b5a7..86c3e58 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -521,13 +521,15 @@
fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL;
- fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ae98fdd..b3aeda2 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -532,13 +532,15 @@
fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL;
- fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 54b2621..1209f9b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -591,11 +591,12 @@ fadt->reserved = 0;
fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -613,7 +614,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a..da744bf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -740,11 +740,12 @@ u16 pmbase = get_pmbase();
fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -775,7 +776,6 @@ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0;
- fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 0;
Hello build bot (Jenkins), David Guckian, Vanessa Eusebio, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41909
to look at the new patch set (#3).
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
soc,southbridge/intel: Control SMI related FADT entries
When no SMI is installed, FADT should not advertise a trigger mechanism that does respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 78 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41909/3
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41909 )
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
Patch Set 3: Code-Review+2
Hello build bot (Jenkins), Furquan Shaikh, David Guckian, Vanessa Eusebio, Subrata Banik, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41909
to look at the new patch set (#4).
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
soc,southbridge/intel: Control SMI related FADT entries
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 78 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41909/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41909 )
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41909 )
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
soc,southbridge/intel: Control SMI related FADT entries
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 78 insertions(+), 103 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 66cdc3d..66263e6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -128,11 +128,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -150,7 +151,6 @@ fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index a3025c2..4e3795e 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -132,11 +132,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -154,7 +155,6 @@ fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 316b85a..9df7dee 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -184,11 +184,12 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -206,7 +207,6 @@ fadt->gpe0_blk_len = 32; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 70a9cac..c4a0698 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -100,11 +100,12 @@ fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 4041ca2..15d2e66 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -121,13 +121,6 @@ { u16 pmbase = get_pmbase();
- /* System Management */ - if (!CONFIG(HAVE_SMI_HANDLER)) { - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - } - /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -139,7 +132,7 @@ fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c5d709f..34aed02 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -225,11 +225,12 @@ fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -248,7 +249,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 334b1b7..d6d847b 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -152,16 +152,6 @@ fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0; - fadt->pstate_cnt = 0; - fadt->cst_cnt = 0; - } else { - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0; - fadt->pstate_cnt = 0; - fadt->cst_cnt = 0; }
/* General-Purpose Event Registers */ diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 71119c0..9cb36b8 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -6,6 +6,7 @@ #include <intelblocks/acpi.h> #include <device/pci.h> #include <cbmem.h> +#include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> @@ -227,13 +228,6 @@ { uint16_t pmbase = ACPI_BASE_ADDRESS;
- /* System Management */ - if (!CONFIG(HAVE_SMI_HANDLER)) { - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - } - /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -246,7 +240,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ @@ -345,17 +338,13 @@ fadt->header.revision = get_acpi_table_revision(FADT);
fadt->sci_int = acpi_sci_irq(); - /* - TODO: enabled SMM mode switch when SMM handlers are set up. - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - */ - fadt->smi_cmd = 0x00; - fadt->acpi_enable = 0x00; - fadt->acpi_disable = 0x00; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + /* TODO: enabled SMM mode switch when SMM handlers are set up. */ + if (0 && CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -374,7 +363,6 @@ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 55e2573..45215f1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -697,11 +697,12 @@ fadt->reserved = 0;
fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -719,7 +720,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 921edf3..09e027f 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -35,11 +35,11 @@ fadt->dsdt = (uintptr_t)dsdt; fadt->preferred_pm_profile = 0; /* unspecified */ fadt->sci_int = 9; - fadt->smi_cmd = 0; /* smi command port */ - fadt->acpi_enable = 0; /* acpi enable smi command */ - fadt->acpi_disable = 0; /* acpi disable smi command */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* TODO: SMI handler is not implemented. */ + fadt->smi_cmd = 0x00; + }
fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1b_evt_blk = 0x0; @@ -60,7 +60,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4;
- fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7e2b5a7..86c3e58 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -521,13 +521,15 @@
fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL;
- fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ae98fdd..b3aeda2 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -532,13 +532,15 @@
fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL;
- fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 54b2621..1209f9b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -591,11 +591,12 @@ fadt->reserved = 0;
fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -613,7 +614,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a..da744bf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -740,11 +740,12 @@ u16 pmbase = get_pmbase();
fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + }
fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -775,7 +776,6 @@ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0;
- fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 0;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41909 )
Change subject: soc,southbridge/intel: Control SMI related FADT entries ......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4968 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4967 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4966 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4965
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Kyösti Mälkki (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)