coreboot-gerrit June 2020

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Change in coreboot[master]: src: Remove unused 'include <cpu/x86/mtrr.h>'
by HAOUAS Elyes (Code Review) 07 Jun '20

07 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41782 ) Change subject: src: Remove unused 'include <cpu/x86/mtrr.h>' ...................................................................... src: Remove unused 'include <cpu/x86/mtrr.h>' Change-Id: I3f08b9cc34582165785063580b3356135030f63e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/car/romstage.c M src/cpu/intel/haswell/bootblock.c M src/cpu/x86/lapic/secondary.S M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/gma/intel_ddi.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/x4x/raminit.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/common/block/cpu/car/exit_car_fsp.S M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/xeon_sp/skx/romstage.c 15 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/41782/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 233e106..a955d8c 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -4,7 +4,6 @@ #include <arch/romstage.h> #include <bootblock_common.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <arch/symbols.h> #include <commonlib/helpers.h> diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 2fe9400..c9e3f2a 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <arch/bootblock.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 6aa0c59..8a44112 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> #include <arch/ram_segs.h> diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 51c4340..46df1c8 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -7,7 +7,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <cpu/intel/microcode.h> -#include <cpu/x86/mtrr.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <elog.h> diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 87b768c..a04789b 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -8,7 +8,6 @@ #include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <cpu/x86/tsc.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <edid.h> #include <drivers/intel/gma/i915.h> diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 65db922..b87ba6e 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -19,7 +19,6 @@ #include <lib.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <assert.h> #include <spd.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 330ce9e..e505a5b 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -4,7 +4,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <arch/cpu.h> #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 79f859b..d6883c6 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -4,7 +4,6 @@ #include <arch/bootblock.h> #include <arch/io.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <halt.h> #include <soc/rcba.h> #include <soc/msr.h> diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 393d612..b9daf08 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <device/pci_def.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> diff --git a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S index e5798fb..fd79e8e 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car_fsp.S +++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cpu/x86/mtrr.h> #include <cpu/x86/cr.h> /* diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c39b453..ae0a8a0 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/cpu.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index cabcded..76db62e 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> -#include <cpu/x86/mtrr.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index abfd3de..713fb1e 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <device/pci_ops.h> #include <soc/fiamux.h> #include <device/mmio.h> diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 9693b72..31df09d 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -5,7 +5,6 @@ #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 18dc814..c4c473b 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -3,7 +3,6 @@ #include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> #include <soc/soc_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f08b9cc34582165785063580b3356135030f63e Gerrit-Change-Number: 41782 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>'
by HAOUAS Elyes (Code Review) 07 Jun '20

07 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41686 ) Change subject: cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>' ...................................................................... cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>' Change-Id: I5156eb97648927e5fe6e467abb8e3e055a231fec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/41686/1 diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index c682ef9..4b56301 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <cf9_reset.h> -#include <cpu/x86/bist.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5156eb97648927e5fe6e467abb8e3e055a231fec Gerrit-Change-Number: 41686 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: amd/pi/hudson boards: Get rid of power button device
by Paul Menzel (Code Review) 07 Jun '20

07 Jun '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40753 ) Change subject: amd/pi/hudson boards: Get rid of power button device ...................................................................... amd/pi/hudson boards: Get rid of power button device Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD AGESA Hudson boards (SOUTHBRIDGE_AMD_PI_AVALON). Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/bap/ode_e21XX/dsdt.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/40753/1 diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index f18550a..e604a5a 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -40,13 +40,6 @@ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index cc6c03d..9ef1dd3 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -40,13 +40,6 @@ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/40753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45 Gerrit-Change-Number: 40753 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: amd/agesa/hudson boards: Get rid of power button device
by Paul Menzel (Code Review) 07 Jun '20

07 Jun '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40754 ) Change subject: amd/agesa/hudson boards: Get rid of power button device ...................................................................... amd/agesa/hudson boards: Get rid of power button device Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD AGESA Hudson boards. No idea, if this is correct for the two laptops. The Lenovo G505s also incorrectly defines two power buttons. [ 0.911423] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 [ 0.911434] ACPI: Power Button [PWRB] [ 0.911493] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 [ 0.912326] ACPI: Power Button [PWRF] If the generic power button device is needed, the POWER_BUTTON flag should be set in FADT. Change-Id: I88950e15faf1b90ca6e688864bac40bf9779c32e Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/amd/parmer/dsdt.asl M src/mainboard/amd/thatcher/dsdt.asl M src/mainboard/asus/f2a85-m/dsdt.asl M src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl M src/mainboard/lenovo/g505s/acpi/mainboard.asl M src/mainboard/msi/ms7721/dsdt.asl 6 files changed, 0 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/40754/1 diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index 20e550f..95b4a72 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -39,13 +39,6 @@ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index 20e550f..95b4a72 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -39,13 +39,6 @@ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index e436409..426b330 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -39,13 +39,6 @@ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index fc8fb72..6d1370a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -80,12 +80,6 @@ } } - Device(PWRB) { - Name(_HID, EisaId("PNP0C0C")) - Name(_UID, 0xAA) - Name(_STA, 0x0B) - } - Device (MB) { Name(_HID, EisaId("PNP0C01")) // System Board diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl index fc8fb72..6d1370a 100644 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl @@ -80,12 +80,6 @@ } } - Device(PWRB) { - Name(_HID, EisaId("PNP0C0C")) - Name(_UID, 0xAA) - Name(_STA, 0x0B) - } - Device (MB) { Name(_HID, EisaId("PNP0C01")) // System Board diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl index 5fb15ea..375ce96 100644 --- a/src/mainboard/msi/ms7721/dsdt.asl +++ b/src/mainboard/msi/ms7721/dsdt.asl @@ -36,13 +36,6 @@ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/40754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88950e15faf1b90ca6e688864bac40bf9779c32e Gerrit-Change-Number: 40754 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/amd/picasso: Add device operations for UART MMIO devices
by Furquan Shaikh (Code Review) 07 Jun '20

07 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42068 ) Change subject: soc/amd/picasso: Add device operations for UART MMIO devices ...................................................................... soc/amd/picasso: Add device operations for UART MMIO devices This change adds device_operations for UART MMIO devices that provides following operations: 1. uart_acpi_name: Returns ACPI name of UART device. Generation of UART device node is not yet moved to SSDT, but will be done in follow-up CLs. 2. scan_bus: Uses scan_static_bus to scan devices added under the UART devices. This allows mainboard to add devices under the UART MMIO device. Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/uart.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/42068/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index ed39b53..503dc62 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -16,6 +16,8 @@ /* Supplied by i2c.c */ extern struct device_operations picasso_i2c_mmio_ops; +/* Supplied by uart.c */ +extern struct device_operations picasso_uart_mmio_ops; struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, @@ -127,6 +129,12 @@ case APU_I2C4_BASE: dev->ops = &picasso_i2c_mmio_ops; break; + case APU_UART0_BASE: + case APU_UART1_BASE: + case APU_UART2_BASE: + case APU_UART3_BASE: + dev->ops = &picasso_uart_mmio_ops; + break; } } diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 6ae79b95..b1331ec 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -74,3 +74,26 @@ { return CONFIG(PICASSO_UART_48MZ) ? 48000000 : 115200 * 16; } + +static const char *uart_acpi_name(const struct device *dev) +{ + switch (dev->path.mmio.addr) { + case APU_UART0_BASE: + return "FUR0"; + case APU_UART1_BASE: + return "FUR1"; + case APU_UART2_BASE: + return "FUR2"; + case APU_UART3_BASE: + return "FUR3"; + default: + return NULL; + } +} + +struct device_operations picasso_uart_mmio_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .acpi_name = uart_acpi_name, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/42068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850 Gerrit-Change-Number: 42068 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/51nb/x210: Remove duplicate ACPI power button device
by Paul Menzel (Code Review) 07 Jun '20

07 Jun '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41018 ) Change subject: mb/51nb/x210: Remove duplicate ACPI power button device ...................................................................... mb/51nb/x210: Remove duplicate ACPI power button device This is copied from the Purism Librem 13v3, and is not needed, as the standard fixed power button is used. It was removed for the Pursim devices in commit 2d977b2dcb (mb/purism: remove duplicate ACPI power button). Change-Id: I8fe19b8fbcc11d859a75b3dc6b9bcc42c80d13f1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/51nb/x210/acpi/mainboard.asl 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41018/1 diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl index fb389a4..cf63b5b 100644 --- a/src/mainboard/51nb/x210/acpi/mainboard.asl +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -18,18 +18,6 @@ } } - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - - Method (_STA) - { - Return (0xF) - } - - Name (_PRW, Package () { 27, 4 }) - } - Device (SLPB) { Name (_HID, EisaId ("PNP0C0E")) -- To view, visit https://review.coreboot.org/c/coreboot/+/41018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fe19b8fbcc11d859a75b3dc6b9bcc42c80d13f1 Gerrit-Change-Number: 41018 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/roda/rk9: Control SMI related FADT entries
by Kyösti Mälkki (Code Review) 07 Jun '20

07 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41905 ) Change subject: mb/roda/rk9: Control SMI related FADT entries ...................................................................... mb/roda/rk9: Control SMI related FADT entries When no SMI is installed, FADT should not advertise a trigger mechanism that does respond. Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/roda/rk9/fadt.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/41905/1 diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index b854667..102865d 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -25,11 +25,14 @@ fadt->reserved = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -48,7 +51,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = APM_CNT_CST_CONTROL; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 0x39; fadt->flush_size = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/41905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f Gerrit-Change-Number: 41905 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35: Control SMI related FADT entries
by Kyösti Mälkki (Code Review) 07 Jun '20

07 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41907 ) Change subject: mb/emulation/qemu-q35: Control SMI related FADT entries ...................................................................... mb/emulation/qemu-q35: Control SMI related FADT entries Never advertise SMI in FADT for the emulation. Change-Id: I170058793798648c6713de1530d89ec2ac53e39a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/acpi_tables.c 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/41907/1 diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index b9e76a9..4236257 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -42,11 +42,13 @@ fadt->reserved = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* Do not advertise SMI even if installed. */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -65,7 +67,6 @@ fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 0x39; fadt->flush_size = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/41907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I170058793798648c6713de1530d89ec2ac53e39a Gerrit-Change-Number: 41907 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: set up cpus
by 9elements QA (Code Review) 07 Jun '20

07 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40112 ) Change subject: soc/intel/xeon_sp/cpx: set up cpus ...................................................................... Patch Set 20: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4950 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4949 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4948 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4947 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/40112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8 Gerrit-Change-Number: 40112 Gerrit-PatchSet: 20 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 07 Jun 2020 17:36:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: drivers/usb: add a USB pre-poll hook
by 9elements QA (Code Review) 07 Jun '20

07 Jun '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42072 ) Change subject: libpayload: drivers/usb: add a USB pre-poll hook ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4943 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4942 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4941 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4940 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/42072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Gerrit-Change-Number: 42072 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 07 Jun 2020 17:36:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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