Change in coreboot[master]: nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register

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HAOUAS Elyes (Code Review)

29 Apr 2020 29 Apr '20

7:09 a.m.

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register ......................................................................

nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/iommu.c 1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/1

diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4d88e36..a0f85f9 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -37,9 +37,9 @@ pci_devfn_t igd = PCI_DEV(0, 2, 0);

/* setup somewhere */ - u8 cmd = pci_read_config8(igd, PCI_COMMAND); + u16 cmd = pci_read_config16(igd, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);

/* clear GTT, 2MB is enough (and should be safe) */ @@ -47,7 +47,7 @@

/* and now disable again */ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); }

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HAOUAS Elyes (Code Review)

29 Apr 29 Apr

7:14 a.m.

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40835

to look at the new patch set (#2).

Change subject: nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register ......................................................................

nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c 2 files changed, 4 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/2

HAOUAS Elyes (Code Review)

7:20 a.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

Patch Set 2:

This change is ready for review.

HAOUAS Elyes (Code Review)

1 May 1 May

5:51 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40835

to look at the new patch set (#4).

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

nb/intel: Fix 16-bit read/write PCI_COMMAND register

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/4

HAOUAS Elyes (Code Review)

6:31 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40835

to look at the new patch set (#5).

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

nb/intel: Fix 16-bit read/write PCI_COMMAND register

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/5

HAOUAS Elyes (Code Review)

6:40 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40835

to look at the new patch set (#6).

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

nb/intel: Fix 16-bit read/write PCI_COMMAND register

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/6

Nico Huber (Code Review)

21 May 21 May

11:09 a.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

Patch Set 6: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/40835/6/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/iommu.c:

https://review.coreboot.org/c/coreboot/+/40835/6/src/northbridge/intel/gm45/... PS6, Line 47: u16 cmd = pci_read_config8(igd, PCI_COMMAND); : cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); : pci_write_config16(igd, PCI_COMMAND, cmd); Can be written as

pci_update_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY), 0);

-- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Thu, 21 May 2020 11:09:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

HAOUAS Elyes (Code Review)

5:25 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

Patch Set 6:

(1 comment)

Thank you.

https://review.coreboot.org/c/coreboot/+/40835/6/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/iommu.c:

...

Can be written as […]

maybe for the next changes (see https://review.coreboot.org/c/coreboot/+/41631 )

-- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 21 May 2020 17:25:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber nico.h@gmx.de Gerrit-MessageType: comment

Patrick Georgi (Code Review)

26 May 26 May

3:11 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

nb/intel: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/northbridge.c 4 files changed, 6 insertions(+), 19 deletions(-)

Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 0d106b8..10e0d02 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -36,17 +36,16 @@ const pci_devfn_t igd = PCI_DEV(0, 2, 0);

/* setup somewhere */ - u8 cmd = pci_read_config8(igd, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);

/* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20);

/* and now disable again */ + u16 cmd = pci_read_config8(igd, PCI_COMMAND); cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); }

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index cd64dfe..b3dbe16 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -178,14 +178,10 @@

static void mch_domain_init(struct device *dev) { - u32 reg32; - struct device *mch = pcidev_on_root(0, 0);

/* Enable SERR */ - reg32 = pci_read_config32(mch, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(mch, PCI_COMMAND, reg32); + pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR); }

static const char *northbridge_acpi_name(const struct device *dev) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 83bc60e..856eab3 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -147,12 +147,8 @@

static void mch_domain_init(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); }

static const char *northbridge_acpi_name(const struct device *dev) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 45b6ce3..9c32dae 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -131,12 +131,8 @@

static const char *northbridge_acpi_name(const struct device *dev)

-- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: merged

9elements QA (Code Review)

6:10 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

Patch Set 7:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4107 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4106 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4105 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4104

Please note: This test is under development and might not be accurate at all!

-- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 26 May 2020 18:10:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Angel Pons (Code Review)

7 Jun 7 Jun

4:22 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40835/7/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/iommu.c:

https://review.coreboot.org/c/coreboot/+/40835/7/src/northbridge/intel/gm45/... PS7, Line 46: pci_read_config8 um

-- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 07 Jun 2020 16:22:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Nico Huber (Code Review)

4:30 p.m.

New subject: Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register ......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40835/7/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/iommu.c:

https://review.coreboot.org/c/coreboot/+/40835/7/src/northbridge/intel/gm45/... PS7, Line 46: pci_read_config8

...

um

yeah

-- To view, visit https://review.coreboot.org/c/coreboot/+/40835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Gerrit-Change-Number: 40835 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 07 Jun 2020 16:30:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

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9elements QA (Code Review)
Angel Pons (Code Review)
HAOUAS Elyes (Code Review)
Nico Huber (Code Review)
Patrick Georgi (Code Review)