[coreboot-gerrit] Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register
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Patch Set 6:

(1 comment)

Thank you.

https://review.coreboot.org/c/coreboot/+/40835/6/src/northbridge/intel/gm45/... 
File src/northbridge/intel/gm45/iommu.c:

https://review.coreboot.org/c/coreboot/+/40835/6/src/northbridge/intel/gm45/... 
PS6, Line 47: 		u16 cmd = pci_read_config8(igd, PCI_COMMAND);
            : 		cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
            : 		pci_write_config16(igd, PCI_COMMAND, cmd);
> Can be written as […]

maybe for the next changes 
(see  https://review.coreboot.org/c/coreboot/+/41631 )