HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40835 )
Change subject: nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register ......................................................................
nb/intel/gm45: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/gm45/iommu.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40835/1
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4d88e36..a0f85f9 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -37,9 +37,9 @@ pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */ - u8 cmd = pci_read_config8(igd, PCI_COMMAND); + u16 cmd = pci_read_config16(igd, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
/* clear GTT, 2MB is enough (and should be safe) */ @@ -47,7 +47,7 @@
/* and now disable again */ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(igd, PCI_COMMAND, cmd); + pci_write_config16(igd, PCI_COMMAND, cmd); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); }