Change in coreboot[master]: soc/intel/tigerlake: Add CPU ID for TGL B0

[Jamie Ryu (Code Review)]

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

soc/intel/tigerlake: Add CPU ID for TGL B0

BRANCH=none
BUG=none
TEST=build and boot tglrvp

Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/tigerlake/bootblock/report_platform.c
3 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41516/1

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 5cd0134..90bae16 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -73,6 +73,7 @@
    { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 },
    { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 },
    { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 },
+	{ X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 },
    { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 },
    { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0},
    { 0, 0 },
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index c15c323..e03d8bd 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -41,6 +41,7 @@
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
 #define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
 #define CPUID_TIGERLAKE_A0	0x806c0
+#define CPUID_TIGERLAKE_B0	0x806c1
 #define CPUID_ELKHARTLAKE_A0	0x90660

/*
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index d6d9f36..a64738d 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -25,6 +25,7 @@
    const char *name;
 } cpu_table[] = {
    { CPUID_TIGERLAKE_A0, "Tigerlake A0" },
+	{ CPUID_TIGERLAKE_B0, "Tigerlake B0" },
 };

static struct {

[Jamie Ryu (Code Review)]

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 1: Code-Review+1

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 1:

Can you add reference document info in commit message?
I think best reference document is Tiger Lake Platform Stepping and IDs User Guide(#605534)
But I had issue to download.  And I could also find this info from #626109.

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 1: Code-Review+1

[Jamie Ryu (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Shreesh Chhabbi, Nick Vaccaro, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41516

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

soc/intel/tigerlake: Add CPU ID for TGL B0

Reference:
- TGL User Guide #613584 Rev 2.2
- TGL User Guide #605534 Rev 1.0

BRANCH=none
BUG=none
TEST=build and boot tglrvp

Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/tigerlake/bootblock/report_platform.c
3 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41516/2

[Jamie Ryu (Code Review)]

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 2: Code-Review+1

Updated comments with reference document information.

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 2: Code-Review+2

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 2: Code-Review+1

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

soc/intel/tigerlake: Add CPU ID for TGL B0

Reference:
- TGL User Guide #613584 Rev 2.2
- TGL User Guide #605534 Rev 1.0

BRANCH=none
BUG=none
TEST=build and boot tglrvp

Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e
Signed-off-by: Jamie Ryu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41516
Reviewed-by: Wonkyu Kim 
Reviewed-by: Paul Menzel 
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/tigerlake/bootblock/report_platform.c
3 files changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Nick Vaccaro: Looks good to me, approved
  Wonkyu Kim: Looks good to me, approved
  Jamie Ryu: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 5cd0134..90bae16 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -73,6 +73,7 @@
    { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 },
    { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 },
    { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 },
+	{ X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 },
    { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 },
    { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0},
    { 0, 0 },
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
index c15c323..e03d8bd 100644
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -41,6 +41,7 @@
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
 #define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
 #define CPUID_TIGERLAKE_A0	0x806c0
+#define CPUID_TIGERLAKE_B0	0x806c1
 #define CPUID_ELKHARTLAKE_A0	0x90660

/*
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index d6d9f36..a64738d 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -25,6 +25,7 @@
    const char *name;
 } cpu_table[] = {
    { CPUID_TIGERLAKE_A0, "Tigerlake A0" },
+	{ CPUID_TIGERLAKE_B0, "Tigerlake B0" },
 };

static struct {

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41516 )

Change subject: soc/intel/tigerlake: Add CPU ID for TGL B0
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/5052
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5051
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5050
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/5049

Please note: This test is under development and might not be accurate at all!