[PATCH 00/20] q35 support patch series

[Gerd Hoffmann]

Hi,

Next round of the q35 patch series, addressing review
comments from Jason and Kevin.

cheers,
  Gerd

Gerd Hoffmann (14):
  simplify chipset detection
  acpi: add mcfg table for mmconfig
  acpi: move DBUG() to separate file
  acpi: move DBUG() to separate file [q35]
  acpi: move _SB.HPET to separate file
  acpi: move _SB.HPET to separate file [q35]
  acpi: move _SB.PCI0._CRS to separate file
  acpi: move _SB.PCI0._CRS to separate file [q35]
  acpi: move cpu hotplug to separate file
  acpi: move cpu hotplug to separate file [q35]
  acpi: rework enable bits
  acpi: move isa devices to separate file
  acpi: move isa devices to separate file [q35]
  q35: fix default vga address

Isaku Yamahata (4):
  seabios: acpi, fadt: make while fadt initialization chipset specific
  seabios: pci: enable SERR of normal device.
  seabios: add q35 initialization functions.
  seabios: q35: add dsdt

Jan Kiszka (1):
  seabios: q35: Register PCI IRQs as active high in APIC mode

Jason Baron (1):
  seabios: make mttr UC area setup dynamic

Makefile                      |    2 +-
 src/acpi-dsdt-cpu-hotplug.dsl |   77 +++++++
 src/acpi-dsdt-dbug.dsl        |   30 +++
 src/acpi-dsdt-hpet.dsl        |   36 ++++
 src/acpi-dsdt-isa.dsl         |  134 ++++++++++++
 src/acpi-dsdt-pci-crs.dsl     |  108 ++++++++++
 src/acpi-dsdt.dsl             |  450 ++-------------------------------------
 src/acpi.c                    |  108 +++++++----
 src/acpi.h                    |   17 ++
 src/config.h                  |    1 -
 src/dev-q35.h                 |   46 ++++
 src/mtrr.c                    |    5 +-
 src/pci.h                     |    2 +
 src/pciinit.c                 |   94 ++++++++-
 src/post.c                    |    6 +-
 src/q35-acpi-dsdt.dsl         |  464 +++++++++++++++++++++++++++++++++++++++++
 src/shadow.c                  |   13 ++
 src/smm.c                     |   37 ++++
 18 files changed, 1153 insertions(+), 477 deletions(-)
 create mode 100644 src/acpi-dsdt-cpu-hotplug.dsl
 create mode 100644 src/acpi-dsdt-dbug.dsl
 create mode 100644 src/acpi-dsdt-hpet.dsl
 create mode 100644 src/acpi-dsdt-isa.dsl
 create mode 100644 src/acpi-dsdt-pci-crs.dsl
 create mode 100644 src/dev-q35.h
 create mode 100644 src/q35-acpi-dsdt.dsl

[PATCH 01/20] seabios: make mttr UC area setup dynamic

[Gerd Hoffmann]

From: Jason Baron

Set up the UC area of mtrr dynamically based on mtrr_base. This allows
the bios to work for other chipsets that might want to set the mtrr.
Since BUILD_MAX_HIGHMEM is no longer used we can remove the config parameter.

This change reverses the order of pci_setup() and smm_init() with
mtrr_setup().

Signed-off-by: Jason Baron 
---
 src/config.h |    1 -
 src/mtrr.c   |    5 +++--
 src/post.c   |    6 +++---
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/config.h b/src/config.h
index 0d4066d..71c0b7e 100644
--- a/src/config.h
+++ b/src/config.h
@@ -44,7 +44,6 @@
 #define BUILD_SMM_INIT_ADDR       0x38000
 #define BUILD_SMM_ADDR            0xa8000
 #define BUILD_SMM_SIZE            0x8000
-#define BUILD_MAX_HIGHMEM         0xe0000000

#define BUILD_PCIMEM_START        0xe0000000
 #define BUILD_PCIMEM_END          0xfec00000    /* IOAPIC is mapped at */
diff --git a/src/mtrr.c b/src/mtrr.c
index 0957834..2cbf234 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -7,6 +7,7 @@
 #include "util.h" // dprintf
 #include "config.h" // CONFIG_*
 #include "xen.h" // usingXen
+#include "pci.h" // pcimem_start

#define MSR_MTRRcap                    0x000000fe
 #define MSR_MTRRfix64K_00000           0x00000250
@@ -94,9 +95,9 @@ void mtrr_setup(void)
         wrmsr_smp(MTRRphysMask_MSR(i), 0);
     }
     /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
-    wrmsr_smp(MTRRphysBase_MSR(0), BUILD_MAX_HIGHMEM | MTRR_MEMTYPE_UC);
+    wrmsr_smp(MTRRphysBase_MSR(0), pcimem_start | MTRR_MEMTYPE_UC);
     wrmsr_smp(MTRRphysMask_MSR(0)
-              , (-((1ull<<32)-BUILD_MAX_HIGHMEM) & phys_mask) | 0x800);
+              , (-((1ull<<32)-pcimem_start) & phys_mask) | 0x800);

// Enable fixed and variable MTRRs; set default type.
     wrmsr_smp(MSR_MTRRdefType, 0xc00 | MTRR_MEMTYPE_WB);
diff --git a/src/post.c b/src/post.c
index 0133f75..ffb4717 100644
--- a/src/post.c
+++ b/src/post.c
@@ -232,13 +232,13 @@ maininit(void)
     timer_setup();
     mathcp_setup();

-    // Initialize mtrr
-    mtrr_setup();
-
     // Initialize pci
     pci_setup();
     smm_init();

+    // Initialize mtrr
+    mtrr_setup();
+
     // Setup Xen hypercalls
     xen_init_hypercalls();

[PATCH 02/20] seabios: acpi, fadt: make while fadt initialization chipset specific

[Gerd Hoffmann]

From: Isaku Yamahata

make while fadt initialization chipset specific.

Reviewed-by: Paolo Bonzini 
Signed-off-by: Isaku Yamahata 
Signed-off-by: Jason Baron 
---
 src/acpi.c |   34 ++++++++++++++++++----------------
 1 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/acpi.c b/src/acpi.c
index 6d239fa..1fc170f 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -233,13 +233,31 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
 #define PIIX4_GPE0_BLK          0xafe0
 #define PIIX4_GPE0_BLK_LEN      4

+#define PIIX4_PM_INTRRUPT       9       // irq 9
+
 static void piix4_fadt_init(struct pci_device *pci, void *arg)
 {
     struct fadt_descriptor_rev1 *fadt = arg;
+
+    fadt->model = 1;
+    fadt->reserved1 = 0;
+    fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT);
+    fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
     fadt->acpi_enable = PIIX4_ACPI_ENABLE;
     fadt->acpi_disable = PIIX4_ACPI_DISABLE;
+    fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
+    fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
+    fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
     fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
+    fadt->pm1_evt_len = 4;
+    fadt->pm1_cnt_len = 2;
+    fadt->pm_tmr_len = 4;
     fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
+    fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+    fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+    /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
+    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) |
+                              (1 << 15));
 }

static const struct pci_device_id fadt_init_tbl[] = {
@@ -281,23 +299,7 @@ build_fadt(struct pci_device *pci)
     fadt->firmware_ctrl = cpu_to_le32((u32)facs);
     fadt->dsdt = 0;  /* dsdt will be filled later in acpi_bios_init()
                         by fill_dsdt() */
-    fadt->model = 1;
-    fadt->reserved1 = 0;
-    int pm_sci_int = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE);
-    fadt->sci_int = cpu_to_le16(pm_sci_int);
-    fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
-    fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
-    fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
-    fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
-    fadt->pm1_evt_len = 4;
-    fadt->pm1_cnt_len = 2;
-    fadt->pm_tmr_len = 4;
-    fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
-    fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
     pci_init_device(fadt_init_tbl, pci, fadt);
-    /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
-    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) |
-                              (1 << 15));

build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);

[PATCH 03/20] seabios: pci: enable SERR of normal device.

[Gerd Hoffmann]

From: Isaku Yamahata

enable SERR of normal device for AER.

Reviewed-by: Paolo Bonzini 
Signed-off-by: Isaku Yamahata 
Signed-off-by: Jason Baron 
---
 src/pciinit.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/pciinit.c b/src/pciinit.c
index 0e87ab0..b322848 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -213,7 +213,8 @@ static void pci_bios_init_device(struct pci_device *pci)
     pci_init_device(pci_device_tbl, pci, NULL);

/* enable memory mappings */
-    pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+    pci_config_maskw(bdf, PCI_COMMAND, 0,
+                     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
 }

static void pci_bios_init_devices(void)

[PATCH 04/20] seabios: add q35 initialization functions.

[Gerd Hoffmann]

From: Isaku Yamahata

add q35 initialization functions.

[[e-mail]: restructured to current seabios base, updated pci base to 0xb0000000]
[[e-mail]: join the two lpc init funcs into one]

Signed-off-by: Isaku Yamahata 
Signed-off-by: Jason Baron 
Signed-off-by: Gerd Hoffmann 
---
 src/acpi.c    |   32 ++++++++++++++++++++-
 src/dev-q35.h |   46 +++++++++++++++++++++++++++++++
 src/pciinit.c |   84 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 src/shadow.c  |   13 +++++++++
 src/smm.c     |   37 +++++++++++++++++++++++++
 5 files changed, 207 insertions(+), 5 deletions(-)
 create mode 100644 src/dev-q35.h

diff --git a/src/acpi.c b/src/acpi.c
index 1fc170f..72c8fe8 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -13,6 +13,7 @@
 #include "pci_regs.h" // PCI_INTERRUPT_LINE
 #include "ioport.h" // inl
 #include "paravirt.h" // qemu_cfg_irq0_override
+#include "dev-q35.h" // qemu_cfg_irq0_override

/****************************************************/
 /* ACPI tables init */
@@ -260,11 +261,38 @@ static void piix4_fadt_init(struct pci_device *pci, void *arg)
                               (1 << 15));
 }

+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void ich9_lpc_fadt_init(struct pci_device *dev, void *arg)
+{
+    struct fadt_descriptor_rev1 *fadt = arg;
+
+    fadt->model = 1;
+    fadt->reserved1 = 0;
+    fadt->sci_int = cpu_to_le16(9);
+    fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
+    fadt->acpi_enable = ICH9_ACPI_ENABLE;
+    fadt->acpi_disable = ICH9_ACPI_DISABLE;
+    fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
+    fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
+    fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
+    fadt->gpe0_blk = cpu_to_le32(PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS);
+    fadt->pm1_evt_len = 4;
+    fadt->pm1_cnt_len = 2;
+    fadt->pm_tmr_len = 4;
+    fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN;
+    fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+    fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+    /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
+    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) |
+                              (1 << 7));
+}
+
 static const struct pci_device_id fadt_init_tbl[] = {
     /* PIIX4 Power Management device (for ACPI) */
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
                piix4_fadt_init),
-
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+               ich9_lpc_fadt_init),
     PCI_DEVICE_END
 };

@@ -739,7 +767,7 @@ build_srat(void)
 static const struct pci_device_id acpi_find_tbl[] = {
     /* PIIX4 Power Management device. */
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
-
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, NULL),
     PCI_DEVICE_END,
 };

diff --git a/src/dev-q35.h b/src/dev-q35.h
new file mode 100644
index 0000000..6ae039f
--- /dev/null
+++ b/src/dev-q35.h
@@ -0,0 +1,46 @@
+#ifndef __DEV_Q35_H
+#define __DEV_Q35_H
+
+#include "types.h"      // u16
+
+#define PCI_DEVICE_ID_INTEL_Q35_MCH     0x29c0
+#define Q35_HOST_BRIDGE_PAM0            0x90
+#define Q35_HOST_BRIDGE_SMRAM           0x9d
+#define Q35_HOST_BRIDGE_PCIEXBAR        0x60
+#define Q35_HOST_BRIDGE_PCIEXBAR_SIZE   (256 * 1024 * 1024)
+#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR   0xb0000000
+#define Q35_HOST_BRIDGE_PCIEXBAREN      ((u64)1)
+#define Q35_HOST_PCIE_PCI_SEGMENT       0
+#define Q35_HOST_PCIE_START_BUS_NUMBER  0
+#define Q35_HOST_PCIE_END_BUS_NUMBER    255
+
+#define PCI_DEVICE_ID_INTEL_ICH9_LPC    0x2918
+#define ICH9_LPC_PMBASE                 0x40
+#define ICH9_LPC_PMBASE_RTE             0x1
+
+#define ICH9_LPC_ACPI_CTRL             0x44
+#define ICH9_LPC_ACPI_CTRL_ACPI_EN     0x80
+#define ICH9_LPC_PIRQA_ROUT            0x60
+#define ICH9_LPC_PIRQE_ROUT            0x68
+#define ICH9_LPC_PIRQ_ROUT_IRQEN       0x80
+#define ICH9_LPC_PORT_ELCR1            0x4d0
+#define ICH9_LPC_PORT_ELCR2            0x4d1
+#define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930
+#define ICH9_SMB_SMB_BASE              0x20
+#define ICH9_SMB_HOSTC                 0x40
+#define ICH9_SMB_HOSTC_HST_EN          0x01
+
+#define ICH9_ACPI_ENABLE               0x2
+#define ICH9_ACPI_DISABLE              0x3
+
+/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
+#define ICH9_PMIO_GPE0_STS             0x20
+#define ICH9_PMIO_GPE0_BLK_LEN         0x10
+#define ICH9_PMIO_SMI_EN               0x30
+#define ICH9_PMIO_SMI_EN_APMC_EN       (1 << 5)
+
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define ICH9_APM_ACPI_ENABLE           0x2
+#define ICH9_APM_ACPI_DISABLE          0x3
+
+#endif // dev-q35.h
diff --git a/src/pciinit.c b/src/pciinit.c
index b322848..a406bbd 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -12,6 +12,11 @@
 #include "ioport.h" // PORT_ATA1_CMD_BASE
 #include "config.h" // CONFIG_*
 #include "xen.h" // usingXen
+#include "memmap.h" // add_e820
+#include "dev-q35.h"
+
+/* PM Timer ticks per second (HZ) */
+#define PM_TIMER_FREQUENCY  3579545

#define PCI_DEVICE_MEM_MIN     0x1000
 #define PCI_BRIDGE_IO_MIN      0x1000
@@ -119,6 +124,45 @@ static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
     dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
 }

+/* ICH9 LPC PCI to ISA bridge */
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void mch_isa_bridge_init(struct pci_device *dev, void *arg)
+{
+    u16 bdf = dev->bdf;
+    int i, irq;
+    u8 elcr[2];
+
+    elcr[0] = 0x00;
+    elcr[1] = 0x00;
+
+    for (i = 0; i < 4; i++) {
+        irq = pci_irqs[i];
+        /* set to trigger level */
+        elcr[irq >> 3] |= (1 << (irq & 7));
+
+        /* activate irq remapping in LPC */
+
+        /* PIRQ[A-D] routing */
+        pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i,
+                          irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+        /* PIRQ[E-H] routing */
+        pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i,
+                          irq | ICH9_LPC_PIRQ_ROUT_IRQEN);
+    }
+    outb(elcr[0], ICH9_LPC_PORT_ELCR1);
+    outb(elcr[1], ICH9_LPC_PORT_ELCR2);
+    dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
+
+    /* pm io base */
+    pci_config_writel(bdf, ICH9_LPC_PMBASE,
+                      PORT_ACPI_PM_BASE | ICH9_LPC_PMBASE_RTE);
+
+    /* acpi enable, SCI: IRQ9 000b = irq9*/
+    pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
+
+    pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
+}
+
 static void storage_ide_init(struct pci_device *pci, void *arg)
 {
     /* IDE: we map it as in ISA mode */
@@ -148,9 +192,6 @@ static void apple_macio_init(struct pci_device *pci, void *arg)
     pci_set_io_region_addr(pci, 0, 0x80800000, 0);
 }

-/* PM Timer ticks per second (HZ) */
-#define PM_TIMER_FREQUENCY  3579545
-
 /* PIIX4 Power Management device (for ACPI) */
 static void piix4_pm_init(struct pci_device *pci, void *arg)
 {
@@ -166,12 +207,27 @@ static void piix4_pm_init(struct pci_device *pci, void *arg)
     pmtimer_init(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
 }

+/* ICH9 SMBUS */
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
+void ich9_smbus_init(struct pci_device *dev, void *arg)
+{
+    u16 bdf = dev->bdf;
+    /* map smbus into io space */
+    pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
+                      PORT_SMB_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+    /* enable SMBus */
+    pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
+}
+
 static const struct pci_device_id pci_device_tbl[] = {
     /* PIIX3/PIIX4 PCI to ISA bridge */
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
                piix_isa_bridge_init),
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
                piix_isa_bridge_init),
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+               mch_isa_bridge_init),

/* STORAGE IDE */
     PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
@@ -190,6 +246,8 @@ static const struct pci_device_id pci_device_tbl[] = {
     /* PIIX4 Power Management device (for ACPI) */
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
                piix4_pm_init),
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
+               ich9_smbus_init),

/* 0xff00 */
     PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
@@ -238,9 +296,29 @@ void i440fx_mem_addr_init(struct pci_device *dev, void *arg)
         pcimem_start = 0xc0000000;
 }

+void mch_mem_addr_init(struct pci_device *dev, void *arg)
+{
+    u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+    u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
+
+    /* setup mmconfig */
+    u16 bdf = dev->bdf;
+    u32 upper = addr >> 32;
+    u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
+    pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
+    pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
+    pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
+    add_e820(addr, size, E820_RESERVED);
+
+    /* setup pci i/o window (above mmconfig) */
+    pcimem_start = addr + size;
+}
+
 static const struct pci_device_id pci_platform_tbl[] = {
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
                i440fx_mem_addr_init),
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
+               mch_mem_addr_init),
     PCI_DEVICE_END
 };

diff --git a/src/shadow.c b/src/shadow.c
index 11c4d5e..a2195da 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -11,6 +11,7 @@
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
 #include "pci_regs.h" // PCI_VENDOR_ID
 #include "xen.h" // usingXen
+#include "dev-q35.h" // PCI_VENDOR_ID_INTEL

// On the emulators, the bios at 0xf0000 is also at 0xffff0000
 #define BIOS_SRC_OFFSET 0xfff00000
@@ -101,9 +102,16 @@ static void i440fx_bios_make_readonly(struct pci_device *pci, void *arg)
     make_bios_readonly_intel(pci->bdf, I440FX_PAM0);
 }

+void mch_bios_make_readonly(struct pci_device *pci, void *arg)
+{
+    make_bios_readonly_intel(pci->bdf, Q35_HOST_BRIDGE_PAM0);
+}
+
 static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
                i440fx_bios_make_readonly),
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
+               mch_bios_make_readonly),
     PCI_DEVICE_END
 };

@@ -127,6 +135,11 @@ make_bios_writable(void)
             make_bios_writable_intel(bdf, I440FX_PAM0);
             return;
         }
+        if (vendor == PCI_VENDOR_ID_INTEL
+            && device == PCI_DEVICE_ID_INTEL_Q35_MCH) {
+            make_bios_writable_intel(bdf, Q35_HOST_BRIDGE_PAM0);
+            return;
+        }
     }
     dprintf(1, "Unable to unlock ram - bridge not found\n");
 }
diff --git a/src/smm.c b/src/smm.c
index d0d1476..7977ac7 100644
--- a/src/smm.c
+++ b/src/smm.c
@@ -11,6 +11,7 @@
 #include "ioport.h" // outb
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
 #include "xen.h" // usingXen
+#include "dev-q35.h"

ASM32FLAT(
     ".global smm_relocation_start\n"
@@ -137,9 +138,45 @@ static void piix4_apmc_smm_init(struct pci_device *pci, void *arg)
     pci_config_writeb(i440_pci->bdf, I440FX_SMRAM, 0x02 | 0x08);
 }

+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void ich9_lpc_apmc_smm_init(struct pci_device *dev, void *arg)
+{
+    struct pci_device *mch_dev;
+    int mch_bdf;
+
+    // This code is hardcoded for Q35 Power Management device.
+    mch_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+                              PCI_DEVICE_ID_INTEL_Q35_MCH);
+    mch_bdf = mch_dev->bdf;
+
+    if (mch_bdf < 0)
+        return;
+
+    /* check if SMM init is already done */
+    u32 value = inl(PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN);
+    if (value & ICH9_PMIO_SMI_EN_APMC_EN)
+        return;
+
+    /* enable the SMM memory window */
+    pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x48);
+
+    smm_save_and_copy();
+
+    /* enable SMI generation when writing to the APMC register */
+    outl(value | ICH9_PMIO_SMI_EN_APMC_EN,
+         PORT_ACPI_PM_BASE + ICH9_PMIO_SMI_EN);
+
+    smm_relocate_and_restore();
+
+    /* close the SMM memory window and enable normal SMM */
+    pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x08);
+}
+
 static const struct pci_device_id smm_init_tbl[] = {
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
                piix4_apmc_smm_init),
+    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
+               ich9_lpc_apmc_smm_init),

PCI_DEVICE_END,
 };

[PATCH 05/20] simplify chipset detection

[Gerd Hoffmann]

Just set a global variable in the first chipset detection
function (pci_bios_init_platform) and use them later on.

Signed-off-by: Gerd Hoffmann 
---
 src/acpi.c    |   39 ++++++++++-----------------------------
 src/pci.h     |    2 ++
 src/pciinit.c |    7 +++++++
 3 files changed, 19 insertions(+), 29 deletions(-)

diff --git a/src/acpi.c b/src/acpi.c
index 72c8fe8..350b55b 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -236,10 +236,8 @@ build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)

#define PIIX4_PM_INTRRUPT       9       // irq 9

-static void piix4_fadt_init(struct pci_device *pci, void *arg)
+static void piix4_fadt_init(struct fadt_descriptor_rev1 *fadt)
 {
-    struct fadt_descriptor_rev1 *fadt = arg;
-
     fadt->model = 1;
     fadt->reserved1 = 0;
     fadt->sci_int = cpu_to_le16(PIIX4_PM_INTRRUPT);
@@ -262,10 +260,8 @@ static void piix4_fadt_init(struct pci_device *pci, void *arg)
 }

/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
-void ich9_lpc_fadt_init(struct pci_device *dev, void *arg)
+void ich9_lpc_fadt_init(struct fadt_descriptor_rev1 *fadt)
 {
-    struct fadt_descriptor_rev1 *fadt = arg;
-
     fadt->model = 1;
     fadt->reserved1 = 0;
     fadt->sci_int = cpu_to_le16(9);
@@ -287,15 +283,6 @@ void ich9_lpc_fadt_init(struct pci_device *dev, void *arg)
                               (1 << 7));
 }

-static const struct pci_device_id fadt_init_tbl[] = {
-    /* PIIX4 Power Management device (for ACPI) */
-    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
-               piix4_fadt_init),
-    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
-               ich9_lpc_fadt_init),
-    PCI_DEVICE_END
-};
-
 static void fill_dsdt(struct fadt_descriptor_rev1 *fadt, void *dsdt)
 {
     if (fadt->dsdt) {
@@ -307,7 +294,7 @@ static void fill_dsdt(struct fadt_descriptor_rev1 *fadt, void *dsdt)
 }

static void *
-build_fadt(struct pci_device *pci)
+build_fadt(void)
 {
     struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
     struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
@@ -327,7 +314,10 @@ build_fadt(struct pci_device *pci)
     fadt->firmware_ctrl = cpu_to_le32((u32)facs);
     fadt->dsdt = 0;  /* dsdt will be filled later in acpi_bios_init()
                         by fill_dsdt() */
-    pci_init_device(fadt_init_tbl, pci, fadt);
+    if (have_piix4)
+        piix4_fadt_init(fadt);
+    if (have_ich9)
+        ich9_lpc_fadt_init(fadt);

build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);

@@ -764,13 +754,6 @@ build_srat(void)
     return srat;
 }

-static const struct pci_device_id acpi_find_tbl[] = {
-    /* PIIX4 Power Management device. */
-    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
-    PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC, NULL),
-    PCI_DEVICE_END,
-};
-
 struct rsdp_descriptor *RsdpAddr;

#define MAX_ACPI_TABLES 20
@@ -782,10 +765,8 @@ acpi_bios_init(void)

dprintf(3, "init ACPI tables\n");

-    // This code is hardcoded for PIIX4 Power Management device.
-    struct pci_device *pci = pci_find_init_device(acpi_find_tbl, NULL);
-    if (!pci)
-        // Device not found
+    // This code is hardcoded for PIIX4/ICH9 Power Management device.
+    if (!have_piix4 && !have_ich9)
         return;

// Build ACPI tables
@@ -798,7 +779,7 @@ acpi_bios_init(void)
             tbl_idx++;                                       \
     } while(0)

-    struct fadt_descriptor_rev1 *fadt = build_fadt(pci);
+    struct fadt_descriptor_rev1 *fadt = build_fadt();
     ACPI_INIT_TABLE(fadt);
     ACPI_INIT_TABLE(build_ssdt());
     ACPI_INIT_TABLE(build_madt());
diff --git a/src/pci.h b/src/pci.h
index fe663b8..007dbaa 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -56,6 +56,8 @@ struct pci_device {
     // Local information on device.
     int have_driver;
 };
+extern u32 have_piix4;
+extern u32 have_ich9;
 extern u64 pcimem_start, pcimem_end;
 extern u64 pcimem64_start, pcimem64_end;
 extern struct pci_device *PCIDevices;
diff --git a/src/pciinit.c b/src/pciinit.c
index a406bbd..4df9fc3 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -40,6 +40,9 @@ u64 pcimem_end     = BUILD_PCIMEM_END;
 u64 pcimem64_start = BUILD_PCIMEM64_START;
 u64 pcimem64_end   = BUILD_PCIMEM64_END;

+u32 have_piix4     = 0;
+u32 have_ich9      = 0;
+
 struct pci_region_entry {
     struct pci_device *dev;
     int bar;
@@ -290,6 +293,8 @@ static void pci_bios_init_devices(void)

void i440fx_mem_addr_init(struct pci_device *dev, void *arg)
 {
+    have_piix4 = 1;
+
     if (RamSize <= 0x80000000)
         pcimem_start = 0x80000000;
     else if (RamSize <= 0xc0000000)
@@ -298,6 +303,8 @@ void i440fx_mem_addr_init(struct pci_device *dev, void *arg)

void mch_mem_addr_init(struct pci_device *dev, void *arg)
 {
+    have_ich9 = 1;
+
     u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
     u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;

[PATCH 06/20] acpi: add mcfg table for mmconfig

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/acpi.c |   23 +++++++++++++++++++++++
 src/acpi.h |   17 +++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/src/acpi.c b/src/acpi.c
index 350b55b..86fe501 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -754,6 +754,27 @@ build_srat(void)
     return srat;
 }

+static void *
+build_mcfg_q35(void)
+{
+    struct acpi_table_mcfg *mcfg;
+
+    int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
+    mcfg = malloc_high(len);
+    if (!mcfg) {
+        warn_noalloc();
+        return NULL;
+    }
+    memset(mcfg, 0, len);
+    mcfg->allocation[0].address = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+    mcfg->allocation[0].pci_segment = Q35_HOST_PCIE_PCI_SEGMENT;
+    mcfg->allocation[0].start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER;
+    mcfg->allocation[0].end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER;
+
+    build_header((void *)mcfg, MCFG_SIGNATURE, len, 1);
+    return mcfg;
+}
+
 struct rsdp_descriptor *RsdpAddr;

#define MAX_ACPI_TABLES 20
@@ -785,6 +806,8 @@ acpi_bios_init(void)
     ACPI_INIT_TABLE(build_madt());
     ACPI_INIT_TABLE(build_hpet());
     ACPI_INIT_TABLE(build_srat());
+    if (have_ich9)
+        ACPI_INIT_TABLE(build_mcfg_q35());

u16 i, external_tables = qemu_cfg_acpi_additional_tables();

diff --git a/src/acpi.h b/src/acpi.h
index cb21561..715d19d 100644
--- a/src/acpi.h
+++ b/src/acpi.h
@@ -107,4 +107,21 @@ struct bfld {
     u64 p1l;  /* pci window 1 (above 4g) - length */
 } PACKED;

+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct acpi_mcfg_allocation {
+    u64 address;                /* Base address, processor-relative */
+    u16 pci_segment;            /* PCI segment group number */
+    u8 start_bus_number;       /* Starting PCI Bus number */
+    u8 end_bus_number;         /* Final PCI Bus number */
+    u32 reserved;
+} PACKED;
+
+#define MCFG_SIGNATURE 0x4746434d       // MCFG
+struct acpi_table_mcfg {
+    ACPI_TABLE_HEADER_DEF;
+    u8 reserved[8];
+    struct acpi_mcfg_allocation allocation[0];
+} PACKED;
+
 #endif // acpi.h

[PATCH 06/20] acpi: add mcfg table for mmconfig

[Kevin O'Connor]

On Wed, Nov 28, 2012 at 10:17:35AM +0100, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann

How about the below (untested) instead of patch 5/6?

-Kevin
> From 7e269b47cb46a16baa03a184553f780b4eb3dc2b Mon Sep 17 00:00:00 2001

From: Gerd Hoffmann 
Date: Wed, 28 Nov 2012 10:17:35 +0100
Subject: [PATCH] acpi: add mcfg table for mmconfig
To: [e-mail]

Signed-off-by: Gerd Hoffmann 
Signed-off-by: Kevin O'Connor 
---
 src/acpi.c | 23 +++++++++++++++++++++++
 src/acpi.h | 17 +++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/src/acpi.c b/src/acpi.c
index 72c8fe8..6267d7b 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -764,6 +764,27 @@ build_srat(void)
     return srat;
 }

+static void *
+build_mcfg_q35(void)
+{
+    struct acpi_table_mcfg *mcfg;
+
+    int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
+    mcfg = malloc_high(len);
+    if (!mcfg) {
+        warn_noalloc();
+        return NULL;
+    }
+    memset(mcfg, 0, len);
+    mcfg->allocation[0].address = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
+    mcfg->allocation[0].pci_segment = Q35_HOST_PCIE_PCI_SEGMENT;
+    mcfg->allocation[0].start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER;
+    mcfg->allocation[0].end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER;
+
+    build_header((void *)mcfg, MCFG_SIGNATURE, len, 1);
+    return mcfg;
+}
+
 static const struct pci_device_id acpi_find_tbl[] = {
     /* PIIX4 Power Management device. */
     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
@@ -804,6 +825,8 @@ acpi_bios_init(void)
     ACPI_INIT_TABLE(build_madt());
     ACPI_INIT_TABLE(build_hpet());
     ACPI_INIT_TABLE(build_srat());
+    if (pci->device == PCI_DEVICE_ID_INTEL_ICH9_LPC)
+        ACPI_INIT_TABLE(build_mcfg_q35());

u16 i, external_tables = qemu_cfg_acpi_additional_tables();

diff --git a/src/acpi.h b/src/acpi.h
index cb21561..715d19d 100644
--- a/src/acpi.h
+++ b/src/acpi.h
@@ -107,4 +107,21 @@ struct bfld {
     u64 p1l;  /* pci window 1 (above 4g) - length */
 } PACKED;

+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct acpi_mcfg_allocation {
+    u64 address;                /* Base address, processor-relative */
+    u16 pci_segment;            /* PCI segment group number */
+    u8 start_bus_number;       /* Starting PCI Bus number */
+    u8 end_bus_number;         /* Final PCI Bus number */
+    u32 reserved;
+} PACKED;
+
+#define MCFG_SIGNATURE 0x4746434d       // MCFG
+struct acpi_table_mcfg {
+    ACPI_TABLE_HEADER_DEF;
+    u8 reserved[8];
+    struct acpi_mcfg_allocation allocation[0];
+} PACKED;
+
 #endif // acpi.h

[PATCH 06/20] acpi: add mcfg table for mmconfig

[Gerd Hoffmann]

On 12/02/12 05:41, Kevin O'Connor wrote:
> On Wed, Nov 28, 2012 at 10:17:35AM +0100, Gerd Hoffmann wrote:
> > Signed-off-by: Gerd Hoffmann
>
> How about the below (untested) instead of patch 5/6?

Fine with me.

cheers,
  Gerd

[PATCH 07/20] seabios: q35: add dsdt

[Gerd Hoffmann]

From: Isaku Yamahata

add dsdt for q35 chipset of qemu.

[jbaron: remove suspd bits since they are now auto-generated, move pci window to 0xb0000000,
    add framework for auto generated pci windows]
[kraxel: remove pci express root ports + pci bridge]

Cc: Matthew Garrett 
Signed-off-by: Isaku Yamahata 
Signed-off-by: Jason Baron 
---
 Makefile              |    2 +-
 src/q35-acpi-dsdt.dsl |  830 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 831 insertions(+), 1 deletions(-)
 create mode 100644 src/q35-acpi-dsdt.dsl

diff --git a/Makefile b/Makefile
index b0e2031..8e32670 100644
--- a/Makefile
+++ b/Makefile
@@ -233,7 +233,7 @@ $(OUT)%.hex: src/%.dsl ./tools/acpi_extract_preprocess.py ./tools/acpi_extract.p
    $(Q)$(PYTHON) ./tools/acpi_extract.py $(OUT)$*.lst > $(OUT)$*.off
    $(Q)cat $(OUT)$*.off > $@

-$(OUT)ccode32flat.o: $(OUT)acpi-dsdt.hex $(OUT)ssdt-proc.hex $(OUT)ssdt-pcihp.hex $(OUT)ssdt-susp.hex
+$(OUT)ccode32flat.o: $(OUT)acpi-dsdt.hex $(OUT)ssdt-proc.hex $(OUT)ssdt-pcihp.hex $(OUT)ssdt-susp.hex $(OUT)q35-acpi-dsdt.hex

################ Kconfig rules

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
new file mode 100644
index 0000000..4b4f291
--- /dev/null
+++ b/src/q35-acpi-dsdt.dsl
@@ -0,0 +1,830 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+ * Copyright (c) 2010 Isaku Yamahata
+ *                    yamahata at valinux co jp
+ * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
+ */
+
+DefinitionBlock (
+    "q35-acpi-dsdt.aml",// Output Filename
+    "DSDT",             // Signature
+    0x01,               // DSDT Compliance Revision
+    "BXPC",             // OEMID
+    "BXDSDT",           // TABLE ID
+    0x2                 // OEM Revision
+    )
+{
+    Scope ()
+    {
+        /* Debug Output */
+        OperationRegion (DBG, SystemIO, 0x0402, 0x01)
+        Field (DBG, ByteAcc, NoLock, Preserve)
+        {
+            DBGB,   8,
+        }
+
+        /* Debug method - use this method to send output to the QEMU
+         * BIOS debug port.  This method handles strings, integers,
+         * and buffers.  For example: DBUG("abc") DBUG(0x123) */
+        Method(DBUG, 1) {
+            ToHexString(Arg0, Local0)
+            ToBuffer(Local0, Local0)
+            Subtract(SizeOf(Local0), 1, Local1)
+            Store(Zero, Local2)
+            While (LLess(Local2, Local1)) {
+                Store(DerefOf(Index(Local0, Local2)), DBGB)
+                Increment(Local2)
+            }
+            Store(0x0A, DBGB)
+        }
+    }
+
+
+    Scope (_SB)
+    {
+        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
+        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
+        Field (PCSB, AnyAcc, NoLock, WriteAsZeros)
+        {
+            PCIB, 8,
+        }
+    }
+
+    /* Zero => PIC mode, One => APIC Mode */
+    Name (\PICF, Zero)
+    Method (_PIC, 1, NotSerialized)
+    {
+        Store (Arg0, \PICF)
+    }
+
+    /* PCI Bus definition */
+    Scope(_SB) {
+
+        Device(PCI0) {
+            Name (_HID, EisaId ("PNP0A08"))
+            Name (_CID, EisaId ("PNP0A03"))
+            Name (_ADR, 0x00)
+            Name (_UID, 1)
+
+            // _OSC: based on sample of ACPI3.0b spec
+            Name(SUPP,0) // PCI _OSC Support Field value
+            Name(CTRL,0) // PCI _OSC Control Field value
+            Method(_OSC,4)
+            {
+                // Create DWORD-addressable fields from the Capabilities Buffer
+                CreateDWordField(Arg3,0,CDW1)
+
+                // Check for proper UUID
+                If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+                {
+                    // Create DWORD-addressable fields from the Capabilities Buffer
+                    CreateDWordField(Arg3,4,CDW2)
+                    CreateDWordField(Arg3,8,CDW3)
+
+                    // Save Capabilities DWORD2 & 3
+                    Store(CDW2,SUPP)
+                    Store(CDW3,CTRL)
+
+                    // Always allow native PME, AER (no dependencies)
+                    // Never allow SHPC (no SHPC controller in this system)
+                    And(CTRL,0x1D,CTRL)
+
+#if 0 // For now, nothing to do
+                    If(Not(And(CDW1,1))) // Query flag clear?
+                    {   // Disable GPEs for features granted native control.
+                        If(And(CTRL,0x01)) // Hot plug control granted?
+                        {
+                            Store(0,HPCE) // clear the hot plug SCI enable bit
+                            Store(1,HPCS) // clear the hot plug SCI status bit
+                        }
+                        If(And(CTRL,0x04)) // PME control granted?
+                        {
+                            Store(0,PMCE) // clear the PME SCI enable bit
+                            Store(1,PMCS) // clear the PME SCI status bit
+                        }
+                        If(And(CTRL,0x10)) // OS restoring PCI Express cap structure?
+                        {
+                            // Set status to not restore PCI Express cap structure
+                            // upon resume from S3
+                            Store(1,S3CR)
+                        }
+
+                    }
+#endif
+                    If(LNotEqual(Arg1,One))
+                    {   // Unknown revision
+                        Or(CDW1,0x08,CDW1)
+                    }
+                    If(LNotEqual(CDW3,CTRL))
+                    {   // Capabilities bits were masked
+                        Or(CDW1,0x10,CDW1)
+                    }
+                    // Update DWORD3 in the buffer
+                    Store(CTRL,CDW3)
+                } Else {
+                    Or(CDW1,4,CDW1) // Unrecognized UUID
+                }
+                Return(Arg3)
+            }
+
+#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
+       Package() { nr##ffff, 0, lnk0, 0 },       \
+       Package() { nr##ffff, 1, lnk1, 0 },       \
+       Package() { nr##ffff, 2, lnk2, 0 },       \
+       Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
+#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
+
+#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
+#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
+#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
+#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
+
+#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
+       Package() { nr##ffff, 0, 0, gsi0 },       \
+       Package() { nr##ffff, 1, 0, gsi1 },       \
+       Package() { nr##ffff, 2, 0, gsi2 },       \
+       Package() { nr##ffff, 3, 0, gsi3 }
+
+#define GSIA    0x10
+#define GSIB    0x11
+#define GSIC    0x12
+#define GSID    0x13
+#define GSIE    0x14
+#define GSIF    0x15
+#define GSIG    0x16
+#define GSIH    0x17
+
+#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
+#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
+#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
+#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
+
+#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
+#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
+#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
+#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
+
+	    NAME(PRTP, package()
+            {
+             prt_slot_lnkE(0x0000),
+             prt_slot_lnkF(0x0001),
+             prt_slot_lnkG(0x0002),
+             prt_slot_lnkH(0x0003),
+             prt_slot_lnkE(0x0004),
+             prt_slot_lnkF(0x0005),
+             prt_slot_lnkG(0x0006),
+             prt_slot_lnkH(0x0007),
+             prt_slot_lnkE(0x0008),
+             prt_slot_lnkF(0x0009),
+             prt_slot_lnkG(0x000a),
+             prt_slot_lnkH(0x000b),
+             prt_slot_lnkE(0x000c),
+             prt_slot_lnkF(0x000d),
+             prt_slot_lnkG(0x000e),
+             prt_slot_lnkH(0x000f),
+             prt_slot_lnkE(0x0010),
+             prt_slot_lnkF(0x0011),
+             prt_slot_lnkG(0x0012),
+             prt_slot_lnkH(0x0013),
+             prt_slot_lnkE(0x0014),
+             prt_slot_lnkF(0x0015),
+             prt_slot_lnkG(0x0016),
+             prt_slot_lnkH(0x0017),
+             prt_slot_lnkE(0x0018),
+
+             /* INTA -> PIRQA for slot 25 - 31
+                see the default value of D<N>IR */
+             prt_slot_lnkA(0x0019),
+             prt_slot_lnkA(0x001a),
+             prt_slot_lnkA(0x001b),
+             prt_slot_lnkA(0x001c),
+             prt_slot_lnkA(0x001d),
+
+             /* PCIe->PCI bridge. use PIRQ[E-H] */
+             prt_slot_lnkE(0x001e),
+
+             prt_slot_lnkA(0x001f)
+            })
+
+	    NAME(PRTA, package()
+            {
+	     prt_slot_gsiE(0x0000),
+	     prt_slot_gsiF(0x0001),
+	     prt_slot_gsiG(0x0002),
+	     prt_slot_gsiH(0x0003),
+	     prt_slot_gsiE(0x0004),
+	     prt_slot_gsiF(0x0005),
+	     prt_slot_gsiG(0x0006),
+	     prt_slot_gsiH(0x0007),
+	     prt_slot_gsiE(0x0008),
+	     prt_slot_gsiF(0x0009),
+	     prt_slot_gsiG(0x000a),
+	     prt_slot_gsiH(0x000b),
+	     prt_slot_gsiE(0x000c),
+	     prt_slot_gsiF(0x000d),
+	     prt_slot_gsiG(0x000e),
+	     prt_slot_gsiH(0x000f),
+	     prt_slot_gsiE(0x0010),
+	     prt_slot_gsiF(0x0011),
+	     prt_slot_gsiG(0x0012),
+	     prt_slot_gsiH(0x0013),
+	     prt_slot_gsiE(0x0014),
+	     prt_slot_gsiF(0x0015),
+	     prt_slot_gsiG(0x0016),
+	     prt_slot_gsiH(0x0017),
+	     prt_slot_gsiE(0x0018),
+
+             /* INTA -> PIRQA for slot 25 - 31, but 30
+	        see the default value of D<N>IR */
+	     prt_slot_gsiA(0x0019),
+	     prt_slot_gsiA(0x001a),
+	     prt_slot_gsiA(0x001b),
+	     prt_slot_gsiA(0x001c),
+	     prt_slot_gsiA(0x001d),
+
+             /* PCIe->PCI bridge. use PIRQ[E-H] */
+	     prt_slot_gsiE(0x001e),
+
+	     prt_slot_gsiA(0x001f)
+	    })
+
+            Method(_PRT, 0, NotSerialized)
+            {
+                /* PCI IRQ routing table, example from ACPI 2.0a specification,
+                   section 6.2.8.1 */
+                /* Note: we provide the same info as the PCI routing
+                   table of the Bochs BIOS */
+                If (LEqual (\PICF, Zero))
+		{
+		 Return (PRTP)
+		}
+                Else
+		{
+		 Return (PRTA)
+		}
+            }
+
+            Name (CRES, ResourceTemplate ()
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000,             // Address Space Granularity
+                    0x0000,             // Address Range Minimum
+                    0x00FF,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0x0100,             // Address Length
+                    ,, )
+                IO (Decode16,
+                    0x0CF8,             // Address Range Minimum
+                    0x0CF8,             // Address Range Maximum
+                    0x01,               // Address Alignment
+                    0x08,               // Address Length
+                    )
+                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x0000,             // Address Space Granularity
+                    0x0000,             // Address Range Minimum
+                    0x0CF7,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0x0CF8,             // Address Length
+                    ,, , TypeStatic)
+                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x0000,             // Address Space Granularity
+                    0x0D00,             // Address Range Minimum
+                    0xFFFF,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0xF300,             // Address Length
+                    ,, , TypeStatic)
+                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                    0x00000000,         // Address Space Granularity
+                    0x000A0000,         // Address Range Minimum
+                    0x000BFFFF,         // Address Range Maximum
+                    0x00000000,         // Address Translation Offset
+                    0x00020000,         // Address Length
+                    ,, , AddressRangeMemory, TypeStatic)
+                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                    0x00000000,         // Address Space Granularity
+                    0xC0000000,         // Address Range Minimum
+                    0xFEBFFFFF,         // Address Range Maximum
+                    0x00000000,         // Address Translation Offset
+                    0x3EC00000,         // Address Length
+                    ,, PW32, AddressRangeMemory, TypeStatic)
+            })
+            Name (CR64, ResourceTemplate ()
+            {
+                QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                    0x00000000,          // Address Space Granularity
+                    0x8000000000,        // Address Range Minimum
+                    0xFFFFFFFFFF,        // Address Range Maximum
+                    0x00000000,          // Address Translation Offset
+                    0x8000000000,        // Address Length
+                    ,, PW64, AddressRangeMemory, TypeStatic)
+            })
+            Method (_CRS, 0)
+            {
+        /* see see acpi.h, struct bfld */
+        External (BDAT, OpRegionObj)
+        Field(BDAT, QWordAcc, NoLock, Preserve) {
+                    P0S, 64,
+                    P0E, 64,
+                    P0L, 64,
+                    P1S, 64,
+                    P1E, 64,
+                    P1L, 64,
+        }
+        Field(BDAT, DWordAcc, NoLock, Preserve) {
+                    P0SL, 32,
+                    P0SH, 32,
+                    P0EL, 32,
+                    P0EH, 32,
+                    P0LL, 32,
+                    P0LH, 32,
+                    P1SL, 32,
+                    P1SH, 32,
+                    P1EL, 32,
+                    P1EH, 32,
+                    P1LL, 32,
+                    P1LH, 32,
+        }
+
+                /* fixup 32bit pci io window */
+        CreateDWordField (CRES,_SB.PCI0.PW32._MIN, PS32)
+        CreateDWordField (CRES,_SB.PCI0.PW32._MAX, PE32)
+        CreateDWordField (CRES,_SB.PCI0.PW32._LEN, PL32)
+        Store (P0SL, PS32)
+        Store (P0EL, PE32)
+        Store (P0LL, PL32)
+
+        If (LAnd(LEqual(P1SL, 0x00), LEqual(P1SH, 0x00))) {
+            Return (CRES)
+        } Else {
+            /* fixup 64bit pci io window */
+            CreateQWordField (CR64,_SB.PCI0.PW64._MIN, PS64)
+            CreateQWordField (CR64,_SB.PCI0.PW64._MAX, PE64)
+            CreateQWordField (CR64,_SB.PCI0.PW64._LEN, PL64)
+            Store (P1S, PS64)
+            Store (P1E, PE64)
+            Store (P1L, PL64)
+            /* add window and return result */
+            ConcatenateResTemplate (CRES, CR64, Local0)
+            Return (Local0)
+        }
+            }
+        }
+    }
+
+    Scope(_SB.PCI0) {
+        Device (VGA) {
+                 Name (_ADR, 0x00020000)
+                 Method (_S1D, 0, NotSerialized)
+                 {
+                         Return (0x00)
+                 }
+                 Method (_S2D, 0, NotSerialized)
+                 {
+                         Return (0x00)
+                 }
+                 Method (_S3D, 0, NotSerialized)
+                 {
+                         Return (0x00)
+                 }
+        }
+
+
+        /* PCI D31:f0 LPC ISA bridge */
+        Device (LPC) {
+            /* PCI D31:f0 */
+            Name (_ADR, 0x001f0000)
+
+            /* ICH9 PCI to ISA irq remapping */
+            OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+            Field (PIRQ, ByteAcc, NoLock, Preserve)
+            {
+                PRQA,   8,
+                PRQB,   8,
+                PRQC,   8,
+                PRQD,   8,
+
+                Offset (0x08),
+                PRQE,   8,
+                PRQF,   8,
+                PRQG,   8,
+                PRQH,   8
+            }
+
+            OperationRegion (LPCD, PCI_Config, 0x80, 0x2)
+            Field (LPCD, AnyAcc, NoLock, Preserve)
+            {
+                COMA,   3,
+                    ,   1,
+                COMB,   3,
+
+                Offset(0x01),
+                LPTD,   2,
+                    ,   2,
+                FDCD,   2
+            }
+            OperationRegion (LPCE, PCI_Config, 0x82, 0x2)
+            Field (LPCE, AnyAcc, NoLock, Preserve)
+            {
+                CAEN,   1,
+                CBEN,   1,
+                LPEN,   1,
+                FDEN,   1
+            }
+
+            /* High Precision Event Timer */
+            Device(HPET) {
+                Name(_HID,  EISAID("PNP0103"))
+                Name(_UID, 0)
+                Method (_STA, 0, NotSerialized) {
+                        Return(0x0F)
+                }
+                Name(_CRS, ResourceTemplate() {
+                    DWordMemory(
+                        ResourceConsumer, PosDecode, MinFixed, MaxFixed,
+                        NonCacheable, ReadWrite,
+                        0x00000000,
+                        0xFED00000,
+                        0xFED003FF,
+                        0x00000000,
+                        0x00000400 /* 1K memory: FED00000 - FED003FF */
+                    )
+                })
+            }
+            /* Real-time clock */
+            Device (RTC)
+            {
+                Name (_HID, EisaId ("PNP0B00"))
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
+                    IRQNoFlags () {8}
+                    IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
+                })
+            }
+
+            /* Keyboard seems to be important for WinXP install */
+            Device (KBD)
+            {
+                Name (_HID, EisaId ("PNP0303"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+
+                Method (_CRS, 0, NotSerialized)
+                {
+                     Name (TMP, ResourceTemplate ()
+                     {
+                    IO (Decode16,
+                        0x0060,             // Address Range Minimum
+                        0x0060,             // Address Range Maximum
+                        0x01,               // Address Alignment
+                        0x01,               // Address Length
+                        )
+                    IO (Decode16,
+                        0x0064,             // Address Range Minimum
+                        0x0064,             // Address Range Maximum
+                        0x01,               // Address Alignment
+                        0x01,               // Address Length
+                        )
+                    IRQNoFlags ()
+                        {1}
+                    })
+                    Return (TMP)
+                }
+            }
+
+	    /* PS/2 mouse */
+            Device (MOU)
+            {
+                Name (_HID, EisaId ("PNP0F13"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (TMP, ResourceTemplate ()
+                    {
+                         IRQNoFlags () {12}
+                    })
+                    Return (TMP)
+                }
+            }
+
+	    /* PS/2 floppy controller */
+	    Device (FDC0)
+	    {
+	        Name (_HID, EisaId ("PNP0700"))
+		Method (_STA, 0, NotSerialized)
+		{
+                    Store (_SB.PCI0.LPC.FDEN, Local0)
+                    If (LEqual (Local0, 0))
+                    {
+                         Return (0x00)
+                    }
+                    Else
+                    {
+                         Return (0x0F)
+                    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+                        IRQNoFlags () {6}
+                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
+                    })
+		    Return (BUF0)
+		}
+	    }
+
+	    /* Parallel port */
+	    Device (LPT)
+	    {
+	        Name (_HID, EisaId ("PNP0400"))
+		Method (_STA, 0, NotSerialized)
+		{
+		    Store (_SB.PCI0.LPC.LPEN, Local0)
+		    If (LEqual (Local0, 0))
+		    {
+			Return (0x00)
+		    }
+		    Else
+		    {
+			Return (0x0F)
+		    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+			IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
+			IRQNoFlags () {7}
+		    })
+		    Return (BUF0)
+		}
+	    }
+
+	    /* Serial Ports */
+	    Device (COM1)
+	    {
+	        Name (_HID, EisaId ("PNP0501"))
+		Name (_UID, 0x01)
+		Method (_STA, 0, NotSerialized)
+		{
+		    Store (_SB.PCI0.LPC.CAEN, Local0)
+		    If (LEqual (Local0, 0))
+		    {
+			Return (0x00)
+		    }
+		    Else
+		    {
+			Return (0x0F)
+		    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+			IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
+                	IRQNoFlags () {4}
+		    })
+		    Return (BUF0)
+		}
+	    }
+
+	    Device (COM2)
+	    {
+	        Name (_HID, EisaId ("PNP0501"))
+		Name (_UID, 0x02)
+		Method (_STA, 0, NotSerialized)
+		{
+		    Store (_SB.PCI0.LPC.CBEN, Local0)
+		    If (LEqual (Local0, 0))
+		    {
+			Return (0x00)
+		    }
+		    Else
+		    {
+			Return (0x0F)
+		    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+			IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
+                	IRQNoFlags () {3}
+		    })
+		    Return (BUF0)
+		}
+	    }
+        }
+    }
+
+    /* PCI IRQs */
+    Scope(_SB) {
+#define define_link(link, uid, reg)                     \
+        Device(link){                                   \
+                Name(_HID, EISAID("PNP0C0F"))           \
+                Name(_UID, uid)                         \
+                Name(_PRS, ResourceTemplate(){          \
+                    Interrupt (, Level, ActiveHigh,     \
+                               Shared)                  \
+                        { 5, 10, 11 }                   \
+                })                                      \
+                Method (_STA, 0, NotSerialized)         \
+                {                                       \
+                    Store (0x0B, Local0)                \
+                    If (And (0x80, reg, Local1))        \
+                    {                                   \
+                         Store (0x09, Local0)           \
+                    }                                   \
+                    Return (Local0)                     \
+                }                                       \
+                Method (_DIS, 0, NotSerialized)         \
+                {                                       \
+                    Or (reg, 0x80, reg)                 \
+                }                                       \
+                Method (_CRS, 0, NotSerialized)         \
+                {                                       \
+                    Name (PRR0, ResourceTemplate ()     \
+                    {                                   \
+                        Interrupt (, Level, ActiveHigh, \
+                                   Shared)              \
+                             {1}                        \
+                    })                                  \
+                    CreateDWordField (PRR0, 0x05, TMP)  \
+                    And (reg, 0x0F, Local0)             \
+                    Store (Local0, TMP)                 \
+                    Return (PRR0)                       \
+                }                                       \
+                Method (_SRS, 1, NotSerialized)         \
+                {                                       \
+                    CreateDWordField (Arg0, 0x05, TMP)  \
+                    Store (TMP, reg)                    \
+                }                                       \
+        }
+
+        define_link(LNKA, 0, _SB.PCI0.LPC.PRQA)
+        define_link(LNKB, 1, _SB.PCI0.LPC.PRQB)
+        define_link(LNKC, 2, _SB.PCI0.LPC.PRQC)
+        define_link(LNKD, 3, _SB.PCI0.LPC.PRQD)
+        define_link(LNKE, 4, _SB.PCI0.LPC.PRQE)
+        define_link(LNKF, 5, _SB.PCI0.LPC.PRQF)
+        define_link(LNKG, 6, _SB.PCI0.LPC.PRQG)
+        define_link(LNKH, 7, _SB.PCI0.LPC.PRQH)
+    }
+
+    /* CPU hotplug */
+    Scope(_SB) {
+        /* Objects filled in by run-time generated SSDT */
+        External(NTFY, MethodObj)
+        External(CPON, PkgObj)
+
+        /* Methods called by run-time generated SSDT Processor objects */
+        Method (CPMA, 1, NotSerialized) {
+            // _MAT method - create an madt apic buffer
+            // Local0 = CPON flag for this cpu
+            Store(DerefOf(Index(CPON, Arg0)), Local0)
+            // Local1 = Buffer (in madt apic form) to return
+            Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
+            // Update the processor id, lapic id, and enable/disable status
+            Store(Arg0, Index(Local1, 2))
+            Store(Arg0, Index(Local1, 3))
+            Store(Local0, Index(Local1, 4))
+            Return (Local1)
+        }
+        Method (CPST, 1, NotSerialized) {
+            // _STA method - return ON status of cpu
+            // Local0 = CPON flag for this cpu
+            Store(DerefOf(Index(CPON, Arg0)), Local0)
+            If (Local0) { Return(0xF) } Else { Return(0x0) }
+        }
+        Method (CPEJ, 2, NotSerialized) {
+            // _EJ0 method - eject callback
+            Sleep(200)
+        }
+
+        /* CPU hotplug notify method */
+        OperationRegion(PRST, SystemIO, 0xaf00, 32)
+        Field (PRST, ByteAcc, NoLock, Preserve)
+        {
+            PRS, 256
+        }
+        Method(PRSC, 0) {
+            // Local5 = active cpu bitmap
+            Store (PRS, Local5)
+            // Local2 = last read byte from bitmap
+            Store (Zero, Local2)
+            // Local0 = cpuid iterator
+            Store (Zero, Local0)
+            While (LLess(Local0, SizeOf(CPON))) {
+                // Local1 = CPON flag for this cpu
+                Store(DerefOf(Index(CPON, Local0)), Local1)
+                If (And(Local0, 0x07)) {
+                    // Shift down previously read bitmap byte
+                    ShiftRight(Local2, 1, Local2)
+                } Else {
+                    // Read next byte from cpu bitmap
+                    Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
+                }
+                // Local3 = active state for this cpu
+                Store(And(Local2, 1), Local3)
+
+                If (LNotEqual(Local1, Local3)) {
+                    // State change - update CPON with new state
+                    Store(Local3, Index(CPON, Local0))
+                    // Do CPU notify
+                    If (LEqual(Local3, 1)) {
+                        NTFY(Local0, 1)
+                    } Else {
+                        NTFY(Local0, 3)
+                    }
+                }
+                Increment(Local0)
+            }
+            Return(One)
+        }
+    }
+
+    Scope (_GPE)
+    {
+        Name(_HID, "ACPI0006")
+
+        Method(_L00) {
+            Return(0x01)
+        }
+        Method(_L01) {
+             // CPU hotplug event
+	     Return(_SB.PRSC())
+        }
+        Method(_L02) {
+            Return(0x01)
+        }
+        Method(_L03) {
+            Return(0x01)
+        }
+        Method(_L04) {
+            Return(0x01)
+        }
+        Method(_L05) {
+            Return(0x01)
+        }
+        Method(_L06) {
+            Return(0x01)
+        }
+        Method(_L07) {
+            Return(0x01)
+        }
+        Method(_L08) {
+            Return(0x01)
+        }
+        Method(_L09) {
+            Return(0x01)
+        }
+        Method(_L0A) {
+            Return(0x01)
+        }
+        Method(_L0B) {
+            Return(0x01)
+        }
+        Method(_L0C) {
+            Return(0x01)
+        }
+        Method(_L0D) {
+            Return(0x01)
+        }
+        Method(_L0E) {
+            Return(0x01)
+        }
+        Method(_L0F) {
+            Return(0x01)
+        }
+    }
+}

[PATCH 08/20] seabios: q35: Register PCI IRQs as active high in APIC mode

[Gerd Hoffmann]

From: Jan Kiszka

Seems important for Windows.

Reviewed-by: Paolo Bonzini 
Signed-off-by: Jan Kiszka 
Signed-off-by: Jason Baron 
---
 src/q35-acpi-dsdt.dsl |   46 +++++++++++++++++++++++++++++++++-------------
 1 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index 4b4f291..126081c 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -161,19 +161,10 @@ DefinitionBlock (
 #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)

#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
-       Package() { nr##ffff, 0, 0, gsi0 },       \
-       Package() { nr##ffff, 1, 0, gsi1 },       \
-       Package() { nr##ffff, 2, 0, gsi2 },       \
-       Package() { nr##ffff, 3, 0, gsi3 }
-
-#define GSIA    0x10
-#define GSIB    0x11
-#define GSIC    0x12
-#define GSID    0x13
-#define GSIE    0x14
-#define GSIF    0x15
-#define GSIG    0x16
-#define GSIH    0x17
+       Package() { nr##ffff, 0, gsi0, 0 },       \
+       Package() { nr##ffff, 1, gsi1, 0 },       \
+       Package() { nr##ffff, 2, gsi2, 0 },       \
+       Package() { nr##ffff, 3, gsi3, 0 }

#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
 #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
@@ -699,6 +690,35 @@ DefinitionBlock (
         define_link(LNKF, 5, _SB.PCI0.LPC.PRQF)
         define_link(LNKG, 6, _SB.PCI0.LPC.PRQG)
         define_link(LNKH, 7, _SB.PCI0.LPC.PRQH)
+
+#define define_gsi_link(link, uid, gsi)                 \
+        Device(link){                                   \
+                Name(_HID, EISAID("PNP0C0F"))           \
+                Name(_UID, uid)                         \
+                Name(_PRS, ResourceTemplate() {         \
+                    Interrupt (, Level, ActiveHigh,     \
+                               Shared)                  \
+                        { gsi }                         \
+                })                                      \
+                Method (_CRS, 0, NotSerialized)         \
+                {                                       \
+                    Return (ResourceTemplate () {       \
+                        Interrupt (, Level, ActiveHigh, \
+                                   Shared)              \
+                             { gsi }                    \
+                    })                                  \
+                }                                       \
+                Method (_SRS, 1, NotSerialized) { }     \
+        }                                               \
+
+        define_gsi_link(GSIA, 0, 0x10)
+        define_gsi_link(GSIB, 0, 0x11)
+        define_gsi_link(GSIC, 0, 0x12)
+        define_gsi_link(GSID, 0, 0x13)
+        define_gsi_link(GSIE, 0, 0x14)
+        define_gsi_link(GSIF, 0, 0x15)
+        define_gsi_link(GSIG, 0, 0x16)
+        define_gsi_link(GSIH, 0, 0x17)
     }

/* CPU hotplug */

[PATCH 09/20] acpi: move DBUG() to separate file

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt-dbug.dsl |   30 ++++++++++++++++++++++++++++++
 src/acpi-dsdt.dsl      |   31 +------------------------------
 2 files changed, 31 insertions(+), 30 deletions(-)
 create mode 100644 src/acpi-dsdt-dbug.dsl

diff --git a/src/acpi-dsdt-dbug.dsl b/src/acpi-dsdt-dbug.dsl
new file mode 100644
index 0000000..ce6fd6e
--- /dev/null
+++ b/src/acpi-dsdt-dbug.dsl
@@ -0,0 +1,30 @@
+/****************************************************************
+ * Debugging
+ ****************************************************************/
+
+    Scope ()
+    {
+        /* Debug Output */
+        OperationRegion (DBG, SystemIO, 0x0402, 0x01)
+        Field (DBG, ByteAcc, NoLock, Preserve)
+        {
+            DBGB,   8,
+        }
+
+        /* Debug method - use this method to send output to the QEMU
+         * BIOS debug port.  This method handles strings, integers,
+         * and buffers.  For example: DBUG("abc") DBUG(0x123) */
+        Method(DBUG, 1) {
+            ToHexString(Arg0, Local0)
+            ToBuffer(Local0, Local0)
+            Subtract(SizeOf(Local0), 1, Local1)
+            Store(Zero, Local2)
+            While (LLess(Local2, Local1)) {
+                Store(DerefOf(Index(Local0, Local2)), DBGB)
+                Increment(Local2)
+            }
+            Store(0x0A, DBGB)
+        }
+    }
+
+
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 711302e..853648c 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -29,36 +29,7 @@ DefinitionBlock (
     )
 {

-
-/****************************************************************
- * Debugging
- ****************************************************************/
-
-    Scope ()
-    {
-        /* Debug Output */
-        OperationRegion (DBG, SystemIO, 0x0402, 0x01)
-        Field (DBG, ByteAcc, NoLock, Preserve)
-        {
-            DBGB,   8,
-        }
-
-        /* Debug method - use this method to send output to the QEMU
-         * BIOS debug port.  This method handles strings, integers,
-         * and buffers.  For example: DBUG("abc") DBUG(0x123) */
-        Method(DBUG, 1) {
-            ToHexString(Arg0, Local0)
-            ToBuffer(Local0, Local0)
-            Subtract(SizeOf(Local0), 1, Local1)
-            Store(Zero, Local2)
-            While (LLess(Local2, Local1)) {
-                Store(DerefOf(Index(Local0, Local2)), DBGB)
-                Increment(Local2)
-            }
-            Store(0x0A, DBGB)
-        }
-    }
-
+#include "acpi-dsdt-dbug.dsl"

/****************************************************************
  * PCI Bus definition

[PATCH 10/20] acpi: move DBUG() to separate file [q35]

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/q35-acpi-dsdt.dsl |   25 +------------------------
 1 files changed, 1 insertions(+), 24 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index 126081c..e61f142 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -31,31 +31,8 @@ DefinitionBlock (
     0x2                 // OEM Revision
     )
 {
-    Scope ()
-    {
-        /* Debug Output */
-        OperationRegion (DBG, SystemIO, 0x0402, 0x01)
-        Field (DBG, ByteAcc, NoLock, Preserve)
-        {
-            DBGB,   8,
-        }
-
-        /* Debug method - use this method to send output to the QEMU
-         * BIOS debug port.  This method handles strings, integers,
-         * and buffers.  For example: DBUG("abc") DBUG(0x123) */
-        Method(DBUG, 1) {
-            ToHexString(Arg0, Local0)
-            ToBuffer(Local0, Local0)
-            Subtract(SizeOf(Local0), 1, Local1)
-            Store(Zero, Local2)
-            While (LLess(Local2, Local1)) {
-                Store(DerefOf(Index(Local0, Local2)), DBGB)
-                Increment(Local2)
-            }
-            Store(0x0A, DBGB)
-        }
-    }

+#include "acpi-dsdt-dbug.dsl"

Scope (_SB)
     {

[PATCH 11/20] acpi: move \_SB.HPET to separate file

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt-hpet.dsl |   36 ++++++++++++++++++++++++++++++++++++
 src/acpi-dsdt.dsl      |   37 +------------------------------------
 2 files changed, 37 insertions(+), 36 deletions(-)
 create mode 100644 src/acpi-dsdt-hpet.dsl

diff --git a/src/acpi-dsdt-hpet.dsl b/src/acpi-dsdt-hpet.dsl
new file mode 100644
index 0000000..06ec7a3
--- /dev/null
+++ b/src/acpi-dsdt-hpet.dsl
@@ -0,0 +1,36 @@
+/****************************************************************
+ * HPET
+ ****************************************************************/
+
+    Scope(_SB) {
+        Device(HPET) {
+            Name(_HID,  EISAID("PNP0103"))
+            Name(_UID, 0)
+            OperationRegion(HPTM, SystemMemory , 0xFED00000, 0x400)
+            Field(HPTM, DWordAcc, Lock, Preserve) {
+                    VEND, 32,
+                    PRD, 32,
+            }
+            Method (_STA, 0, NotSerialized) {
+                    Store (VEND, Local0)
+                    Store (PRD, Local1)
+                    ShiftRight(Local0, 16, Local0)
+                    If (LOr (LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
+                            Return (0x0)
+                    }
+                    If (LOr (LEqual(Local1, 0), LGreater(Local1, 100000000))) {
+                            Return (0x0)
+                    }
+                    Return (0x0F)
+            }
+            Name(_CRS, ResourceTemplate() {
+                IRQNoFlags () {2, 8}
+                Memory32Fixed (ReadOnly,
+                    0xFED00000,         // Address Base
+                    0x00000400,         // Address Length
+                    )
+            })
+        }
+    }
+
+
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 853648c..9b223c3 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -213,42 +213,7 @@ DefinitionBlock (
         }
     }

-
-/****************************************************************
- * HPET
- ****************************************************************/
-
-    Scope(_SB) {
-        Device(HPET) {
-            Name(_HID,  EISAID("PNP0103"))
-            Name(_UID, 0)
-            OperationRegion(HPTM, SystemMemory , 0xFED00000, 0x400)
-            Field(HPTM, DWordAcc, Lock, Preserve) {
-                    VEND, 32,
-                    PRD, 32,
-            }
-            Method (_STA, 0, NotSerialized) {
-                    Store (VEND, Local0)
-                    Store (PRD, Local1)
-                    ShiftRight(Local0, 16, Local0)
-                    If (LOr (LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
-                            Return (0x0)
-                    }
-                    If (LOr (LEqual(Local1, 0), LGreater(Local1, 100000000))) {
-                            Return (0x0)
-                    }
-                    Return (0x0F)
-            }
-            Name(_CRS, ResourceTemplate() {
-                IRQNoFlags () {2, 8}
-                Memory32Fixed (ReadOnly,
-                    0xFED00000,         // Address Base
-                    0x00000400,         // Address Length
-                    )
-            })
-        }
-    }
-
+#include "acpi-dsdt-hpet.dsl"

/****************************************************************
  * VGA

[PATCH 12/20] acpi: move \_SB.HPET to separate file [q35]

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/q35-acpi-dsdt.dsl |   21 ++-------------------
 1 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index e61f142..737a358 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -360,6 +360,8 @@ DefinitionBlock (
         }
     }

+#include "acpi-dsdt-hpet.dsl"
+
     Scope(_SB.PCI0) {
         Device (VGA) {
                  Name (_ADR, 0x00020000)
@@ -420,25 +422,6 @@ DefinitionBlock (
                 FDEN,   1
             }

-            /* High Precision Event Timer */
-            Device(HPET) {
-                Name(_HID,  EISAID("PNP0103"))
-                Name(_UID, 0)
-                Method (_STA, 0, NotSerialized) {
-                        Return(0x0F)
-                }
-                Name(_CRS, ResourceTemplate() {
-                    DWordMemory(
-                        ResourceConsumer, PosDecode, MinFixed, MaxFixed,
-                        NonCacheable, ReadWrite,
-                        0x00000000,
-                        0xFED00000,
-                        0xFED003FF,
-                        0x00000000,
-                        0x00000400 /* 1K memory: FED00000 - FED003FF */
-                    )
-                })
-            }
             /* Real-time clock */
             Device (RTC)
             {

[PATCH 13/20] acpi: move \_SB.PCI0._CRS to separate file

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt-pci-crs.dsl |  108 +++++++++++++++++++++++++++++++++++++++++++++
 src/acpi-dsdt.dsl         |  106 +-------------------------------------------
 2 files changed, 109 insertions(+), 105 deletions(-)
 create mode 100644 src/acpi-dsdt-pci-crs.dsl

diff --git a/src/acpi-dsdt-pci-crs.dsl b/src/acpi-dsdt-pci-crs.dsl
new file mode 100644
index 0000000..c8c40f3
--- /dev/null
+++ b/src/acpi-dsdt-pci-crs.dsl
@@ -0,0 +1,108 @@
+
+    Scope(_SB.PCI0) {
+
+            Name (CRES, ResourceTemplate ()
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000,             // Address Space Granularity
+                    0x0000,             // Address Range Minimum
+                    0x00FF,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0x0100,             // Address Length
+                    ,, )
+                IO (Decode16,
+                    0x0CF8,             // Address Range Minimum
+                    0x0CF8,             // Address Range Maximum
+                    0x01,               // Address Alignment
+                    0x08,               // Address Length
+                    )
+                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x0000,             // Address Space Granularity
+                    0x0000,             // Address Range Minimum
+                    0x0CF7,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0x0CF8,             // Address Length
+                    ,, , TypeStatic)
+                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x0000,             // Address Space Granularity
+                    0x0D00,             // Address Range Minimum
+                    0xFFFF,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0xF300,             // Address Length
+                    ,, , TypeStatic)
+                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                    0x00000000,         // Address Space Granularity
+                    0x000A0000,         // Address Range Minimum
+                    0x000BFFFF,         // Address Range Maximum
+                    0x00000000,         // Address Translation Offset
+                    0x00020000,         // Address Length
+                    ,, , AddressRangeMemory, TypeStatic)
+                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                    0x00000000,         // Address Space Granularity
+                    0xE0000000,         // Address Range Minimum
+                    0xFEBFFFFF,         // Address Range Maximum
+                    0x00000000,         // Address Translation Offset
+                    0x1EC00000,         // Address Length
+                    ,, PW32, AddressRangeMemory, TypeStatic)
+            })
+            Name (CR64, ResourceTemplate ()
+            {
+                QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                    0x00000000,          // Address Space Granularity
+                    0x8000000000,        // Address Range Minimum
+                    0xFFFFFFFFFF,        // Address Range Maximum
+                    0x00000000,          // Address Translation Offset
+                    0x8000000000,        // Address Length
+                    ,, PW64, AddressRangeMemory, TypeStatic)
+            })
+            Method (_CRS, 0)
+            {
+		/* see see acpi.h, struct bfld */
+		External (BDAT, OpRegionObj)
+		Field(BDAT, QWordAcc, NoLock, Preserve) {
+                    P0S, 64,
+                    P0E, 64,
+                    P0L, 64,
+                    P1S, 64,
+                    P1E, 64,
+                    P1L, 64,
+		}
+		Field(BDAT, DWordAcc, NoLock, Preserve) {
+                    P0SL, 32,
+                    P0SH, 32,
+                    P0EL, 32,
+                    P0EH, 32,
+                    P0LL, 32,
+                    P0LH, 32,
+                    P1SL, 32,
+                    P1SH, 32,
+                    P1EL, 32,
+                    P1EH, 32,
+                    P1LL, 32,
+                    P1LH, 32,
+		}
+
+                /* fixup 32bit pci io window */
+		CreateDWordField (CRES,_SB.PCI0.PW32._MIN, PS32)
+		CreateDWordField (CRES,_SB.PCI0.PW32._MAX, PE32)
+		CreateDWordField (CRES,_SB.PCI0.PW32._LEN, PL32)
+		Store (P0SL, PS32)
+		Store (P0EL, PE32)
+		Store (P0LL, PL32)
+
+		If (LAnd(LEqual(P1SL, 0x00), LEqual(P1SH, 0x00))) {
+		    Return (CRES)
+		} Else {
+		    /* fixup 64bit pci io window */
+		    CreateQWordField (CR64,_SB.PCI0.PW64._MIN, PS64)
+		    CreateQWordField (CR64,_SB.PCI0.PW64._MAX, PE64)
+		    CreateQWordField (CR64,_SB.PCI0.PW64._LEN, PL64)
+		    Store (P1S, PS64)
+		    Store (P1E, PE64)
+		    Store (P1L, PL64)
+		    /* add window and return result */
+		    ConcatenateResTemplate (CRES, CR64, Local0)
+		    Return (Local0)
+		}
+            }
+    }
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 9b223c3..5b89e3f 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -105,114 +105,10 @@ DefinitionBlock (
             {
                 B0EJ, 32,
             }
-
-            Name (CRES, ResourceTemplate ()
-            {
-                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-                    0x0000,             // Address Space Granularity
-                    0x0000,             // Address Range Minimum
-                    0x00FF,             // Address Range Maximum
-                    0x0000,             // Address Translation Offset
-                    0x0100,             // Address Length
-                    ,, )
-                IO (Decode16,
-                    0x0CF8,             // Address Range Minimum
-                    0x0CF8,             // Address Range Maximum
-                    0x01,               // Address Alignment
-                    0x08,               // Address Length
-                    )
-                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-                    0x0000,             // Address Space Granularity
-                    0x0000,             // Address Range Minimum
-                    0x0CF7,             // Address Range Maximum
-                    0x0000,             // Address Translation Offset
-                    0x0CF8,             // Address Length
-                    ,, , TypeStatic)
-                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-                    0x0000,             // Address Space Granularity
-                    0x0D00,             // Address Range Minimum
-                    0xFFFF,             // Address Range Maximum
-                    0x0000,             // Address Translation Offset
-                    0xF300,             // Address Length
-                    ,, , TypeStatic)
-                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-                    0x00000000,         // Address Space Granularity
-                    0x000A0000,         // Address Range Minimum
-                    0x000BFFFF,         // Address Range Maximum
-                    0x00000000,         // Address Translation Offset
-                    0x00020000,         // Address Length
-                    ,, , AddressRangeMemory, TypeStatic)
-                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
-                    0x00000000,         // Address Space Granularity
-                    0xE0000000,         // Address Range Minimum
-                    0xFEBFFFFF,         // Address Range Maximum
-                    0x00000000,         // Address Translation Offset
-                    0x1EC00000,         // Address Length
-                    ,, PW32, AddressRangeMemory, TypeStatic)
-            })
-            Name (CR64, ResourceTemplate ()
-            {
-                QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-                    0x00000000,          // Address Space Granularity
-                    0x8000000000,        // Address Range Minimum
-                    0xFFFFFFFFFF,        // Address Range Maximum
-                    0x00000000,          // Address Translation Offset
-                    0x8000000000,        // Address Length
-                    ,, PW64, AddressRangeMemory, TypeStatic)
-            })
-            Method (_CRS, 0)
-            {
-		/* see see acpi.h, struct bfld */
-		External (BDAT, OpRegionObj)
-		Field(BDAT, QWordAcc, NoLock, Preserve) {
-                    P0S, 64,
-                    P0E, 64,
-                    P0L, 64,
-                    P1S, 64,
-                    P1E, 64,
-                    P1L, 64,
-		}
-		Field(BDAT, DWordAcc, NoLock, Preserve) {
-                    P0SL, 32,
-                    P0SH, 32,
-                    P0EL, 32,
-                    P0EH, 32,
-                    P0LL, 32,
-                    P0LH, 32,
-                    P1SL, 32,
-                    P1SH, 32,
-                    P1EL, 32,
-                    P1EH, 32,
-                    P1LL, 32,
-                    P1LH, 32,
-		}
-
-                /* fixup 32bit pci io window */
-		CreateDWordField (CRES,_SB.PCI0.PW32._MIN, PS32)
-		CreateDWordField (CRES,_SB.PCI0.PW32._MAX, PE32)
-		CreateDWordField (CRES,_SB.PCI0.PW32._LEN, PL32)
-		Store (P0SL, PS32)
-		Store (P0EL, PE32)
-		Store (P0LL, PL32)
-
-		If (LAnd(LEqual(P1SL, 0x00), LEqual(P1SH, 0x00))) {
-		    Return (CRES)
-		} Else {
-		    /* fixup 64bit pci io window */
-		    CreateQWordField (CR64,_SB.PCI0.PW64._MIN, PS64)
-		    CreateQWordField (CR64,_SB.PCI0.PW64._MAX, PE64)
-		    CreateQWordField (CR64,_SB.PCI0.PW64._LEN, PL64)
-		    Store (P1S, PS64)
-		    Store (P1E, PE64)
-		    Store (P1L, PL64)
-		    /* add window and return result */
-		    ConcatenateResTemplate (CRES, CR64, Local0)
-		    Return (Local0)
-		}
-            }
         }
     }

+#include "acpi-dsdt-pci-crs.dsl"
 #include "acpi-dsdt-hpet.dsl"

/****************************************************************

[PATCH 14/20] acpi: move \_SB.PCI0._CRS to separate file [q35]

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/q35-acpi-dsdt.dsl |  106 +------------------------------------------------
 1 files changed, 1 insertions(+), 105 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index 737a358..ddb82bb 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -252,114 +252,10 @@ DefinitionBlock (
    	 Return (PRTA)
    	}
             }
-
-            Name (CRES, ResourceTemplate ()
-            {
-                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-                    0x0000,             // Address Space Granularity
-                    0x0000,             // Address Range Minimum
-                    0x00FF,             // Address Range Maximum
-                    0x0000,             // Address Translation Offset
-                    0x0100,             // Address Length
-                    ,, )
-                IO (Decode16,
-                    0x0CF8,             // Address Range Minimum
-                    0x0CF8,             // Address Range Maximum
-                    0x01,               // Address Alignment
-                    0x08,               // Address Length
-                    )
-                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-                    0x0000,             // Address Space Granularity
-                    0x0000,             // Address Range Minimum
-                    0x0CF7,             // Address Range Maximum
-                    0x0000,             // Address Translation Offset
-                    0x0CF8,             // Address Length
-                    ,, , TypeStatic)
-                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-                    0x0000,             // Address Space Granularity
-                    0x0D00,             // Address Range Minimum
-                    0xFFFF,             // Address Range Maximum
-                    0x0000,             // Address Translation Offset
-                    0xF300,             // Address Length
-                    ,, , TypeStatic)
-                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-                    0x00000000,         // Address Space Granularity
-                    0x000A0000,         // Address Range Minimum
-                    0x000BFFFF,         // Address Range Maximum
-                    0x00000000,         // Address Translation Offset
-                    0x00020000,         // Address Length
-                    ,, , AddressRangeMemory, TypeStatic)
-                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
-                    0x00000000,         // Address Space Granularity
-                    0xC0000000,         // Address Range Minimum
-                    0xFEBFFFFF,         // Address Range Maximum
-                    0x00000000,         // Address Translation Offset
-                    0x3EC00000,         // Address Length
-                    ,, PW32, AddressRangeMemory, TypeStatic)
-            })
-            Name (CR64, ResourceTemplate ()
-            {
-                QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-                    0x00000000,          // Address Space Granularity
-                    0x8000000000,        // Address Range Minimum
-                    0xFFFFFFFFFF,        // Address Range Maximum
-                    0x00000000,          // Address Translation Offset
-                    0x8000000000,        // Address Length
-                    ,, PW64, AddressRangeMemory, TypeStatic)
-            })
-            Method (_CRS, 0)
-            {
-        /* see see acpi.h, struct bfld */
-        External (BDAT, OpRegionObj)
-        Field(BDAT, QWordAcc, NoLock, Preserve) {
-                    P0S, 64,
-                    P0E, 64,
-                    P0L, 64,
-                    P1S, 64,
-                    P1E, 64,
-                    P1L, 64,
-        }
-        Field(BDAT, DWordAcc, NoLock, Preserve) {
-                    P0SL, 32,
-                    P0SH, 32,
-                    P0EL, 32,
-                    P0EH, 32,
-                    P0LL, 32,
-                    P0LH, 32,
-                    P1SL, 32,
-                    P1SH, 32,
-                    P1EL, 32,
-                    P1EH, 32,
-                    P1LL, 32,
-                    P1LH, 32,
-        }
-
-                /* fixup 32bit pci io window */
-        CreateDWordField (CRES,_SB.PCI0.PW32._MIN, PS32)
-        CreateDWordField (CRES,_SB.PCI0.PW32._MAX, PE32)
-        CreateDWordField (CRES,_SB.PCI0.PW32._LEN, PL32)
-        Store (P0SL, PS32)
-        Store (P0EL, PE32)
-        Store (P0LL, PL32)
-
-        If (LAnd(LEqual(P1SL, 0x00), LEqual(P1SH, 0x00))) {
-            Return (CRES)
-        } Else {
-            /* fixup 64bit pci io window */
-            CreateQWordField (CR64,_SB.PCI0.PW64._MIN, PS64)
-            CreateQWordField (CR64,_SB.PCI0.PW64._MAX, PE64)
-            CreateQWordField (CR64,_SB.PCI0.PW64._LEN, PL64)
-            Store (P1S, PS64)
-            Store (P1E, PE64)
-            Store (P1L, PL64)
-            /* add window and return result */
-            ConcatenateResTemplate (CRES, CR64, Local0)
-            Return (Local0)
-        }
-            }
         }
     }

+#include "acpi-dsdt-pci-crs.dsl"
 #include "acpi-dsdt-hpet.dsl"

Scope(_SB.PCI0) {

[PATCH 15/20] acpi: move cpu hotplug to separate file

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt-cpu-hotplug.dsl |   77 +++++++++++++++++++++++++++++++++++++++++
 src/acpi-dsdt.dsl             |   77 +----------------------------------------
 2 files changed, 78 insertions(+), 76 deletions(-)
 create mode 100644 src/acpi-dsdt-cpu-hotplug.dsl

diff --git a/src/acpi-dsdt-cpu-hotplug.dsl b/src/acpi-dsdt-cpu-hotplug.dsl
new file mode 100644
index 0000000..7f3ad3b
--- /dev/null
+++ b/src/acpi-dsdt-cpu-hotplug.dsl
@@ -0,0 +1,77 @@
+/****************************************************************
+ * CPU hotplug
+ ****************************************************************/
+
+    Scope(_SB) {
+        /* Objects filled in by run-time generated SSDT */
+        External(NTFY, MethodObj)
+        External(CPON, PkgObj)
+
+        /* Methods called by run-time generated SSDT Processor objects */
+        Method (CPMA, 1, NotSerialized) {
+            // _MAT method - create an madt apic buffer
+            // Arg0 = Processor ID = Local APIC ID
+            // Local0 = CPON flag for this cpu
+            Store(DerefOf(Index(CPON, Arg0)), Local0)
+            // Local1 = Buffer (in madt apic form) to return
+            Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
+            // Update the processor id, lapic id, and enable/disable status
+            Store(Arg0, Index(Local1, 2))
+            Store(Arg0, Index(Local1, 3))
+            Store(Local0, Index(Local1, 4))
+            Return (Local1)
+        }
+        Method (CPST, 1, NotSerialized) {
+            // _STA method - return ON status of cpu
+            // Arg0 = Processor ID = Local APIC ID
+            // Local0 = CPON flag for this cpu
+            Store(DerefOf(Index(CPON, Arg0)), Local0)
+            If (Local0) { Return(0xF) } Else { Return(0x0) }
+        }
+        Method (CPEJ, 2, NotSerialized) {
+            // _EJ0 method - eject callback
+            Sleep(200)
+        }
+
+        /* CPU hotplug notify method */
+        OperationRegion(PRST, SystemIO, 0xaf00, 32)
+        Field (PRST, ByteAcc, NoLock, Preserve)
+        {
+            PRS, 256
+        }
+        Method(PRSC, 0) {
+            // Local5 = active cpu bitmap
+            Store (PRS, Local5)
+            // Local2 = last read byte from bitmap
+            Store (Zero, Local2)
+            // Local0 = Processor ID / APIC ID iterator
+            Store (Zero, Local0)
+            While (LLess(Local0, SizeOf(CPON))) {
+                // Local1 = CPON flag for this cpu
+                Store(DerefOf(Index(CPON, Local0)), Local1)
+                If (And(Local0, 0x07)) {
+                    // Shift down previously read bitmap byte
+                    ShiftRight(Local2, 1, Local2)
+                } Else {
+                    // Read next byte from cpu bitmap
+                    Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
+                }
+                // Local3 = active state for this cpu
+                Store(And(Local2, 1), Local3)
+
+                If (LNotEqual(Local1, Local3)) {
+                    // State change - update CPON with new state
+                    Store(Local3, Index(CPON, Local0))
+                    // Do CPU notify
+                    If (LEqual(Local3, 1)) {
+                        NTFY(Local0, 1)
+                    } Else {
+                        NTFY(Local0, 3)
+                    }
+                }
+                Increment(Local0)
+            }
+        }
+    }
+
+
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 5b89e3f..947bcff 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -483,82 +483,7 @@ DefinitionBlock (
         }
     }

-/****************************************************************
- * CPU hotplug
- ****************************************************************/
-
-    Scope(_SB) {
-        /* Objects filled in by run-time generated SSDT */
-        External(NTFY, MethodObj)
-        External(CPON, PkgObj)
-
-        /* Methods called by run-time generated SSDT Processor objects */
-        Method (CPMA, 1, NotSerialized) {
-            // _MAT method - create an madt apic buffer
-            // Arg0 = Processor ID = Local APIC ID
-            // Local0 = CPON flag for this cpu
-            Store(DerefOf(Index(CPON, Arg0)), Local0)
-            // Local1 = Buffer (in madt apic form) to return
-            Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
-            // Update the processor id, lapic id, and enable/disable status
-            Store(Arg0, Index(Local1, 2))
-            Store(Arg0, Index(Local1, 3))
-            Store(Local0, Index(Local1, 4))
-            Return (Local1)
-        }
-        Method (CPST, 1, NotSerialized) {
-            // _STA method - return ON status of cpu
-            // Arg0 = Processor ID = Local APIC ID
-            // Local0 = CPON flag for this cpu
-            Store(DerefOf(Index(CPON, Arg0)), Local0)
-            If (Local0) { Return(0xF) } Else { Return(0x0) }
-        }
-        Method (CPEJ, 2, NotSerialized) {
-            // _EJ0 method - eject callback
-            Sleep(200)
-        }
-
-        /* CPU hotplug notify method */
-        OperationRegion(PRST, SystemIO, 0xaf00, 32)
-        Field (PRST, ByteAcc, NoLock, Preserve)
-        {
-            PRS, 256
-        }
-        Method(PRSC, 0) {
-            // Local5 = active cpu bitmap
-            Store (PRS, Local5)
-            // Local2 = last read byte from bitmap
-            Store (Zero, Local2)
-            // Local0 = Processor ID / APIC ID iterator
-            Store (Zero, Local0)
-            While (LLess(Local0, SizeOf(CPON))) {
-                // Local1 = CPON flag for this cpu
-                Store(DerefOf(Index(CPON, Local0)), Local1)
-                If (And(Local0, 0x07)) {
-                    // Shift down previously read bitmap byte
-                    ShiftRight(Local2, 1, Local2)
-                } Else {
-                    // Read next byte from cpu bitmap
-                    Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
-                }
-                // Local3 = active state for this cpu
-                Store(And(Local2, 1), Local3)
-
-                If (LNotEqual(Local1, Local3)) {
-                    // State change - update CPON with new state
-                    Store(Local3, Index(CPON, Local0))
-                    // Do CPU notify
-                    If (LEqual(Local3, 1)) {
-                        NTFY(Local0, 1)
-                    } Else {
-                        NTFY(Local0, 3)
-                    }
-                }
-                Increment(Local0)
-            }
-        }
-    }
-
+#include "acpi-dsdt-cpu-hotplug.dsl"

/****************************************************************
  * General purpose events

[PATCH 16/20] acpi: move cpu hotplug to separate file [q35]

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/q35-acpi-dsdt.dsl |   74 +-----------------------------------------------
 1 files changed, 2 insertions(+), 72 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index ddb82bb..34fb527 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -577,77 +577,7 @@ DefinitionBlock (
         define_gsi_link(GSIH, 0, 0x17)
     }

-    /* CPU hotplug */
-    Scope(_SB) {
-        /* Objects filled in by run-time generated SSDT */
-        External(NTFY, MethodObj)
-        External(CPON, PkgObj)
-
-        /* Methods called by run-time generated SSDT Processor objects */
-        Method (CPMA, 1, NotSerialized) {
-            // _MAT method - create an madt apic buffer
-            // Local0 = CPON flag for this cpu
-            Store(DerefOf(Index(CPON, Arg0)), Local0)
-            // Local1 = Buffer (in madt apic form) to return
-            Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
-            // Update the processor id, lapic id, and enable/disable status
-            Store(Arg0, Index(Local1, 2))
-            Store(Arg0, Index(Local1, 3))
-            Store(Local0, Index(Local1, 4))
-            Return (Local1)
-        }
-        Method (CPST, 1, NotSerialized) {
-            // _STA method - return ON status of cpu
-            // Local0 = CPON flag for this cpu
-            Store(DerefOf(Index(CPON, Arg0)), Local0)
-            If (Local0) { Return(0xF) } Else { Return(0x0) }
-        }
-        Method (CPEJ, 2, NotSerialized) {
-            // _EJ0 method - eject callback
-            Sleep(200)
-        }
-
-        /* CPU hotplug notify method */
-        OperationRegion(PRST, SystemIO, 0xaf00, 32)
-        Field (PRST, ByteAcc, NoLock, Preserve)
-        {
-            PRS, 256
-        }
-        Method(PRSC, 0) {
-            // Local5 = active cpu bitmap
-            Store (PRS, Local5)
-            // Local2 = last read byte from bitmap
-            Store (Zero, Local2)
-            // Local0 = cpuid iterator
-            Store (Zero, Local0)
-            While (LLess(Local0, SizeOf(CPON))) {
-                // Local1 = CPON flag for this cpu
-                Store(DerefOf(Index(CPON, Local0)), Local1)
-                If (And(Local0, 0x07)) {
-                    // Shift down previously read bitmap byte
-                    ShiftRight(Local2, 1, Local2)
-                } Else {
-                    // Read next byte from cpu bitmap
-                    Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
-                }
-                // Local3 = active state for this cpu
-                Store(And(Local2, 1), Local3)
-
-                If (LNotEqual(Local1, Local3)) {
-                    // State change - update CPON with new state
-                    Store(Local3, Index(CPON, Local0))
-                    // Do CPU notify
-                    If (LEqual(Local3, 1)) {
-                        NTFY(Local0, 1)
-                    } Else {
-                        NTFY(Local0, 3)
-                    }
-                }
-                Increment(Local0)
-            }
-            Return(One)
-        }
-    }
+#include "acpi-dsdt-cpu-hotplug.dsl"

Scope (_GPE)
     {
@@ -658,7 +588,7 @@ DefinitionBlock (
         }
         Method(_L01) {
              // CPU hotplug event
-	     Return(_SB.PRSC())
+	     _SB.PRSC()
         }
         Method(_L02) {
             Return(0x01)

[PATCH 17/20] acpi: rework enable bits

[Gerd Hoffmann]

Model the device enable bits as fields so they can be accessed
directly by name.

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt.dsl |   49 ++++++++++++++++++++++++++++---------------------
 1 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 947bcff..6ee3c8e 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -161,6 +161,21 @@ DefinitionBlock (
  ****************************************************************/

Scope(_SB.PCI0.ISA) {
+
+	    /* enable bits */
+	    Field (_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve)
+	    {
+                Offset(0x5f),
+		, 7,
+	        LPEN, 1,         // LPT
+                Offset(0x67),
+		, 3,
+		CAEN, 1,         // COM1
+		, 3,
+		CBEN, 1,         // COM2
+	    }
+	    Name (FDEN, 1)
+
             /* Real-time clock */
             Device (RTC)
             {
@@ -230,7 +245,15 @@ DefinitionBlock (
            Name (_HID, EisaId ("PNP0700"))
    	Method (_STA, 0, NotSerialized)
    	{
-		    Return (0x0F)
+                    Store (FDEN, Local0)
+                    If (LEqual (Local0, 0))
+                    {
+                         Return (0x00)
+                    }
+                    Else
+                    {
+                         Return (0x0F)
+                    }
    	}
    	Method (_CRS, 0, NotSerialized)
    	{
@@ -251,8 +274,7 @@ DefinitionBlock (
            Name (_HID, EisaId ("PNP0400"))
    	Method (_STA, 0, NotSerialized)
    	{
-		    Store (_SB.PCI0.PX13.DRSA, Local0)
-		    And (Local0, 0x80000000, Local0)
+		    Store (LPEN, Local0)
    	    If (LEqual (Local0, 0))
    	    {
    		Return (0x00)
@@ -280,8 +302,7 @@ DefinitionBlock (
    	Name (_UID, 0x01)
    	Method (_STA, 0, NotSerialized)
    	{
-		    Store (_SB.PCI0.PX13.DRSC, Local0)
-		    And (Local0, 0x08000000, Local0)
+		    Store (CAEN, Local0)
    	    If (LEqual (Local0, 0))
    	    {
    		Return (0x00)
@@ -308,8 +329,7 @@ DefinitionBlock (
    	Name (_UID, 0x02)
    	Method (_STA, 0, NotSerialized)
    	{
-		    Store (_SB.PCI0.PX13.DRSC, Local0)
-		    And (Local0, 0x80000000, Local0)
+		    Store (CBEN, Local0)
    	    If (LEqual (Local0, 0))
    	    {
    		Return (0x00)
@@ -339,20 +359,7 @@ DefinitionBlock (
     Scope(_SB.PCI0) {
         Device (PX13) {
        Name (_ADR, 0x00010003)
-
-	    OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
-	    Field (P13C, DWordAcc, NoLock, Preserve)
-	    {
-		DRSA, 32,
-		DRSB, 32,
-		DRSC, 32,
-		DRSE, 32,
-		DRSF, 32,
-		DRSG, 32,
-		DRSH, 32,
-		DRSI, 32,
-		DRSJ, 32
-	    }
+	    OperationRegion (P13C, PCI_Config, 0x00, 0xff)
    }
     }

[PATCH 18/20] acpi: move isa devices to separate file

[Gerd Hoffmann]

Stuff them parameterized into #defines, so we can (a) reuse them for
q35 and (b) don't duplicate the serial line.

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt-isa.dsl |  134 +++++++++++++++++++++++++++++++++++++
 src/acpi-dsdt.dsl     |  176 +------------------------------------------------
 2 files changed, 136 insertions(+), 174 deletions(-)
 create mode 100644 src/acpi-dsdt-isa.dsl

diff --git a/src/acpi-dsdt-isa.dsl b/src/acpi-dsdt-isa.dsl
new file mode 100644
index 0000000..9adc9de
--- /dev/null
+++ b/src/acpi-dsdt-isa.dsl
@@ -0,0 +1,134 @@
+    Scope(_SB.PCI0.ISA) {
+
+            Device (RTC)
+            {
+                Name (_HID, EisaId ("PNP0B00"))
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
+                    IRQNoFlags () {8}
+                    IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
+                })
+            }
+        
+            Device (KBD)
+            {
+                Name (_HID, EisaId ("PNP0303"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+                    IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+                    IRQNoFlags () { 1 }
+                })
+            }
+        
+            Device (MOU)
+            {
+                Name (_HID, EisaId ("PNP0F13"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IRQNoFlags () {12}
+                })
+            }
+        
+            Device (FDC0)
+            {
+                Name (_HID, EisaId ("PNP0700"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (FDEN, Local0)
+                    If (LEqual (Local0, 0))
+                    {
+                        Return (0x00)
+                    }
+                    Else
+                    {
+                        Return (0x0F)
+                    }
+                }
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+                    IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+                    IRQNoFlags () {6}
+                    DMA (Compatibility, NotBusMaster, Transfer8) {2}
+                })
+            }
+        
+            Device (LPT)
+            {
+                Name (_HID, EisaId ("PNP0400"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (LPEN, Local0)
+                    If (LEqual (Local0, 0))
+                    {
+                        Return (0x00)
+                    }
+                    Else
+                    {
+                        Return (0x0F)
+                    }
+                }
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
+                    IRQNoFlags () { 7 }
+                })
+            }
+        
+            Device (COM1)
+            {
+                Name (_HID, EisaId ("PNP0501"))
+                Name (_UID, 0x01)
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (CAEN, Local0)
+                    If (LEqual (Local0, 0))
+                    {
+                        Return (0x00)
+                    }
+                    Else
+                    {
+                        Return (0x0F)
+                    }
+                }
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
+                    IRQNoFlags () { 4 }
+                })
+            }
+        
+            Device (COM2)
+            {
+                Name (_HID, EisaId ("PNP0501"))
+                Name (_UID, 0x01)
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (CBEN, Local0)
+                    If (LEqual (Local0, 0))
+                    {
+                        Return (0x00)
+                    }
+                    Else
+                    {
+                        Return (0x0F)
+                    }
+                }
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
+                    IRQNoFlags () { 3 }
+                })
+            }
+
+    }
\ No newline at end of file
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 6ee3c8e..bb4656c 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -175,182 +175,10 @@ DefinitionBlock (
    	CBEN, 1,         // COM2
        }
        Name (FDEN, 1)
-
-            /* Real-time clock */
-            Device (RTC)
-            {
-                Name (_HID, EisaId ("PNP0B00"))
-                Name (_CRS, ResourceTemplate ()
-                {
-                    IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
-                    IRQNoFlags () {8}
-                    IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
-                })
-            }
-
-            /* Keyboard seems to be important for WinXP install */
-            Device (KBD)
-            {
-                Name (_HID, EisaId ("PNP0303"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                     Name (TMP, ResourceTemplate ()
-                     {
-                    IO (Decode16,
-                        0x0060,             // Address Range Minimum
-                        0x0060,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IO (Decode16,
-                        0x0064,             // Address Range Minimum
-                        0x0064,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IRQNoFlags ()
-                        {1}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 mouse */
-            Device (MOU)
-            {
-                Name (_HID, EisaId ("PNP0F13"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                    Name (TMP, ResourceTemplate ()
-                    {
-                         IRQNoFlags () {12}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 floppy controller */
-	    Device (FDC0)
-	    {
-	        Name (_HID, EisaId ("PNP0700"))
-		Method (_STA, 0, NotSerialized)
-		{
-                    Store (FDEN, Local0)
-                    If (LEqual (Local0, 0))
-                    {
-                         Return (0x00)
-                    }
-                    Else
-                    {
-                         Return (0x0F)
-                    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
-                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
-                        IRQNoFlags () {6}
-                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
-                    })
-		    Return (BUF0)
-		}
-	    }
-
-	    /* Parallel port */
-	    Device (LPT)
-	    {
-	        Name (_HID, EisaId ("PNP0400"))
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (LPEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
-			IRQNoFlags () {7}
-		    })
-		    Return (BUF0)
-		}
-	    }
-
-	    /* Serial Ports */
-	    Device (COM1)
-	    {
-	        Name (_HID, EisaId ("PNP0501"))
-		Name (_UID, 0x01)
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (CAEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
-                	IRQNoFlags () {4}
-		    })
-		    Return (BUF0)
-		}
-	    }
-
-	    Device (COM2)
-	    {
-	        Name (_HID, EisaId ("PNP0501"))
-		Name (_UID, 0x02)
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (CBEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
-                	IRQNoFlags () {3}
-		    })
-		    Return (BUF0)
-		}
-	    }
     }

+#include "acpi-dsdt-isa.dsl"
+

/****************************************************************
  * PIIX4 PM

[PATCH 19/20] acpi: move isa devices to separate file [q35]

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/acpi-dsdt-isa.dsl |    2 +-
 src/acpi-dsdt.dsl     |    6 +-
 src/q35-acpi-dsdt.dsl |  176 +------------------------------------------------
 3 files changed, 6 insertions(+), 178 deletions(-)

diff --git a/src/acpi-dsdt-isa.dsl b/src/acpi-dsdt-isa.dsl
index 9adc9de..30cbbbb 100644
--- a/src/acpi-dsdt-isa.dsl
+++ b/src/acpi-dsdt-isa.dsl
@@ -1,4 +1,4 @@
-    Scope(_SB.PCI0.ISA) {
+    Scope(_SB.PCI0.LPC) {

Device (RTC)
             {
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index bb4656c..d93b1a3 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -147,7 +147,7 @@ DefinitionBlock (
  ****************************************************************/

Scope(_SB.PCI0) {
-        Device (ISA) {
+        Device (LPC) {
             Name (_ADR, 0x00010000)

/* PIIX PCI to ISA irq remapping */
@@ -160,7 +160,7 @@ DefinitionBlock (
  * SuperIO devices (kbd, mouse, etc.)
  ****************************************************************/

-    Scope(_SB.PCI0.ISA) {
+    Scope(_SB.PCI0.LPC) {

/* enable bits */
        Field (_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve)
@@ -232,7 +232,7 @@ DefinitionBlock (
  ****************************************************************/

Scope(_SB) {
-        Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+        Field (PCI0.LPC.P40C, ByteAcc, NoLock, Preserve)
         {
             PRQ0,   8,
             PRQ1,   8,
diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index 34fb527..70e21b9 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -317,183 +317,11 @@ DefinitionBlock (
                 LPEN,   1,
                 FDEN,   1
             }
-
-            /* Real-time clock */
-            Device (RTC)
-            {
-                Name (_HID, EisaId ("PNP0B00"))
-                Name (_CRS, ResourceTemplate ()
-                {
-                    IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
-                    IRQNoFlags () {8}
-                    IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
-                })
-            }
-
-            /* Keyboard seems to be important for WinXP install */
-            Device (KBD)
-            {
-                Name (_HID, EisaId ("PNP0303"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                     Name (TMP, ResourceTemplate ()
-                     {
-                    IO (Decode16,
-                        0x0060,             // Address Range Minimum
-                        0x0060,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IO (Decode16,
-                        0x0064,             // Address Range Minimum
-                        0x0064,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IRQNoFlags ()
-                        {1}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 mouse */
-            Device (MOU)
-            {
-                Name (_HID, EisaId ("PNP0F13"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                    Name (TMP, ResourceTemplate ()
-                    {
-                         IRQNoFlags () {12}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 floppy controller */
-	    Device (FDC0)
-	    {
-	        Name (_HID, EisaId ("PNP0700"))
-		Method (_STA, 0, NotSerialized)
-		{
-                    Store (_SB.PCI0.LPC.FDEN, Local0)
-                    If (LEqual (Local0, 0))
-                    {
-                         Return (0x00)
-                    }
-                    Else
-                    {
-                         Return (0x0F)
-                    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
-                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
-                        IRQNoFlags () {6}
-                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
-                    })
-		    Return (BUF0)
-		}
-	    }
-
-	    /* Parallel port */
-	    Device (LPT)
-	    {
-	        Name (_HID, EisaId ("PNP0400"))
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (_SB.PCI0.LPC.LPEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
-			IRQNoFlags () {7}
-		    })
-		    Return (BUF0)
-		}
-	    }
-
-	    /* Serial Ports */
-	    Device (COM1)
-	    {
-	        Name (_HID, EisaId ("PNP0501"))
-		Name (_UID, 0x01)
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (_SB.PCI0.LPC.CAEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
-                	IRQNoFlags () {4}
-		    })
-		    Return (BUF0)
-		}
-	    }
-
-	    Device (COM2)
-	    {
-	        Name (_HID, EisaId ("PNP0501"))
-		Name (_UID, 0x02)
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (_SB.PCI0.LPC.CBEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
-                	IRQNoFlags () {3}
-		    })
-		    Return (BUF0)
-		}
-	    }
         }
     }

+#include "acpi-dsdt-isa.dsl"
+
     /* PCI IRQs */
     Scope(_SB) {
 #define define_link(link, uid, reg)                     \

[PATCH 19/20] acpi: move isa devices to separate file [q35]

[Kevin O'Connor]

On Wed, Nov 28, 2012 at 10:17:48AM +0100, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann

How about the below instead?  I think it's odd to refer to the ISA
bridge on the PIIX4 as an LPC bus (low pin count bus) when it didn't
have that type of bus.  Granted, it's not technically correct to refer
to the LPC bus on the q35 as an ISA bus, but from a software
perspective the devices are basically ISA devices, so it's a lesser
lie I would think.

-Kevin
> From f051a76b39ef4ac693fd368a7f69160d4a678162 Mon Sep 17 00:00:00 2001

From: Gerd Hoffmann 
Date: Wed, 28 Nov 2012 10:17:48 +0100
Subject: [PATCH] acpi: move isa devices to separate file [q35]
To: [e-mail]

Signed-off-by: Gerd Hoffmann 
Signed-off-by: Kevin O'Connor 
---
 src/q35-acpi-dsdt.dsl | 194 +++-----------------------------------------------
 1 file changed, 11 insertions(+), 183 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index 3032ff6..b106a4f 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -277,7 +277,7 @@ DefinitionBlock (

/* PCI D31:f0 LPC ISA bridge */
-        Device (LPC) {
+        Device (ISA) {
             /* PCI D31:f0 */
             Name (_ADR, 0x001f0000)

@@ -317,183 +317,11 @@ DefinitionBlock (
                 LPEN,   1,
                 FDEN,   1
             }
-
-            /* Real-time clock */
-            Device (RTC)
-            {
-                Name (_HID, EisaId ("PNP0B00"))
-                Name (_CRS, ResourceTemplate ()
-                {
-                    IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
-                    IRQNoFlags () {8}
-                    IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
-                })
-            }
-
-            /* Keyboard seems to be important for WinXP install */
-            Device (KBD)
-            {
-                Name (_HID, EisaId ("PNP0303"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                     Name (TMP, ResourceTemplate ()
-                     {
-                    IO (Decode16,
-                        0x0060,             // Address Range Minimum
-                        0x0060,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IO (Decode16,
-                        0x0064,             // Address Range Minimum
-                        0x0064,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IRQNoFlags ()
-                        {1}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 mouse */
-            Device (MOU)
-            {
-                Name (_HID, EisaId ("PNP0F13"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                    Name (TMP, ResourceTemplate ()
-                    {
-                         IRQNoFlags () {12}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 floppy controller */
-	    Device (FDC0)
-	    {
-	        Name (_HID, EisaId ("PNP0700"))
-		Method (_STA, 0, NotSerialized)
-		{
-                    Store (_SB.PCI0.LPC.FDEN, Local0)
-                    If (LEqual (Local0, 0))
-                    {
-                         Return (0x00)
-                    }
-                    Else
-                    {
-                         Return (0x0F)
-                    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
-                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
-                        IRQNoFlags () {6}
-                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
-                    })
-		    Return (BUF0)
-		}
-	    }
-
-	    /* Parallel port */
-	    Device (LPT)
-	    {
-	        Name (_HID, EisaId ("PNP0400"))
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (_SB.PCI0.LPC.LPEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
-			IRQNoFlags () {7}
-		    })
-		    Return (BUF0)
-		}
-	    }
-
-	    /* Serial Ports */
-	    Device (COM1)
-	    {
-	        Name (_HID, EisaId ("PNP0501"))
-		Name (_UID, 0x01)
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (_SB.PCI0.LPC.CAEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
-                	IRQNoFlags () {4}
-		    })
-		    Return (BUF0)
-		}
-	    }
-
-	    Device (COM2)
-	    {
-	        Name (_HID, EisaId ("PNP0501"))
-		Name (_UID, 0x02)
-		Method (_STA, 0, NotSerialized)
-		{
-		    Store (_SB.PCI0.LPC.CBEN, Local0)
-		    If (LEqual (Local0, 0))
-		    {
-			Return (0x00)
-		    }
-		    Else
-		    {
-			Return (0x0F)
-		    }
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-			IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
-                	IRQNoFlags () {3}
-		    })
-		    Return (BUF0)
-		}
-	    }
         }
     }

+#include "acpi-dsdt-isa.dsl"
+
     /* PCI IRQs */
     Scope(_SB) {
 #define define_link(link, uid, reg)                     \
@@ -538,14 +366,14 @@ DefinitionBlock (
                 }                                       \
         }

-        define_link(LNKA, 0, _SB.PCI0.LPC.PRQA)
-        define_link(LNKB, 1, _SB.PCI0.LPC.PRQB)
-        define_link(LNKC, 2, _SB.PCI0.LPC.PRQC)
-        define_link(LNKD, 3, _SB.PCI0.LPC.PRQD)
-        define_link(LNKE, 4, _SB.PCI0.LPC.PRQE)
-        define_link(LNKF, 5, _SB.PCI0.LPC.PRQF)
-        define_link(LNKG, 6, _SB.PCI0.LPC.PRQG)
-        define_link(LNKH, 7, _SB.PCI0.LPC.PRQH)
+        define_link(LNKA, 0, _SB.PCI0.ISA.PRQA)
+        define_link(LNKB, 1, _SB.PCI0.ISA.PRQB)
+        define_link(LNKC, 2, _SB.PCI0.ISA.PRQC)
+        define_link(LNKD, 3, _SB.PCI0.ISA.PRQD)
+        define_link(LNKE, 4, _SB.PCI0.ISA.PRQE)
+        define_link(LNKF, 5, _SB.PCI0.ISA.PRQF)
+        define_link(LNKG, 6, _SB.PCI0.ISA.PRQG)
+        define_link(LNKH, 7, _SB.PCI0.ISA.PRQH)

#define define_gsi_link(link, uid, gsi)                 \
         Device(link){                                   \

[PATCH 19/20] acpi: move isa devices to separate file [q35]

[Gerd Hoffmann]

On 12/02/12 06:00, Kevin O'Connor wrote:
> On Wed, Nov 28, 2012 at 10:17:48AM +0100, Gerd Hoffmann wrote:
> > Signed-off-by: Gerd Hoffmann
>
> How about the below instead?  I think it's odd to refer to the ISA
> bridge on the PIIX4 as an LPC bus (low pin count bus) when it didn't
> have that type of bus.  Granted, it's not technically correct to refer
> to the LPC bus on the q35 as an ISA bus, but from a software
> perspective the devices are basically ISA devices, so it's a lesser
> lie I would think.

Fine with me.

cheers,
  Gerd

[PATCH 20/20] q35: fix default vga address

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann 
---
 src/q35-acpi-dsdt.dsl |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/q35-acpi-dsdt.dsl b/src/q35-acpi-dsdt.dsl
index 70e21b9..70b488b 100644
--- a/src/q35-acpi-dsdt.dsl
+++ b/src/q35-acpi-dsdt.dsl
@@ -260,7 +260,7 @@ DefinitionBlock (

Scope(_SB.PCI0) {
         Device (VGA) {
-                 Name (_ADR, 0x00020000)
+                 Name (_ADR, 0x00010000)
                  Method (_S1D, 0, NotSerialized)
                  {
                          Return (0x00)

[Kevin O'Connor]

On Wed, Nov 28, 2012 at 10:17:29AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> Next round of the q35 patch series, addressing review
> comments from Jason and Kevin.

Thanks.  I pushed patches 1-4, 7-18, and 20.

-Kevin