SeaBIOS

seabios@seabios.org

4 participants
3734 discussions

new release tag?
by Niklas Cassel 12 Sep '23

12 Sep '23

Hello Seabios maintainers, I was wondering, is there any chance of getting a new release tag (e.g. rel-1.16.3) anytime soon? Or is there any plan on when it will be tagged? I'm waiting to send out a (AHCI specific) QEMU patch, but I can't do so until: 1) there is a new Seabios tag 2) QEMU has updated to the latest Seabios release tag No trying to stress anyone, just looking forward to cross things from my todo list :) Kind regards, Niklas

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Malloc Question
by Kieran Kunhya 12 Sep '23

12 Sep '23

Hello, I'm trying to update this patch for 2017 as I have the same issue as the author in that I can't use the KVM virtual keyboard and a physical keyboard at the same time: https://patchew.org/Seabios/20171215100946.58298-1-stef.van.os@prodrive-tec… I have implemented a linked list as recommended but this has not worked as expected. Assuming I have not made an obvious mistake, I think maybe this patch is not working because I'm using the wrong malloc. Which one should I be using? Thanks for your help. Regards, Kieran Kunhya

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[PATCH] add multiple usb-hid support
by Kieran Kunhya 11 Sep '23

11 Sep '23

Based on a patch from Stef van Os --- src/hw/usb-hid.c | 49 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/src/hw/usb-hid.c b/src/hw/usb-hid.c index dec198a..62c046a 100644 --- a/src/hw/usb-hid.c +++ b/src/hw/usb-hid.c @@ -11,8 +11,14 @@ #include "usb.h" // usb_ctrlrequest #include "usb-hid.h" // usb_keyboard_setup #include "util.h" // process_key +#include "malloc.h" // malloc_low -struct usb_pipe *keyboard_pipe VARFSEG; +struct keyboard_list { + struct usb_pipe *keyboard_pipe; + struct keyboard_list *next; +}; + +struct keyboard_list *keyboard_list VARFSEG; struct usb_pipe *mouse_pipe VARFSEG; @@ -62,11 +68,13 @@ static int usb_kbd_setup(struct usbdevice_s *usbdev , struct usb_endpoint_descriptor *epdesc) { + int kbd_idx = 0; + struct usb_pipe *keyboard_pipe; + struct keyboard_list *prev; + struct keyboard_list *end; + if (! CONFIG_USB_KEYBOARD) return -1; - if (keyboard_pipe) - // XXX - this enables the first found keyboard (could be random) - return -1; if (epdesc->wMaxPacketSize < sizeof(struct keyevent) || epdesc->wMaxPacketSize > MAX_KBD_EVENT) { @@ -91,7 +99,26 @@ usb_kbd_setup(struct usbdevice_s *usbdev if (!keyboard_pipe) return -1; - dprintf(1, "USB keyboard initialized\n"); + prev = end = GET_GLOBAL(keyboard_list); + while (end) { + prev = end; + end = end->next; + kbd_idx++; + } + + end = malloc_low(sizeof(*end)); + if (!end) + return -1; + + end->keyboard_pipe = keyboard_pipe; + end->next = NULL; + + if (!prev) + keyboard_list = end; + else + prev->next = end; + + dprintf(1, "USB keyboard %d initialized\n", kbd_idx); return 0; } @@ -321,13 +348,10 @@ handle_key(struct keyevent *data) // Check if a USB keyboard event is pending and process it if so. static void -usb_check_key(void) +usb_check_key(struct usb_pipe *pipe) { if (! CONFIG_USB_KEYBOARD) return; - struct usb_pipe *pipe = GET_GLOBAL(keyboard_pipe); - if (!pipe) - return; for (;;) { u8 data[MAX_KBD_EVENT]; @@ -344,7 +368,7 @@ usb_kbd_active(void) { if (! CONFIG_USB_KEYBOARD) return 0; - return GET_GLOBAL(keyboard_pipe) != NULL; + return GET_GLOBAL(keyboard_list) != NULL; } // Handle a ps2 style keyboard command. @@ -451,6 +475,9 @@ usb_mouse_command(int command, u8 *param) void usb_check_event(void) { - usb_check_key(); + struct keyboard_list *kbd_list = GET_GLOBAL(keyboard_list); + + for(; kbd_list != NULL; kbd_list = kbd_list->next) + usb_check_key(kbd_list->keyboard_pipe); usb_check_mouse(); } -- 2.25.1

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[PATCH v4 0/6] misc tweaks for kvm and the 64bit pci window
by Gerd Hoffmann 11 Sep '23

11 Sep '23

v4 changes: - fix handling of 32bit memory bars. v3 changes: - rename variables, use u8 for CPULongMode. v2 changes: - e820 conflict fix Gerd Hoffmann (6): better kvm detection detect physical address space size move 64bit pci window to end of address space be less conservative with the 64bit pci io window qemu: log reservations in fw_cfg e820 table check for e820 conflict src/e820map.h | 1 + src/fw/paravirt.h | 2 ++ src/e820map.c | 15 ++++++++ src/fw/paravirt.c | 89 +++++++++++++++++++++++++++++++++++++++++------ src/fw/pciinit.c | 26 +++++++++++--- 5 files changed, 119 insertions(+), 14 deletions(-) -- 2.41.0

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[PATCH v3 0/3] esp-scsi: fix reliance on QEMU ESP SCSI implementation bugs
by Mark Cave-Ayland 24 Aug '23

24 Aug '23

Whilst trying to improve QEMU's ESP SCSI implementation with regard to the NCR datasheet, I noticed that SeaBIOS would fail to boot one of my Debian test images with my patches applied. Further investigation revealed that the SeaBIOS esp-scsi driver inadvertently relies on existing bugs in QEMU's ESP SCSI emulation to work correctly, so this series changes the driver to work as described in the NCR datasheet. With this series applied it is possible for the updated SeaBIOS to boot both QEMU current git HEAD as well as my local WIP branch containing various fixes and improvements to QEMU's ESP SCSI emulation. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> v3: - Add R-B tags for patches 1 and 2 from Paolo - Add patch 3 to handle another bug to be fixed in QEMU's ESP emulation v2: - Fix typo in patch 2 commit message - Add reference to datasheet in patch 2 commit message as requested by Paul Mark Cave-Ayland (3): esp-scsi: flush FIFO before sending SCSI command esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completion esp-scsi: handle non-DMA SCSI commands with no data phase src/hw/esp-scsi.c | 49 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 14 deletions(-) -- 2.39.2

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[Increase BUILD_MAX_E820 to 128] Increase BUILD_MAX_E820 to 128
by Tony Titus 24 Aug '23

24 Aug '23

For platforms with high number of numa nodes, 32 e820 entries are not enough. Linux kernel sets the maximum e820 entries to a base value of 128. Setting BUILD_MAX_E820 to 128 to be in sync with this base value. Signed-off-by: Tony Titus <tonydt(a)amazon.com> --- src/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config.h b/src/config.h index 9abe355..16952eb 100644 --- a/src/config.h +++ b/src/config.h @@ -15,7 +15,7 @@ #define BUILD_APPNAME4 "BXPC" // Maximum number of map entries in the e820 map -#define BUILD_MAX_E820 32 +#define BUILD_MAX_E820 128 // Space to reserve in high-memory for tables #define BUILD_MIN_HIGHTABLE (256*1024) #define BUILD_MAX_HIGHTABLE (16*1024*1024) -- 2.40.1

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[PATCH v2 0/2] esp-scsi: fix reliance on QEMU ESP SCSI implementation bugs
by Mark Cave-Ayland 07 Aug '23

07 Aug '23

Whilst trying to improve QEMU's ESP SCSI implementation with regard to the NCR datasheet, I noticed that SeaBIOS would fail to boot one of my Debian test images with my patches applied. Further investigation revealed that the SeaBIOS esp-scsi driver inadvertently relies on existing bugs in QEMU's ESP SCSI emulation to work correctly, so this series changes the driver to work as described in the NCR datasheet. With this series applied it is possible for the updated SeaBIOS to boot both QEMU current git HEAD as well as my local WIP branch containing various fixes and improvements to QEMU's ESP SCSI emulation. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> v2: - Fix typo in patch 2 commit message - Add reference to datasheet in patch 2 commit message as requested by Paul Mark Cave-Ayland (2): esp-scsi: flush FIFO before sending SCSI command esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completion src/hw/esp-scsi.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) -- 2.39.2

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[PATCH 0/2] esp-scsi: fix reliance on QEMU ESP SCSI implementation bugs
by Mark Cave-Ayland 02 Aug '23

02 Aug '23

Whilst trying to improve QEMU's ESP SCSI implementation with regard to the NCR datasheet, I noticed that SeaBIOS would fail to boot one of my Debian test images with my patches applied. Further investigation revealed that the SeaBIOS esp-scsi driver inadvertently relies on existing bugs in QEMU's ESP SCSI emulation to work correctly, so this series changes the driver to work as described in the NCR datasheet. With this series applied it is possible for the updated SeaBIOS to boot both QEMU current git HEAD as well as my local WIP branch containing various fixes and improvements to QEMU's ESP SCSI emulation. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> Mark Cave-Ayland (2): esp-scsi: flush FIFO before sending SCSI command esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completion src/hw/esp-scsi.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) -- 2.30.2

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[PATCH] paravirt: call pci_bios_init_devices() when runningOnXen()
by Xenia Ragiadakou 14 Jul '23

14 Jul '23

The issue that this patch attempts to address is S3 related. Currently, suspending a XEN guest multiple times does not work. This happens because PIIX4 PM io space gets unmapped during S3 resume and any accesses performed to trigger subsequent suspends are not handled. So, the guest spins on the wake sts bit forever. Below follows a more detailed description of the issue. On S3 resume path, QEMU issues piix4_pm_reset() to bring PPIX4 PM controller to the state expected. More specifically, piix4_pm_reset() zeroes PMIOSE register, i.e pci_conf[0x80] = 0, and this results in unmapping PIIX4 PM io space, i.e. memory_region_set_enabled(&s->io, d->config[0x80] & 1) It is bios responsibility to reenable PIIX4 PM io space during S3 resume path. However, when running on XEN, the qemu platform initialization code does not call pci_bios_init_devices(), hence the PIIX4 PM controller init function is not called and PiixPmBDF is not set. The value of PiixPmBDF indicates the presence of PIIX4 PM controller. Thus, S3 resume code in pci_resume() considers that PIIX4 PM controller is not present and does not perform the relevant post-resume setup that restores PIIX4 PM io space. This is the reason why any subsequent guest access to those registers is not handled. This patch adds a call to pci_bios_init_devices() to the early xen platform setup code. Signed-off-by: Xenia Ragiadakou <xenia.ragiadakou(a)amd.com> --- src/fw/paravirt.c | 1 + src/fw/pciinit.c | 2 +- src/util.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index fba4e52..0c035eb 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -205,6 +205,7 @@ qemu_platform_setup(void) if (runningOnXen()) { pci_probe_devices(); + pci_bios_init_devices(); xen_hypercall_setup(); xen_biostable_setup(); return; diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index badf13d..f955481 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -417,7 +417,7 @@ static void pci_bios_init_device(struct pci_device *pci) PCI_BRIDGE_CTL_SERR); } -static void pci_bios_init_devices(void) +void pci_bios_init_devices(void) { struct pci_device *pci; foreachpci(pci) { diff --git a/src/util.h b/src/util.h index aff8e88..ebd863f 100644 --- a/src/util.h +++ b/src/util.h @@ -137,6 +137,7 @@ extern u64 pcimem64_start, pcimem64_end; extern const u8 pci_irqs[4]; void pci_setup(void); void pci_resume(void); +void pci_bios_init_devices(void); // fw/pirtable.c void pirtable_setup(void); -- 2.34.1

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[PATCH] ahci: handle TFES irq correctly
by Niklas Cassel 07 Jul '23

07 Jul '23

According to AHCI 1.3.1, 5.3.8.1 RegFIS:Entry, if ERR_STAT is set in the received FIS, the HBA shall jump to state ERR:FatalTaskfile, which will raise a TFES IRQ. This means that if ERR_STAT is set in the recevied FIS, PxIS.TFES will be set, without either PxIS.DHRS or PxIS.PSS being set. SeaBIOS function ahci_port_setup() will try to identify an AHCI device by sending an ATAPI identify device command. However, such a command will be aborted with ERR_STAT set for a regular (non-ATAPI) device. ahci_command() already performs the correct error recovery steps when status is correctly set, so simply modify ahci_command() to read the correct status when PxIS.TFES is set. It is safe to read PxTFD when PxIS.TFES is set, even for systems with a port multiplier, see AHCI 1.3.1, 9.3.7 PxTFD Register Information: "When a taskfile error occurs (PxIS.TFES is set to '1'), the host may refer to the values in PxTFD. The values in PxTFD at this time are guaranteed to correspond to the device that reported the taskfile error condition." Without this, each boot will be delayed by 32 seconds, waiting for the AHCI command to timeout. Signed-off-by: Niklas Cassel <niklas.cassel(a)wdc.com> --- src/hw/ahci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hw/ahci.c b/src/hw/ahci.c index d45b430..3fa845a 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -138,6 +138,12 @@ static int ahci_command(struct ahci_port_s *port_gf, int iswrite, int isatapi, intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT); if (intbits) { ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits); + if (intbits & 0x40000000) { + u32 tf = ahci_port_readl(ctrl, pnr, PORT_TFDATA); + status = tf & 0xff; + error = (tf & 0xff00) >> 8; + break; + } if (intbits & 0x02) { status = GET_LOWFLAT(fis->psfis[2]); error = GET_LOWFLAT(fis->psfis[3]); -- 2.40.1

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