SeaBIOS

seabios@seabios.org

1 participants
3784 discussions

[PATCH] vgabios: Fix generating modes list for static_functionality
by Steven Price 12 Oct '24

12 Oct '24

Accessing the data in the vga_modes array requires using GET_GLOBAL(), and the bits set in the bit array should correspond to the modes, not the indexes in vga_modes. With this change the modes calculated matches the expected value of 0xfe0ff. Fixes: 12900b1a2431 ("vgabios: Fill in available legacy modes in video_func_static at runtime") Signed-off-by: Steven Price <steven(a)ecrips.co.uk> --- I suspect this is also the cause of a bug reported against QEMU: https://gitlab.com/qemu-project/qemu/-/issues/629 --- vgasrc/stdvgamodes.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vgasrc/stdvgamodes.c b/vgasrc/stdvgamodes.c index b1d0ef674db4..d72d36b4a27d 100644 --- a/vgasrc/stdvgamodes.c +++ b/vgasrc/stdvgamodes.c @@ -419,9 +419,9 @@ stdvga_build_video_param(void) // Fill available legacy modes in video_func_static table u32 modes = 0; for (i = 0; i < ARRAY_SIZE(vga_modes); i++) { - u16 mode = vga_modes[i].mode; + u16 mode = GET_GLOBAL(vga_modes[i].mode); if (mode <= 0x13) - modes |= 1<<i; + modes |= 1<<mode; } SET_VGA(static_functionality.modes, modes); } -- 2.39.5

1 0

Extending SeaBIOS for additional USB-HID devices
by Fox, Ethan 26 Sep '24

26 Sep '24

Hello! I am a university student and I am interested in extending SeaBIOS for a project which involves requiring connecting a USB SoloKey to your computer during the boot process. Implementing this in SeaBIOS seems promising since it looks like SeaBIOS has code written to interface with USB-HID keyboard and mice. I believe that SoloKey also follows this USB-HID spec. Is it feasible to extend the USB-HID code to also interact with SoloKey, or am I going to run into some road blocks? Any advice is welcome. Thanks, Ethan Fox

1 0

[PATCH 0/2] pci: skip pci resource allocation if instructed by platform
by Abhimanyu Saini 18 Sep '24

18 Sep '24

A hypervisor may want to perform PCI resource allocation (bus numbers, io and mmio ranges) and program the resulting values into the devices itself rather than delegate this to the firmware. Introduce a new flag in fw_cfg, "etc/pci-noalloc", to instruct the firmware to skip the resource allocation phase and use whatever is already programmed in the devices. Abhimanyu Saini (2): fw/pciinit: factor out pci resource allocation pci: skip pci resource allocation if instructed by platform src/fw/pciinit.c | 40 ++++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 14 deletions(-) -- 2.40.1 Amazon Web Services Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B Sitz: Berlin Ust-ID: DE 365 538 597

1 2

[PATCH] esp-scsi: indicate acceptance of MESSAGE IN phase data
by Mark Cave-Ayland 04 Sep '24

04 Sep '24

When the target has sent its MESSAGE IN phase data to the initiator, it waits for the initiator to release the ACK signal before disconnecting from the bus. Send a MSG_ACC command to the ESP so that the initiator releases the ACK signal to allow the target to disconnect, and also return the ASC back to the disconnected state. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> --- src/hw/esp-scsi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) [MCA: this is required for an upcoming QEMU ESP patch series which enforces the commands that can be executed in each internal ESP state. Without this fix SeaBIOS doesn't return the ESP back to its disconnected state after the SCSI transfer, causing subsequent ESP commands to fail.] diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c index 8612069f..e1bee545 100644 --- a/src/hw/esp-scsi.c +++ b/src/hw/esp-scsi.c @@ -50,6 +50,7 @@ #define ESP_CMD_RESET 0x02 #define ESP_CMD_TI 0x10 #define ESP_CMD_ICCS 0x11 +#define ESP_CMD_MSGACC 0x12 #define ESP_CMD_SELATN 0x42 #define ESP_STAT_DI 0x01 @@ -159,11 +160,12 @@ esp_scsi_process_op(struct disk_op_s *op) continue; } - /* Finally read data from the message in phase. */ + /* Finally read data from the message in phase and accept. */ if (state == 3 && (stat & ESP_STAT_MSG)) { state++; status = inb(iobase + ESP_FIFO); inb(iobase + ESP_FIFO); + outb(ESP_CMD_MSGACC, iobase + ESP_CMD); break; } usleep(5); -- 2.39.2

2 1

[PATCH] Major bug in src/farptr.h
by william pecnik 05 Aug '24

05 Aug '24

the patch is in attach file to apply use "*patch src/farptr.h < farptr.patch*" from seabios directory This will fix the problem of calling bios service int 0x13 AH=0x42 when the drive is a ATAPI (because Outs should use DS:SI and not ES:DI) This bug affect all Outs() when called from real mode 16bits ! i save DS and restore it after, because Seabios use it

2 1

Major bug in src/farptr.h
by william pecnik 03 Aug '24

03 Aug '24

inlines outsb_fl() outsw_fl and outsl_fl are broken when used from real mode 16bits Outs use segment DS:SI not ES, so here is the fix: (assuming we save DS and restore it because Seabios use it) static inline void outsb_fl(u16 port, void *ptr_fl, u16 count) { u16 ds = GET_SEG(DS); SET_SEG(DS, FLATPTR_TO_SEG(ptr_fl)); outsb(port, (u8*)FLATPTR_TO_OFFSET(ptr_fl), count); SET_SEG(DS, ds); } static inline void outsw_fl(u16 port, void *ptr_fl, u16 count) { u16 ds = GET_SEG(DS); SET_SEG(DS, FLATPTR_TO_SEG(ptr_fl)); outsw(port, (u16*)FLATPTR_TO_OFFSET(ptr_fl), count); SET_SEG(DS, ds); } static inline void outsl_fl(u16 port, void *ptr_fl, u16 count) { u16 ds = GET_SEG(DS); SET_SEG(DS, FLATPTR_TO_SEG(ptr_fl)); outsl(port, (u32*)FLATPTR_TO_OFFSET(ptr_fl), count); SET_SEG(DS, ds); }

1 0

Thinkpad W530 Windows 10/11 BSOD
by Simon Dominic 22 Jul '24

22 Jul '24

Hi, When I compile coreboot for the Thinkpad W530 with SeaBIOS and even with vga bios roms (both integrated and discrete) and try to run Windows 10 or 11, I get BSOD "ACPI BIOS ERROR". Even just sticking in the Windows install usb and loading that, that error shows up. Thanks Simon

1 0

[PATCH] boot: Add an option to always show boot menu
by Timothy Redaelli 19 Jul '24

19 Jul '24

Always show boot menu when show-boot-menu is set to 3. A good use case for that is when you want to use SeaBIOS as secondary payload on Coreboot (for example, for GRUB2) and you need it only to boot from USB stick or stuff like that. Signed-off-by: Timothy Redaelli <tredaelli(a)redhat.com> --- docs/Runtime_config.md | 2 +- src/boot.c | 33 ++++++++++++++++++--------------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/docs/Runtime_config.md b/docs/Runtime_config.md index 5795382b..89c01f90 100644 --- a/docs/Runtime_config.md +++ b/docs/Runtime_config.md @@ -173,7 +173,7 @@ There are several additional configuration options available in the | Filename | Description |---------------------|--------------------------------------------------- -| show-boot-menu | Controls the display of the boot menu. Valid values are 0: Disable the boot menu, 1: Display boot menu unconditionally, 2: Skip boot menu if only one device is present. The default is 1. +| show-boot-menu | Controls the display of the boot menu. Valid values are 0: Disable the boot menu, 1: Display boot menu unconditionally, 2: Skip boot menu if only one device is present, 3: Always display boot menu without requiring a key press. The default is 1. | boot-menu-message | Customize the text boot menu message. Normally, when in text mode SeaBIOS will report the string "\\nPress ESC for boot menu.\\n\\n". This field allows the string to be changed. (This is a string field, and is added as a file containing the raw string.) | boot-menu-key | Controls which key activates the boot menu. The value stored is the DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set, be sure to also customize the **boot-menu-message** field above. | boot-menu-wait | Amount of time (in milliseconds) to wait at the boot menu prompt before selecting the default boot. diff --git a/src/boot.c b/src/boot.c index 1effd802..cab41f62 100644 --- a/src/boot.c +++ b/src/boot.c @@ -708,21 +708,24 @@ interactive_bootmenu(void) return; } - while (get_keystroke(0) >= 0) - ; - - char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); - int menukey = romfile_loadint("etc/boot-menu-key", 1); - printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); - free(bootmsg); - - u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); - enable_bootsplash(); - int scan_code = get_keystroke(menutime); - disable_bootsplash(); - if (scan_code != menukey) - return; - + int menukey = 0, scan_code; + // wait for keypress + if (show_boot_menu != 3) { + while (get_keystroke(0) >= 0) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); + menukey = romfile_loadint("etc/boot-menu-key", 1); + printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + scan_code = get_keystroke(menutime); + disable_bootsplash(); + if (scan_code != menukey) + return; + } while (get_keystroke(0) >= 0) ; -- 2.45.2

1 0

[PATCH v2 1/4] add debug when we set pci_pad_mem64
by John Levon 17 Jul '24

17 Jul '24

This is an interesting enough setting to add a dprintf() for. Signed-off-by: John Levon <john.levon(a)nutanix.com> --- src/fw/pciinit.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index bb44dc29..0395fdbf 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -1197,8 +1197,10 @@ pci_setup(void) } } - if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G) + if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G) { + dprintf(1, "enabling 64-bit pci mmio window\n"); pci_pad_mem64 = 1; + } dprintf(1, "=== PCI bus & bridge init ===\n"); if (pci_probe_host() != 0) { -- 2.34.1

6 25

regression: cannot boot from nvme anymore, disabling 64bit pci io window helps
by Marek Marczykowski-Górecki 15 Jul '24

15 Jul '24

Hi, After an update some time ago, a VM wit 8GB RAM cannot boot from nvme anymore. QEMU cmdline: /usr/bin/qemu-system-x86_64 \ -chardev ringbuf,id=serial0,logfile=serial0,logappend=on \ -serial chardev:serial0 \ -m 8192 \ -enable-kvm \ -vnc :2,share=force-shared \ -blockdev driver=file,node-name=hd0-file,filename=disk.qcow2,cache.no-flush=on,discard=unmap \ -blockdev driver=qcow2,node-name=hd0,file=hd0-file,cache.no-flush=on,discard=unmap \ -device nvme,id=hd0-device,drive=hd0,serial=hd0 \ -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios \ -bios /home/user/seabios/out/bios.bin There is nothing fancy on the disk, just standard grub2 setup, but also I believe it doesn't matter, as it doesn't even reach grub. When it fails, the seabios log contains: PCI: 64: 0000038000000000 - 0000038040000000 PCI: map device bdf=00:04.0 bar 0, addr 38000000000, size 00004000 [mem] ... Searching bootorder for: /pci@i0cf8/isa@1/fdc@03f0/floppy@0 ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) Searching bootorder for: HALT Can not map memory bar over 4Gig ... Boot failed: could not read the boot disk Working version has this instead: PCI: map device bdf=00:04.0 bar 0, addr febf0000, size 00004000 [mem] ... Booting from Hard Disk... Booting from 0000:7c00 00:04.0 is the nvme. I'm attaching full logs for both cases. Bisect shows: 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb is the first bad commit commit 96a8d130a8c2e908e357ce62cd713f2cc0b0a2eb (HEAD) Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Sep 9 10:17:15 2022 +0200 be less conservative with the 64bit pci io window Current seabios code will only enable and use the 64bit pci io window in case it runs out of space in the 32bit pci mmio window below 4G. This patch will also enable the 64bit pci io window when (a) RAM above 4G is present, and (b) the physical address space size is known, and (c) seabios is running on a 64bit capable processor. This operates with the assumption that guests which are ok with memory above 4G most likely can handle mmio above 4G too. In case the 64bit pci io window is enabled also assign more memory to prefetchable pci bridge windows and the complete 64bit pci io window. The total mmio window size is 1/8 of the physical address space. Minimum bridge windows size is 1/256 of the total mmio window size. Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> I've tried the recent "[PATCH] limit address space used for pci devices, part two" patch from the ML, but it doesn't help. OTOH, the series with "only enable 64bit pci io window when RAM >64G" does help. -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS