SeaBIOS

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Fwd: [PATCH] resume: reset mmconfig to zero
by Omar Berrow 03 Nov '24

03 Nov '24

---------- Forwarded message --------- From: Omar Berrow <omarkberrow(a)gmail.com> Date: Sun, Nov 3, 2024 at 7:11 AM Subject: Re: [SeaBIOS] [PATCH] resume: reset mmconfig to zero To: Paul Menzel <pmenzel(a)molgen.mpg.de> > Also maybe mention the new log messages. > Should the log level be increased to 3, or is it important to have it in the logs? I must've forgotten to remove the printf while debugging, it's fine to completely remove it. > What’s the downside of not making the BIOS read-only? The BIOS does later write to mmconfig while resuming, it does indeed assume that the bios is writable, which, if I made it read-only again, would make this assumption false. > Nice find. Is there a way to reproduce your issue, for example with QEMU? Indeed: - Put QEMU into the S3 sleeping state. - When you wake the virtual machine, if you were to add logs in pci_config_writel, you would see that it tries to use ECAM space while access to the ECAM is being restored. Side effects: ECAM access was never truly restored in the BIOS on resume, so when the kernel then goes to access the PCIe bus through ECAM, it finds that no changes are going through. If you guys need a kernel that has S3 to verify this, I will link my kernel below https://github.com/OBOS-dev/obos/tree/b26e062af2c53ee6c3364a88784d22225ee27… (for the best performance, use CMAKE_BUILD_TYPE=Release and KVM) It should suspend right after printing: > [ LOG ] oboskrnl: Suspend requested Sincerely, Omar

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[PATCH] resume: reset mmconfig to zero
by Omar Berrow 02 Nov '24

02 Nov '24

Signed-off-by: Omar Berrow <omarkberrow(a)gmail.com> --- src/hw/pci.c | 2 +- src/resume.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/hw/pci.c b/src/hw/pci.c index 8eda84b2..dfe4d92a 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -14,7 +14,7 @@ #define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_DATA 0x0cfc -static u32 mmconfig; +volatile u32 mmconfig; static void *mmconfig_addr(u16 bdf, u32 addr) { diff --git a/src/resume.c b/src/resume.c index fb0b8a89..10b873c3 100644 --- a/src/resume.c +++ b/src/resume.c @@ -96,6 +96,15 @@ s3_resume(void) return; } + make_bios_writable(); + // reset mmconfig to make sure that we don't use PCIe to + // resume PCIe + dprintf(1, "resetting mmconfig\n"); + extern volatile u32 mmconfig; + mmconfig = 0; + dprintf(1, "mmconfig: 0x%x\n", mmconfig); +// make_bios_readonly(); + pic_setup(); smm_setup(); smp_resume(); -- 2.45.2

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feature patch: NVRAM bootorder
by Timothy Kenno Handojo 31 Oct '24

31 Oct '24

Dear Maintainers, I hope this message finds you well. Attached is the patch containing some of my changes I'm proposing: 0001-boot-Allow-setting-bootorder-from-CMOS-entry.patch The change allows seabios to load bootorder not only from CBFS but also from the NVRAM as well, making use of coreboot's cmos.layout. To prepare testing environment: - Prepare the coreboot source code with coreboot-qemu-q35-cmos.layout-test.patch. Configure coreboot for QEMU Q35 platform. For the payload, you can select anything (I simply choose SeaBIOS for simplicity), with secondary payloads of coreinfo and nvramcui. I've attached the qemu-q35-defconfig to eliminate possible ambiguity. - Compile a coreboot.rom. - Prepare the SeaBIOS source code with 0001-boot-Allow-setting-bootorder-from-CMOS-entry.patch, and compile it. - On the newly compiled coreboot.rom, use cbfstool (which gets compiled along with the coreboot.rom) to remove fallback/payload, then add the newly compiled bios.bin.elf as the new fallback/payload. - Prepare a Linux bootable. In general, any Linux system would do as long as you can run the required software. I go with Alpine Linux live disk as its ISO image is only 64MB. Any additional files go in a secondary disk, including its overlay system. I simply created a 16MB image using dd command and then formatted it with FAT. - Compile cbmem and nvramtool from coreboot's util directory. For my Alpine Linux setup, I need to make sure to compile with musl instead of glibc (e.g. in an Alpine chroot) - Include cbmem and nvramtool to the Linux bootable. For my Alpine setup, I simply have a secondary disk image (also where I put the overlay). - For convenience, I'd put everything in the same directory. To actually test: - Run QEMU with `qemu-system-x86_64 -enable-kvm -cpu host -M q35 -bios coreboot-qemu.rom -m 1G <disks>` - For the QEMU options, serial output can be used as well, however it tends to break when loading coreinfo & nvramcui. Regardless, it's useful when all I have to do is debug with cbmem output. - On the BIOS screen, press Esc to see the menu. Note the disks should be on top. Boot to the disk. - Once your Linux system boots on QEMU, login to CLI as root, use nvramtool to modify the 'bootorder' entry. I myself ran `nvramtool -w bootorder="/rom@img/coreinfo"` to make it boot coreinfo first thing. - Reboot the QEMU system (do NOT kill the QEMU), press Esc again and see that coreinfo now jumps to the top. You can also not press Esc and see it loads coreinfo. Feel free to replace coreinfo with something else! Some todo - Create a tool to modify bootorder more properly (i.e. loading from file would be nice, for starters) -- in progress - Make bootorder a reserved section on cmos.layout to prevent unintended changes. - Test on a read hardware, I have a Thinkpad X230 eager to try it Do let me know if you have any feedback! Warm regards, Timothy Kenno Handojo

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[PATCH] vgabios: Fix generating modes list for static_functionality
by Steven Price 25 Oct '24

25 Oct '24

Accessing the data in the vga_modes array requires using GET_GLOBAL(), and the bits set in the bit array should correspond to the modes, not the indexes in vga_modes. With this change the modes calculated matches the expected value of 0xfe0ff. Fixes: 12900b1a2431 ("vgabios: Fill in available legacy modes in video_func_static at runtime") Signed-off-by: Steven Price <steven(a)ecrips.co.uk> --- I suspect this is also the cause of a bug reported against QEMU: https://gitlab.com/qemu-project/qemu/-/issues/629 --- vgasrc/stdvgamodes.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vgasrc/stdvgamodes.c b/vgasrc/stdvgamodes.c index b1d0ef674db4..d72d36b4a27d 100644 --- a/vgasrc/stdvgamodes.c +++ b/vgasrc/stdvgamodes.c @@ -419,9 +419,9 @@ stdvga_build_video_param(void) // Fill available legacy modes in video_func_static table u32 modes = 0; for (i = 0; i < ARRAY_SIZE(vga_modes); i++) { - u16 mode = vga_modes[i].mode; + u16 mode = GET_GLOBAL(vga_modes[i].mode); if (mode <= 0x13) - modes |= 1<<i; + modes |= 1<<mode; } SET_VGA(static_functionality.modes, modes); } -- 2.39.5

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Extending SeaBIOS for additional USB-HID devices
by Fox, Ethan 26 Sep '24

26 Sep '24

Hello! I am a university student and I am interested in extending SeaBIOS for a project which involves requiring connecting a USB SoloKey to your computer during the boot process. Implementing this in SeaBIOS seems promising since it looks like SeaBIOS has code written to interface with USB-HID keyboard and mice. I believe that SoloKey also follows this USB-HID spec. Is it feasible to extend the USB-HID code to also interact with SoloKey, or am I going to run into some road blocks? Any advice is welcome. Thanks, Ethan Fox

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[PATCH 0/2] pci: skip pci resource allocation if instructed by platform
by Abhimanyu Saini 18 Sep '24

18 Sep '24

A hypervisor may want to perform PCI resource allocation (bus numbers, io and mmio ranges) and program the resulting values into the devices itself rather than delegate this to the firmware. Introduce a new flag in fw_cfg, "etc/pci-noalloc", to instruct the firmware to skip the resource allocation phase and use whatever is already programmed in the devices. Abhimanyu Saini (2): fw/pciinit: factor out pci resource allocation pci: skip pci resource allocation if instructed by platform src/fw/pciinit.c | 40 ++++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 14 deletions(-) -- 2.40.1 Amazon Web Services Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B Sitz: Berlin Ust-ID: DE 365 538 597

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[PATCH] esp-scsi: indicate acceptance of MESSAGE IN phase data
by Mark Cave-Ayland 04 Sep '24

04 Sep '24

When the target has sent its MESSAGE IN phase data to the initiator, it waits for the initiator to release the ACK signal before disconnecting from the bus. Send a MSG_ACC command to the ESP so that the initiator releases the ACK signal to allow the target to disconnect, and also return the ASC back to the disconnected state. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland(a)ilande.co.uk> --- src/hw/esp-scsi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) [MCA: this is required for an upcoming QEMU ESP patch series which enforces the commands that can be executed in each internal ESP state. Without this fix SeaBIOS doesn't return the ESP back to its disconnected state after the SCSI transfer, causing subsequent ESP commands to fail.] diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c index 8612069f..e1bee545 100644 --- a/src/hw/esp-scsi.c +++ b/src/hw/esp-scsi.c @@ -50,6 +50,7 @@ #define ESP_CMD_RESET 0x02 #define ESP_CMD_TI 0x10 #define ESP_CMD_ICCS 0x11 +#define ESP_CMD_MSGACC 0x12 #define ESP_CMD_SELATN 0x42 #define ESP_STAT_DI 0x01 @@ -159,11 +160,12 @@ esp_scsi_process_op(struct disk_op_s *op) continue; } - /* Finally read data from the message in phase. */ + /* Finally read data from the message in phase and accept. */ if (state == 3 && (stat & ESP_STAT_MSG)) { state++; status = inb(iobase + ESP_FIFO); inb(iobase + ESP_FIFO); + outb(ESP_CMD_MSGACC, iobase + ESP_CMD); break; } usleep(5); -- 2.39.2

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[PATCH] Major bug in src/farptr.h
by william pecnik 05 Aug '24

05 Aug '24

the patch is in attach file to apply use "*patch src/farptr.h < farptr.patch*" from seabios directory This will fix the problem of calling bios service int 0x13 AH=0x42 when the drive is a ATAPI (because Outs should use DS:SI and not ES:DI) This bug affect all Outs() when called from real mode 16bits ! i save DS and restore it after, because Seabios use it

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Major bug in src/farptr.h
by william pecnik 03 Aug '24

03 Aug '24

inlines outsb_fl() outsw_fl and outsl_fl are broken when used from real mode 16bits Outs use segment DS:SI not ES, so here is the fix: (assuming we save DS and restore it because Seabios use it) static inline void outsb_fl(u16 port, void *ptr_fl, u16 count) { u16 ds = GET_SEG(DS); SET_SEG(DS, FLATPTR_TO_SEG(ptr_fl)); outsb(port, (u8*)FLATPTR_TO_OFFSET(ptr_fl), count); SET_SEG(DS, ds); } static inline void outsw_fl(u16 port, void *ptr_fl, u16 count) { u16 ds = GET_SEG(DS); SET_SEG(DS, FLATPTR_TO_SEG(ptr_fl)); outsw(port, (u16*)FLATPTR_TO_OFFSET(ptr_fl), count); SET_SEG(DS, ds); } static inline void outsl_fl(u16 port, void *ptr_fl, u16 count) { u16 ds = GET_SEG(DS); SET_SEG(DS, FLATPTR_TO_SEG(ptr_fl)); outsl(port, (u32*)FLATPTR_TO_OFFSET(ptr_fl), count); SET_SEG(DS, ds); }

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Thinkpad W530 Windows 10/11 BSOD
by Simon Dominic 22 Jul '24

22 Jul '24

Hi, When I compile coreboot for the Thinkpad W530 with SeaBIOS and even with vga bios roms (both integrated and discrete) and try to run Windows 10 or 11, I get BSOD "ACPI BIOS ERROR". Even just sticking in the Windows install usb and loading that, that error shows up. Thanks Simon

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