Table type 20 (memory device mapped address) is no longer required as of smbios spec v2.5. Leaving it out completely saves us from having to figure out how to connect type 17 devices to type 19 memory areas.
Signed-off-by: Gabriel Somlo somlo@cmu.edu --- hw/i386/smbios.c | 99 +----------------------------------------------- include/hw/i386/smbios.h | 12 ------ 2 files changed, 1 insertion(+), 110 deletions(-)
diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c index 1b9465a..f6fbb69 100644 --- a/hw/i386/smbios.c +++ b/hw/i386/smbios.c @@ -563,35 +563,6 @@ static void smbios_build_type_19_table(unsigned instance, SMBIOS_BUILD_TABLE_POST; }
-static void smbios_build_type_20_table(unsigned instance, - unsigned dev_hndl, unsigned array_hndl, - ram_addr_t start, ram_addr_t size) -{ - ram_addr_t end, start_kb, end_kb; - - SMBIOS_BUILD_TABLE_PRE(20, 0x1400 + instance, true); /* required */ - - end = start + size - 1; - assert(end > start); - start_kb = start / ONE_KB; - end_kb = end / ONE_KB; - if (start_kb >= UINT32_MAX || end_kb >= UINT32_MAX) { - t->starting_address = t->ending_address = UINT32_MAX; - fprintf(stderr, "qemu: warning: SMBIOS v2.7+ required for " - "type20(start=%lx, size=%lx)\n", start, size); - } else { - t->starting_address = start_kb; - t->ending_address = end_kb; - } - t->memory_device_handle = 0x1100 + dev_hndl; /* Type 17 (Memory Device) */ - t->memory_array_mapped_address_handle = 0x1300 + array_hndl; /* Type 19 */ - t->partition_row_position = 1; /* One device per row, always first pos. */ - t->interleave_position = 0; /* Not interleaved */ - t->interleaved_data_depth = 0; /* Not interleaved */ - - SMBIOS_BUILD_TABLE_POST; -} - static void smbios_build_type_32_table(void) { SMBIOS_BUILD_TABLE_PRE(32, 0x2000, true); /* required */ @@ -685,64 +656,6 @@ void smbios_get_tables(uint8_t **tables, size_t *tables_len, smbios_build_type_4_table(i); }
- /* SeaBIOS expects tables compliant to smbios v2.4; - * As such, we currently support ram_size up to 2T - * (relevant to type 16), and DIMM sizes up to 16G - * (for type 17). - * - * One type 16 (physical memory array) table is created - * to represent the entire given ram_size, which is then - * split into type 17 (memory device) DMIMMs of 16G, with - * the last DIMM covering the sub-16G remainder - * (ram_size % 16G). - * - * Up to two type 19 (memory array mapped address) tables - * are created: the first one covers below-4G memory, and - * the second, if applicable, covers above-4g memory. - * - * Tables of type 20 (memory device mapped address) are - * created as necessary, to connect type 17 DIMMs to - * type 19 memory areas. - * - * The following figure illustrates how many instances of - * each type are generated: - * - * ------- ------- - * | T17 | | T17 | - * | <=16G | | <=16G | ... - * | 1100h |<----+ | 1101h | - * ------- | ------- - * ^ | ^ - * | | | - * ---+--- ---+--- ---+--- - * | T20 | | T20 | | T20 | - * | <4G | | 4G+ | | <=16G | ... - * | 1400h | | 1401h | | 1402h | - * ---+--- ---+--- ---+--- - * | | | - * v v v - * ------- -------------------...-- - * | T19 | | T19 | - * | <4G | | 4G and up | - * | 1300h | | 1301h | - * ------- -------------------...-- - * - * With under 4G of memory, a single DIMM and a single - * below-4G memory area are linked together by a single - * type 20 device mapped address. - * - * With over 4G (but less than 16G) of memory, we still - * require only one DIMM, but create two memory areas, - * one representing the below_4g_ram, and the other one - * for above_4g_ram. Two type 20 device mapped address - * tables link our DIMM to the below_4g and above_4g - * areas, respectively. - * - * With over 16G of memory, we create additional DIMMs, and - * additional type 20 device mapped address tables to link - * each such additional DIMM to the above_4g_ram area. - */ - #define MAX_DIMM_SZ (16 * ONE_GB) #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ : ram_size % MAX_DIMM_SZ)
@@ -752,18 +665,8 @@ void smbios_get_tables(uint8_t **tables, size_t *tables_len, smbios_build_type_17_table(i, GET_DIMM_SZ); } smbios_build_type_19_table(0, 0, smbios_below_4g_ram); - smbios_build_type_20_table(0, 0, 0, 0, smbios_below_4g_ram); if (smbios_above_4g_ram) { - ram_addr_t start = 4 * ONE_GB, size; - smbios_build_type_19_table(1, start, smbios_above_4g_ram); - for (i = 0; i < dimm_cnt; i++) { - size = GET_DIMM_SZ; - if (i == 0) { /* below-4G portion of DIMM 0 already mapped */ - size -= smbios_below_4g_ram; - } - smbios_build_type_20_table(i + 1, i, 1, start, size); - start += size; - } + smbios_build_type_19_table(1, 4 * ONE_GB, smbios_above_4g_ram); }
smbios_build_type_32_table(); diff --git a/include/hw/i386/smbios.h b/include/hw/i386/smbios.h index 8a4e3b1..83a3604 100644 --- a/include/hw/i386/smbios.h +++ b/include/hw/i386/smbios.h @@ -177,18 +177,6 @@ struct smbios_type_19 { uint8_t partition_width; } QEMU_PACKED;
-/* SMBIOS type 20 - Memory Device Mapped Address */ -struct smbios_type_20 { - struct smbios_structure_header header; - uint32_t starting_address; - uint32_t ending_address; - uint16_t memory_device_handle; - uint16_t memory_array_mapped_address_handle; - uint8_t partition_row_position; - uint8_t interleave_position; - uint8_t interleaved_data_depth; -} QEMU_PACKED; - /* SMBIOS type 32 - System Boot Information */ struct smbios_type_32 { struct smbios_structure_header header;