On Tue, Jul 13, 2010 at 06:45:00PM +0900, Isaku Yamahata wrote:
On Mon, Jul 12, 2010 at 08:59:14PM -0400, Kevin O'Connor wrote:
On Mon, Jul 12, 2010 at 08:47:47PM +0900, Isaku Yamahata wrote:
pam register offset is north bridge specific. So determine the offset based on found north bridge.
Is it really just the offset that is north bridge specific? I thought the entire process was very north bridge specific.
If so, I don't think it makes sense to pass back the pam0 register - instead the north bridge specific code should do the necessary work (using helper functions if possible).
I have the same concern with part 3 and 4 of this series.
I440fx and Q35 (all Intel chipset?) are similar in registers which seabios programs, so I choice to abstract it at register offset level. I don't expect that other vendor's chipset support is wanted.
Although it isn't currently used, the memory locking support is useful on real machines too. I'd prefer a solution that would work on both qemu and real machines.
It's minor for part 2 of the series, but I found part 3/4 to be hard to follow due to the way the flow of code jumps between machine specific code in dev-i440fx.c and the smm code in smm.c.
If you want more high level abstract, I'll respin the patch set.
I've been meaning to look through the full series of changes in your repo, but have not yet had a chance to do so. I hope to get to that in the next few days. Sorry for the delay.
-Kevin