SeaBIOS

seabios@seabios.org

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Re: SeaBIOS compile on OpenBSD with SeaVGABIOS planar & cga page offset support
by puffy daemon 27 Feb '19

27 Feb '19

I attach the patch for compiling under OpenBSD. Please, forget the first patch.

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SeaBIOS compile on OpenBSD with SeaVGABIOS planar & cga page offset support
by puffy daemon 26 Feb '19

26 Feb '19

Hello, I wrote an email few hours ago, and as no fast response given I decided to try to implement by myself. I got it, (or it seems), I am able to write to page > 0 in graphics mode. I attach you the patch to compile under OpenBSD and also write on page > 0 Also I attach the raw image (that only works on QEMU not BOCHS). But you can compile it if you want: https://github.com/hombrelogico/MyOwnOperatingSystem P.D: master branch is painting pixels very slow. The SeaBIOS of qemu package in OpenBSD is painting really faster.

1 0

[PATCH v3 0/2] Add menu item for activating TPM 2.0 PCR banks
by Stefan Berger 20 Feb '19

20 Feb '19

The following two patches add a menu item to the TPM 2.0 menu that allows a user to activate and deactivate the PCR banks the attached TPM 2.0 supports. This operation has to be done while in the firmware. Stefan v2->v3: - Activate the selection of activate PCR banks right from the menu - Undo some other changes, such as #define in src/utils.h v1->v2: - Refactor existing function for looking up the buffer size a hash needs to use a table instead; we extend the table then in patch 2 Stefan Berger (2): tcgbios: Use table to convert hash to buffer size tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks src/std/tcg.h | 17 ++++ src/tcgbios.c | 264 +++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 268 insertions(+), 13 deletions(-) -- 2.17.2

3 4

Need help! Seabios hangs on "Press ESC for boot menu" atom denverton c3538.
by dponamorev＠gmail.com 12 Feb '19

12 Feb '19

Seabios freezes (hangs) on "Press ESC for boot menu". Does not respond to the keyboard and does not boot from the sata disk. Last post code 0x7b. Console output, Coreboot 4.9 config and seabios config see below. BS: BS_PAYLOAD_LOAD times (us): entry 0 run 311644 exit 1598599 BS: Entering BS_PAYLOAD_BOOT state. Jumping to boot code at 000fcea0(7f755000) Timestamp - selfboot jump: 447304932782 CPU0: stack: 7f7be000 - 7f7bf000, lowest used address 7f7beafc, stack used: 1284 bytes SeaBIOS (version rel-1.12.0-0-ga698c89) BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30 Attempting to find coreboot table Found coreboot table forwarder. Now attempting to find coreboot memory map Add to e820 map: 00000000 00001000 2 Add to e820 map: 00001000 0009f000 1 Add to e820 map: 000a0000 00060000 2 Add to e820 map: 00100000 7f630000 1 Add to e820 map: 7f730000 004d0000 2 Add to e820 map: 7fc00000 00400000 2 Add to e820 map: e0000000 10000000 2 Add to e820 map: fed10000 00008000 2 Add to e820 map: 100000000 180000000 1 Add to e820 map: 00000000 00004000 1 SeaBIOS (version rel-1.12.0-0-ga698c89) BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30 Found coreboot cbmem console @ 7f7de000 Found mainboard Intel Harcuvar CRB malloc preinit Add to e820 map: 000a0000 00050000 -1 Add to e820 map: 000f0000 00010000 2 Add to e820 map: 7f6f0000 00040000 2 phys_alloc zone=0x000f08ec size=36352 align=20 ret=7f6e7160 (detail=0x7f6e7130) Relocating init from 0x000e7b80 to 0x7f6e7160 (size 36352) malloc init Found CBFS header at 0xffe20038 phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e7030 (detail=0x7f6e7000) Add romfile: cbfs master header (size=32) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6f60 (detail=0x7f6e6f30) Add romfile: fallback/romstage (size=27548) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6e90 (detail=0x7f6e6e60) Add romfile: fallback/ramstage (size=61295) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6dc0 (detail=0x7f6e6d90) Add romfile: config (size=882) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6cf0 (detail=0x7f6e6cc0) Add romfile: revision (size=570) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6c20 (detail=0x7f6e6bf0) Add romfile: fallback/postcar (size=18560) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6b50 (detail=0x7f6e6b20) Add romfile: fallback/dsdt.aml (size=6793) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6a80 (detail=0x7f6e6a50) Add romfile: fallback/payload (size=54784) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e69b0 (detail=0x7f6e6980) Add romfile: payload_config (size=1708) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e68e0 (detail=0x7f6e68b0) Add romfile: payload_revision (size=236) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6810 (detail=0x7f6e67e0) Add romfile: bootorder (size=55) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6740 (detail=0x7f6e6710) Add romfile: (size=875096) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6670 (detail=0x7f6e6640) Add romfile: cpu_microcode_blob.bin (size=10240) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e65a0 (detail=0x7f6e6570) Add romfile: (size=55128) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e64d0 (detail=0x7f6e64a0) Add romfile: fspt.bin (size=4096) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6400 (detail=0x7f6e63d0) Add romfile: (size=3992) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6330 (detail=0x7f6e6300) Add romfile: fspm.bin (size=589824) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6260 (detail=0x7f6e6230) Add romfile: (size=3992) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e6190 (detail=0x7f6e6160) Add romfile: fsps.bin (size=102400) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e60c0 (detail=0x7f6e6090) Add romfile: (size=114584) phys_alloc zone=0x7f6efecc size=156 align=10 ret=7f6e5ff0 (detail=0x7f6e5fc0) Add romfile: bootblock (size=32768) init ivt init bda Add to e820 map: 0009fc00 00000400 2 init bios32 init PMM init PNPBIOS table init keyboard init mouse init pic math cp init PCI probe phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5fa0 (detail=0x7f6e5f70) PCI device 00:00.0 (vd=8086:1980 c=0600) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5f50 (detail=0x7f6e5f20) PCI device 00:04.0 (vd=8086:19a1 c=0600) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5f00 (detail=0x7f6e5ed0) PCI device 00:05.0 (vd=8086:19a2 c=0807) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5eb0 (detail=0x7f6e5e80) PCI device 00:09.0 (vd=8086:19a4 c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5e60 (detail=0x7f6e5e30) PCI device 00:0b.0 (vd=8086:19a6 c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5e10 (detail=0x7f6e5de0) PCI device 00:0e.0 (vd=8086:19a8 c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5dc0 (detail=0x7f6e5d90) PCI device 00:0f.0 (vd=8086:19a9 c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5d70 (detail=0x7f6e5d40) PCI device 00:10.0 (vd=8086:19aa c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5d20 (detail=0x7f6e5cf0) PCI device 00:11.0 (vd=8086:19ab c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5cd0 (detail=0x7f6e5ca0) PCI device 00:12.0 (vd=8086:19ac c=0880) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5c80 (detail=0x7f6e5c50) PCI device 00:14.0 (vd=8086:19c2 c=0106) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5c30 (detail=0x7f6e5c00) PCI device 00:15.0 (vd=8086:19d0 c=0c03) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5be0 (detail=0x7f6e5bb0) PCI device 00:16.0 (vd=8086:19d1 c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5b90 (detail=0x7f6e5b60) PCI device 00:17.0 (vd=8086:19d2 c=0604) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5b40 (detail=0x7f6e5b10) PCI device 00:18.0 (vd=8086:19d3 c=0780) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5af0 (detail=0x7f6e5ac0) PCI device 00:1f.0 (vd=8086:19dc c=0601) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5aa0 (detail=0x7f6e5a70) PCI device 00:1f.2 (vd=8086:19de c=0580) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5a50 (detail=0x7f6e5a20) PCI device 00:1f.4 (vd=8086:19df c=0c05) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5a00 (detail=0x7f6e59d0) PCI device 00:1f.5 (vd=8086:19e0 c=0c80) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e59b0 (detail=0x7f6e5980) PCI device 07:00.0 (vd=8086:1306 c=0200) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5960 (detail=0x7f6e5930) PCI device 07:00.1 (vd=8086:1306 c=0200) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e5910 (detail=0x7f6e58e0) PCI device 08:00.0 (vd=8086:15e5 c=0200) phys_alloc zone=0x7f6efecc size=32 align=10 ret=7f6e58c0 (detail=0x7f6e5890) PCI device 08:00.1 (vd=8086:15e5 c=0200) Found 23 PCI devices (max PCI bus is 08) Relocating coreboot bios tables phys_alloc zone=0x7f6efed4 size=31 align=10 ret=f0960 (detail=0x7f6e5860) Copying SMBIOS entry point from 0x7f730000 to 0x000f0960 phys_alloc zone=0x7f6efed4 size=36 align=10 ret=f0930 (detail=0x7f6e5830) Copying ACPI RSDP from 0x7f731000 to 0x000f0930 rsdp=0x000f0930 rsdt=0x7f731030 table(50434146)=0x7f732d20 pm_tmr_blk=1808 Using pmtimer, ioport 0x1808 init timer Scan for VGA option rom No VGA found, scan for other display Turning on vga text mode console SeaBIOS (version rel-1.12.0-0-ga698c89) init usb phys_alloc zone=0x7f6efed8 size=72 align=10 ret=7f72ffb0 (detail=0x7f6e5800) XHCI init on dev 00:15.0: regs @ 0xdfec0000, 8 ports, 32 slots, 32 byte contexts XHCI protocol USB 2.00, 4 ports (offset 1), def 3011 XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 XHCI extcap 0xc0 @ 0xdfec8070 XHCI extcap 0x1 @ 0xdfec846c XHCI extcap 0xc6 @ 0xdfec84f4 XHCI extcap 0xc7 @ 0xdfec8500 XHCI extcap 0xc2 @ 0xdfec8600 XHCI extcap 0xa @ 0xdfec8700 phys_alloc zone=0x7f6efed8 size=264 align=40 ret=7f72fe80 (detail=0x7f6e57d0) phys_alloc zone=0x7f6efed8 size=16 align=40 ret=7f72fe40 (detail=0x7f6e57a0) phys_alloc zone=0x7f6efed8 size=288 align=100 ret=7f72fd00 (detail=0x7f6e5770) phys_alloc zone=0x7f6efed8 size=288 align=100 ret=7f72fb00 (detail=0x7f6e5740) configure_xhci: resetting configure_xhci: setup 18 scratch pad buffers phys_alloc zone=0x7f6efed8 size=144 align=40 ret=7f72fc40 (detail=0x7f6e5710) phys_alloc zone=0x7f6efed8 size=73728 align=1000 ret=7f71d000 (detail=0x7f6e56e0) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) xhci_hub_reset port #2: 0x00020ae1, powered, pls 7, speed 2 [Low] XHCI port #2: 0x00200a03, powered, enabled, pls 0, speed 2 [Low] set_address 0x7f72ffb0 phys_alloc zone=0x7f6efed8 size=316 align=100 ret=7f72f900 (detail=0x7f6e5660) phys_alloc zone=0x7f6efecc size=1056 align=800 ret=7f6e5000 (detail=0x7f6e5630) xhci_alloc_pipe: usbdev 0x7f6e56c0, ring 0x7f72f900, slotid 0, epid 1 phys_alloc zone=0x7f6efed8 size=1024 align=400 ret=7f72f400 (detail=0x7f6e5600) xhci_cmd_enable_slot: xhci_trb_queue: ring 0x7f72fd00 [nidx 1, len 0] xhci_doorbell: slotid 0, epid 0 xhci_process_events port #2: 0x00200a03, powered, enabled, pls 0, speed 2 [Low] xhci_process_events port #2: 0x00000a03, powered, enabled, pls 0, speed 2 [Low] xhci_process_events: ring 0x7f72fd00 [trb 0x7f72fd00, evt 0x7f72fe00, type 33, eidx 1, cc 1] xhci_alloc_pipe: enable slot: got slotid 1 xhci_cmd_address_device: slotid 1 xhci_trb_queue: ring 0x7f72fd00 [nidx 2, len 0] xhci_doorbell: slotid 0, epid 0 xhci_process_events: ring 0x7f72fd00 [trb 0x7f72fd10, evt 0x7f72fe00, type 33, eidx 2, cc 1] phys_free 7f6e5000 (detail=0x7f6e5630) xhci_realloc_pipe: usbdev 0x7f6e56c0, ring 0x7f72f900, slotid 1, epid 1 config_usb: 0x7f72fa20 xhci_trb_queue: ring 0x7f72f900 [nidx 1, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 2, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 3, len 0] xhci_doorbell: slotid 1, epid 1 xhci_process_events: ring 0x7f72f900 [trb 0x7f72f920, evt 0x7f72fa00, type 32, eidx 3, cc 1] device rev=0110 cls=00 sub=00 proto=00 size=8 xhci_realloc_pipe: usbdev 0x7f6e56c0, ring 0x7f72f900, slotid 1, epid 1 xhci_trb_queue: ring 0x7f72f900 [nidx 4, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 5, len 9] xhci_trb_queue: ring 0x7f72f900 [nidx 6, len 0] xhci_doorbell: slotid 1, epid 1 xhci_process_events: ring 0x7f72f900 [trb 0x7f72f950, evt 0x7f72fa00, type 32, eidx 6, cc 1] phys_alloc zone=0x7f6efecc size=59 align=10 ret=7f6e55c0 (detail=0x7f6e5630) xhci_trb_queue: ring 0x7f72f900 [nidx 7, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 8, len 59] xhci_trb_queue: ring 0x7f72f900 [nidx 9, len 0] xhci_doorbell: slotid 1, epid 1 xhci_process_events: ring 0x7f72f900 [trb 0x7f72f980, evt 0x7f72fa00, type 32, eidx 9, cc 1] xhci_trb_queue: ring 0x7f72f900 [nidx 10, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 11, len 0] xhci_doorbell: slotid 1, epid 1 xhci_process_events: ring 0x7f72f900 [trb 0x7f72f9a0, evt 0x7f72fa00, type 32, eidx 11, cc 1] usb_hid_setup 0x7f72fa20 xhci_trb_queue: ring 0x7f72f900 [nidx 12, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 13, len 0] xhci_doorbell: slotid 1, epid 1 xhci_process_events: ring 0x7f72f900 [trb 0x7f72f9c0, evt 0x7f72fa00, type 32, eidx 13, cc 1] xhci_trb_queue: ring 0x7f72f900 [nidx 14, len 8] xhci_trb_queue: ring 0x7f72f900 [nidx 15, len 0] xhci_doorbell: slotid 1, epid 1 xhci_process_events: ring 0x7f72f900 [trb 0x7f72f9e0, evt 0x7f72fa00, type 32, eidx 15, cc 1] phys_alloc zone=0x7f6efedc size=316 align=100 ret=ef600 (detail=0x7f6e5590) phys_alloc zone=0x7f6efed8 size=8 align=10 ret=7f72ffa0 (detail=0x7f6e5560) phys_alloc zone=0x7f6efecc size=1056 align=800 ret=7f6e5000 (detail=0x7f6e5530) xhci_alloc_pipe: usbdev 0x7f6e56c0, ring 0x000ef600, slotid 0, epid 3 xhci_cmd_configure_endpoint: slotid 1, add 0x9, del 0x0 xhci_trb_queue: ring 0x7f72fd00 [nidx 3, len 0] xhci_doorbell: slotid 0, epid 0 xhci_process_events: ring 0x7f72fd00 [trb 0x7f72fd20, evt 0x7f72fe00, type 33, eidx 3, cc 1] phys_free 7f6e5000 (detail=0x7f6e5530) USB keyboard initialized phys_free 7f6e55c0 (detail=0x7f6e5630) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) phys_alloc zone=0x7f6efecc size=28 align=10 ret=7f6e56c0 (detail=0x7f6e5690) phys_free 7f6e56c0 (detail=0x7f6e5690) init hard drives init ahci phys_alloc zone=0x7f6efedc size=2048 align=10 ret=eee00 (detail=0x7f6e56b0) phys_alloc zone=0x7f6efed4 size=20 align=10 ret=f0910 (detail=0x7f6e5630) AHCI controller at 00:14.0, iobase 0xdfed8000, irq 11 AHCI: cap 0xc3369f41, ports_impl 0xa phys_alloc zone=0x7f6efecc size=68 align=10 ret=7f6e5510 (detail=0x7f6e55d0) phys_alloc zone=0x7f6efecc size=1024 align=400 ret=7f6e5000 (detail=0x7f6e54e0) phys_alloc zone=0x7f6efecc size=256 align=100 ret=7f6e4f00 (detail=0x7f6e54b0) phys_alloc zone=0x7f6efecc size=256 align=100 ret=7f6e4e00 (detail=0x7f6e5480) AHCI/1: probing AHCI/1: link down phys_free 7f6e5000 (detail=0x7f6e54e0) phys_free 7f6e4f00 (detail=0x7f6e54b0) phys_free 7f6e4e00 (detail=0x7f6e5480) phys_free 7f6e5510 (detail=0x7f6e55d0) phys_alloc zone=0x7f6efecc size=68 align=10 ret=7f6e5510 (detail=0x7f6e55d0) phys_alloc zone=0x7f6efecc size=1024 align=400 ret=7f6e5000 (detail=0x7f6e54e0) phys_alloc zone=0x7f6efecc size=256 align=100 ret=7f6e4f00 (detail=0x7f6e54b0) phys_alloc zone=0x7f6efecc size=256 align=100 ret=7f6e4e00 (detail=0x7f6e5480) AHCI/3: probing AHCI/3: link up AHCI/3: send cmd ... AHCI/3: ... intbits 0x40000001, status 0x51 ... AHCI/3: ... finished, status 0x51, ERROR 0x4 AHCI/3: send cmd ... AHCI/3: ... intbits 0x2, status 0x58 ... AHCI/3: ... finished, status 0x58, OK phys_alloc zone=0x7f6efecc size=80 align=10 ret=7f6e5430 (detail=0x7f6e5400) AHCI/3: supported modes: udma 6, multi-dma 2, pio 4 AHCI/3: Set transfer mode to UDMA-6 AHCI/3: send cmd ... AHCI/3: ... intbits 0x1, status 0x50 ... AHCI/3: ... finished, status 0x50, OK phys_alloc zone=0x7f6efed4 size=68 align=10 ret=f08c0 (detail=0x7f6e4dd0) phys_free 7f6e5510 (detail=0x7f6e55d0) phys_free 7f6e5000 (detail=0x7f6e54e0) phys_free 7f6e4f00 (detail=0x7f6e54b0) phys_free 7f6e4e00 (detail=0x7f6e5480) phys_alloc zone=0x7f6efed8 size=1024 align=400 ret=7f72f000 (detail=0x7f6e55d0) phys_alloc zone=0x7f6efed8 size=256 align=100 ret=7f72f800 (detail=0x7f6e5530) phys_alloc zone=0x7f6efed8 size=256 align=100 ret=7f71cf00 (detail=0x7f6e5500) AHCI/3: registering: "AHCI/3: WDC WDS250G2B0B-00YS70 ATA-11 Hard-Disk (232 GiBytes)" phys_alloc zone=0x7f6efecc size=24 align=10 ret=7f6e5690 (detail=0x7f6e54d0) Registering bootable: AHCI/3: WDC WDS250G2B0B-00YS70 ATA-11 Hard-Disk (232 GiBytes) (type:2 prio:103 data:f08c0) init nvme init serial Found 3 serial ports Scan for option roms Attempting to init PCI bdf 00:00.0 (vd 8086:1980) Attempting to map option rom on dev 00:00.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:04.0 (vd 8086:19a1) Attempting to map option rom on dev 00:04.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:05.0 (vd 8086:19a2) Attempting to map option rom on dev 00:05.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:09.0 (vd 8086:19a4) Attempting to map option rom on dev 00:09.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:0b.0 (vd 8086:19a6) Attempting to map option rom on dev 00:0b.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:0e.0 (vd 8086:19a8) Attempting to map option rom on dev 00:0e.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:0f.0 (vd 8086:19a9) Attempting to map option rom on dev 00:0f.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:10.0 (vd 8086:19aa) Attempting to map option rom on dev 00:10.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:11.0 (vd 8086:19ab) Attempting to map option rom on dev 00:11.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:12.0 (vd 8086:19ac) Attempting to map option rom on dev 00:12.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:16.0 (vd 8086:19d1) Attempting to map option rom on dev 00:16.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:17.0 (vd 8086:19d2) Attempting to map option rom on dev 00:17.0 Skipping non-normal pci device (type=1) Attempting to init PCI bdf 00:18.0 (vd 8086:19d3) Attempting to map option rom on dev 00:18.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:1f.0 (vd 8086:19dc) Attempting to map option rom on dev 00:1f.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:1f.2 (vd 8086:19de) Attempting to map option rom on dev 00:1f.2 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:1f.4 (vd 8086:19df) Attempting to map option rom on dev 00:1f.4 Option rom sizing returned 0 0 Attempting to init PCI bdf 00:1f.5 (vd 8086:19e0) Attempting to map option rom on dev 00:1f.5 Option rom sizing returned 0 0 Attempting to init PCI bdf 07:00.0 (vd 8086:1306) Attempting to map option rom on dev 07:00.0 Option rom sizing returned 0 0 Attempting to init PCI bdf 07:00.1 (vd 8086:1306) Attempting to map option rom on dev 07:00.1 Option rom sizing returned 0 0 Attempting to init PCI bdf 08:00.0 (vd 8086:15e5) Attempting to map option rom on dev 08:00.0 Option rom sizing returned dfd00000 fff80000 Inspecting possible rom at 0xdfd00000 (vd=8086:15e5 bdf=08:00.0) No option rom signature (got beef) Attempting to init PCI bdf 08:00.1 (vd 8086:15e5) Attempting to map option rom on dev 08:00.1 Option rom sizing returned dfd80000 fff80000 Inspecting possible rom at 0xdfd80000 (vd=8086:15e5 bdf=08:00.1) No option rom signature (got beef) Press ESC for boot menu. # # Automatically generated file; DO NOT EDIT. # SeaBIOS Configuration # # # General Features # CONFIG_COREBOOT=y # CONFIG_QEMU is not set # CONFIG_CSM is not set # CONFIG_QEMU_HARDWARE is not set # CONFIG_THREADS is not set CONFIG_RELOCATE_INIT=y CONFIG_BOOTMENU=y # CONFIG_BOOTSPLASH is not set # CONFIG_BOOTORDER is not set CONFIG_COREBOOT_FLASH=y CONFIG_LZMA=y CONFIG_CBFS_LOCATION=0 # CONFIG_MULTIBOOT is not set # CONFIG_ENTRY_EXTRASTACK is not set CONFIG_MALLOC_UPPERMEMORY=y CONFIG_ROM_SIZE=0 # # Hardware support # CONFIG_ATA=y # CONFIG_ATA_DMA is not set # CONFIG_ATA_PIO32 is not set CONFIG_AHCI=y CONFIG_SDCARD=y # CONFIG_MEGASAS is not set # CONFIG_FLOPPY is not set # CONFIG_FLASH_FLOPPY is not set CONFIG_NVME=y # CONFIG_PS2PORT is not set CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y CONFIG_USB_EHCI=y CONFIG_USB_XHCI=y CONFIG_USB_MSC=y CONFIG_USB_UAS=y CONFIG_USB_HUB=y CONFIG_USB_KEYBOARD=y CONFIG_USB_MOUSE=y CONFIG_SERIAL=y CONFIG_SERCON=y # CONFIG_LPT is not set CONFIG_RTC_TIMER=y CONFIG_HARDWARE_IRQ=y CONFIG_PMTIMER=y CONFIG_TSC_TIMER=y # # BIOS interfaces # CONFIG_DRIVES=y CONFIG_CDROM_BOOT=y CONFIG_CDROM_EMU=y CONFIG_PCIBIOS=y CONFIG_APMBIOS=y CONFIG_PNPBIOS=y CONFIG_OPTIONROMS=y CONFIG_PMM=y CONFIG_BOOT=y CONFIG_KEYBOARD=y CONFIG_KBD_CALL_INT15_4F=y CONFIG_MOUSE=y # CONFIG_S3_RESUME is not set # CONFIG_VGAHOOKS is not set # CONFIG_DISABLE_A20 is not set # # VGA ROM # CONFIG_NO_VGABIOS=y # CONFIG_VGA_GEODEGX2 is not set # CONFIG_VGA_GEODELX is not set # CONFIG_VGA_COREBOOT is not set # CONFIG_BUILD_VGABIOS is not set CONFIG_VGA_EXTRA_STACK_SIZE=512 # # Debugging # CONFIG_DEBUG_LEVEL=8 CONFIG_DEBUG_SERIAL=y CONFIG_DEBUG_SERIAL_PORT=0x3f8 CONFIG_DEBUG_COREBOOT=y # # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y CONFIG_TIMESTAMPS_ON_CONSOLE=y # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set # CONFIG_UBSAN is not set # CONFIG_NO_RELOCATABLE_RAMSTAGE is not set CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # # # Important: Run 'make distclean' before switching boards # # CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IEI is not set CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_OCP is not set # CONFIG_VENDOR_OPENCELLULAR is not set # CONFIG_VENDOR_PACKARDBELL is not set # CONFIG_VENDOR_PCENGINES is not set # CONFIG_VENDOR_PURISM is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SCALEWAY is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SIFIVE is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TI is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/harcuvar" CONFIG_MAINBOARD_PART_NUMBER="Harcuvar CRB" CONFIG_MAX_CPUS=16 CONFIG_CBFS_SIZE=0x200000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_PAYLOAD_CONFIGFILE="/home/dubel/Work/2019/coreboot-4.9/FSP/seabios_config" CONFIG_MAINBOARD_VENDOR="Intel" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="11022019" CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" CONFIG_DEVICETREE="devicetree.cb" CONFIG_POST_IO=y CONFIG_DCACHE_RAM_BASE=0xfef00000 CONFIG_DCACHE_RAM_SIZE=0xb0000 CONFIG_MAX_REBOOT_CNT=3 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_FMDFILE="" CONFIG_C_ENV_BOOTBLOCK_SIZE=0x8000 CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_POST_DEVICE=y CONFIG_DRIVERS_UART_8250IO=y # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_TTYS0_LCS=3 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set # CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set # CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set # CONFIG_BOARD_INTEL_CANNONLAKE_RVPU is not set # CONFIG_BOARD_INTEL_CANNONLAKE_RVPY is not set # # Coffeelake RVP # # CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set # CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set # CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set # CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set # CONFIG_BOARD_INTEL_D510MO is not set # CONFIG_BOARD_INTEL_D945GCLF is not set # CONFIG_BOARD_INTEL_DCP847SKE is not set # CONFIG_BOARD_INTEL_DG41WV is not set # CONFIG_BOARD_INTEL_DG43GT is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set # CONFIG_BOARD_INTEL_GALILEO is not set # CONFIG_BOARD_INTEL_GLKRVP is not set CONFIG_BOARD_INTEL_HARCUVAR=y # CONFIG_BOARD_INTEL_ICELAKE_RVPU is not set # CONFIG_BOARD_INTEL_ICELAKE_RVPY is not set # CONFIG_BOARD_INTEL_KBLRVP3 is not set # CONFIG_BOARD_INTEL_KBLRVP7 is not set # CONFIG_BOARD_INTEL_KBLRVP8 is not set # CONFIG_BOARD_INTEL_KUNIMITSU is not set # CONFIG_BOARD_INTEL_LEAFHILL is not set # CONFIG_BOARD_INTEL_LITTLEPLAINS is not set # CONFIG_BOARD_INTEL_MINNOW3 is not set # CONFIG_BOARD_INTEL_MINNOWMAX is not set # CONFIG_BOARD_INTEL_MOHONPEAK is not set # CONFIG_BOARD_INTEL_SKLSDLBRK is not set # CONFIG_BOARD_INTEL_STRAGO is not set # CONFIG_BOARD_INTEL_WTM2 is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Harcuvar CRB" # CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set # CONFIG_ENABLE_FSP_MEMORY_DOWN is not set # CONFIG_HAVE_IFD_BIN is not set CONFIG_ADD_FSP_BINARIES=y CONFIG_FSP_M_FILE="./FSP/FSP_M.rom" CONFIG_FSP_S_FILE="./FSP/FSP_S.rom" CONFIG_FSP_S_CBFS="fsps.bin" CONFIG_FSP_M_CBFS="fspm.bin" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAINBOARD_VERSION="2.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_CPU_MICROCODE_CBFS_LEN=0x0ff80 CONFIG_CPU_MICROCODE_CBFS_LOC=0xfff20040 CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 CONFIG_BOARD_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set # # Chipset # # # SoC # CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_HEAP_SIZE=0x4000 CONFIG_SMM_TSEG_SIZE=0x200000 CONFIG_SMM_RESERVED_SIZE=0x000000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_CAVIUM_CN81XX is not set CONFIG_ARCH_ARMV8_EXTENSION=0 CONFIG_STACK_SIZE=0x1000 # CONFIG_SOC_CAVIUM_COMMON is not set # CONFIG_SOC_INTEL_GLK is not set CONFIG_PCR_BASE_ADDRESS=0xfd000000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_FSP_M_ADDR=0xfff32000 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_CPU_BCLK_MHZ=100 # CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set # CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_CLK_PM is not set CONFIG_TTYS0_BASE=0x3f8 # CONFIG_SOC_INTEL_COFFEELAKE is not set # CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set CONFIG_SOC_INTEL_DENVERTON_NS=y CONFIG_FSP_T_ADDR=0xfff30000 CONFIG_FSP_S_ADDR=0xfffc3000 CONFIG_IQAT_ENABLE=y CONFIG_IQAT_MEMORY_REGION_SIZE=0x100000 CONFIG_HSUART_DEV=0x1a # CONFIG_NON_LEGACY_UART_MODE is not set CONFIG_LEGACY_UART_MODE=y CONFIG_CPU_MICROCODE_HEADER_FILES="./FSP/microcode.h" CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_INTEL_KABYLAKE is not set CONFIG_SOC_INTEL_COMMON=y # # Intel SoC Common Code # CONFIG_SOC_INTEL_COMMON_BLOCK=y CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y # CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_CAR is not set # CONFIG_INTEL_CAR_NEM is not set # CONFIG_INTEL_CAR_CQOS is not set # CONFIG_INTEL_CAR_NEM_ENHANCED is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_CSE is not set CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y CONFIG_PCR_COMMON_IOSF_1_0=y CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y # CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set CONFIG_POWER_STATE_ON_AFTER_FAILURE=y # CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set # CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 CONFIG_SA_PCIEX_LENGTH=0x10000000 # CONFIG_SA_ENABLE_IMR is not set # CONFIG_SA_ENABLE_DPR is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set # # Intel SoC Common PCH Code # # # Intel SoC Common coreboot stages # # CONFIG_DISPLAY_SMM_MEMORY_MAP is not set CONFIG_SOC_INTEL_COMMON_RESET=y # CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE is not set # CONFIG_ACPI_CONSOLE is not set # CONFIG_SOC_INTEL_COMMON_ACPI is not set # CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set # CONFIG_SOC_INTEL_COMMON_NHLT is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_MEDIATEK_MT8183 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_QUALCOMM_SDM845 is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set # CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set # # CPU # # CONFIG_CPU_ALLWINNER_A10 is not set CONFIG_XIP_ROM_SIZE=0x10000 CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set # CONFIG_SSE2 is not set # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set CONFIG_PARALLEL_MP=y # CONFIG_PARALLEL_MP_AP_WORK is not set # CONFIG_UDELAY_IO is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y CONFIG_TSC_CONSTANT_RATE=y CONFIG_TSC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y # CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y CONFIG_SMM_TSEG=y CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 CONFIG_SMM_STUB_STACK_SIZE=0x400 # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set # CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y CONFIG_NO_CAR_GLOBAL_MIGRATION=y CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 # CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set # CONFIG_USES_MICROCODE_HEADER_FILES is not set # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y # CONFIG_CPU_MICROCODE_CBFS_NONE is not set # # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set # CONFIG_NORTHBRIDGE_AMD_PI is not set CONFIG_MAX_PIRQ_LINKS=4 # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set # CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y # CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # # CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # # CONFIG_EC_GOOGLE_WILCO is not set CONFIG_EC_BASE_ACPI_DATA=0x930 CONFIG_EC_BASE_ACPI_COMMAND=0x934 CONFIG_EC_BASE_HOST_DATA=0x940 CONFIG_EC_BASE_HOST_COMMAND=0x944 CONFIG_EC_BASE_PACKET=0x950 CONFIG_SEABIOS_PS2_TIMEOUT=0 # # Intel Firmware # # CONFIG_CAVIUM_BDK is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set CONFIG_UDK_2015_BINDING=y # CONFIG_UDK_2017_BINDING is not set CONFIG_UDK_2013_VERSION=2013 CONFIG_UDK_2015_VERSION=2015 CONFIG_UDK_2017_VERSION=2017 CONFIG_UDK_VERSION=2015 # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set # CONFIG_ARCH_ROMSTAGE_ARM is not set # CONFIG_ARCH_RAMSTAGE_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set # CONFIG_ARCH_VERSTAGE_ARMV4 is not set # CONFIG_ARCH_ROMSTAGE_ARMV4 is not set # CONFIG_ARCH_RAMSTAGE_ARMV4 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set # CONFIG_ARCH_VERSTAGE_ARMV7 is not set # CONFIG_ARCH_ROMSTAGE_ARMV7 is not set # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set # CONFIG_ARCH_VERSTAGE_ARMV7_R is not set # CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set # CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set # CONFIG_ARCH_VERSTAGE_ARM64 is not set # CONFIG_ARCH_ROMSTAGE_ARM64 is not set # CONFIG_ARCH_RAMSTAGE_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set # CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set # CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set # CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set # CONFIG_ARM64_USE_ARCH_TIMER is not set # CONFIG_ARM64_A53_ERRATUM_843419 is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_BOOTBLOCK_MIPS is not set # CONFIG_ARCH_VERSTAGE_MIPS is not set # CONFIG_ARCH_ROMSTAGE_MIPS is not set # CONFIG_ARCH_RAMSTAGE_MIPS is not set # CONFIG_ARCH_PPC64 is not set # CONFIG_ARCH_BOOTBLOCK_PPC64 is not set # CONFIG_ARCH_VERSTAGE_PPC64 is not set # CONFIG_ARCH_ROMSTAGE_PPC64 is not set # CONFIG_ARCH_RAMSTAGE_PPC64 is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_BOOTBLOCK_RISCV is not set # CONFIG_ARCH_VERSTAGE_RISCV is not set # CONFIG_ARCH_ROMSTAGE_RISCV is not set # CONFIG_ARCH_RAMSTAGE_RISCV is not set # CONFIG_RISCV_USE_ARCH_TIMER is not set CONFIG_ARCH_X86=y CONFIG_ARCH_BOOTBLOCK_X86_32=y CONFIG_ARCH_VERSTAGE_X86_32=y CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_BOOTBLOCK_X86_64 is not set # CONFIG_ARCH_VERSTAGE_X86_64 is not set # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_POSTCAR_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set CONFIG_RAMBASE=0xe00000 CONFIG_RAMTOP=0x1000000 # CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set # CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set # CONFIG_HPET_ADDRESS_OVERRIDE is not set CONFIG_HPET_ADDRESS=0xfed00000 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POSTCAR_STAGE=y # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set CONFIG_BOOTBLOCK_SIMPLE=y # CONFIG_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set CONFIG_COLLECT_TIMESTAMPS_TSC=y # CONFIG_PAGING_IN_CACHE_AS_RAM is not set # CONFIG_IDT_IN_EVERY_STAGE is not set CONFIG_HAVE_CF9_RESET=y # # Devices # # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set # CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set # CONFIG_VGA_ROM_RUN is not set CONFIG_NO_GFX_INIT=y # CONFIG_MULTIPLE_VGA_ADAPTERS is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set CONFIG_PCI=y # CONFIG_NO_MMCONF_SUPPORT is not set CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_ELOG is not set # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set CONFIG_CACHE_MRC_SETTINGS=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 # CONFIG_MRC_SETTINGS_PROTECT is not set # CONFIG_HAS_RECOVERY_MRC_CACHE is not set # CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set # CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set # CONFIG_MRC_WRITE_NV_LATE is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SMMSTORE is not set # CONFIG_SMMSTORE_IN_CBFS is not set CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y CONFIG_SPI_FLASH_NO_FAST_READ=y CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_DRIVERS_UART_8250MEM_32 is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set # CONFIG_HAVE_USBDEBUG is not set # CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_VPD is not set # CONFIG_DRIVERS_AMD_PI is not set # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set # CONFIG_DRIVERS_I2C_MAX98373 is not set # CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCA9538 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set # CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set # CONFIG_DRIVERS_I2C_RX6110SA is not set # CONFIG_DRIVERS_I2C_SX9310 is not set # CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set # CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set # CONFIG_DISPLAY_HOBS is not set # CONFIG_DISPLAY_UPD_DATA is not set CONFIG_CHECKLIST_DATA_FILE_LOCATION="src/vendorcode/intel/fsp/fsp2_0/checklist" CONFIG_PLATFORM_USES_FSP2_0=y # CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set # CONFIG_DISPLAY_FSP_HEADER is not set CONFIG_FSP_T_CBFS="fspt.bin" CONFIG_FSP_T_FILE="./FSP/FSP_T.rom" CONFIG_FSP_CAR=y # CONFIG_FSP_M_XIP is not set # CONFIG_FSP_T_XIP is not set # CONFIG_FSP_USES_CB_STACK is not set # CONFIG_VERIFY_HOBS is not set # CONFIG_DISPLAY_FSP_VERSION_INFO is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set # CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_INTEL_GMA_SWSMISCI is not set # CONFIG_DRIVER_INTEL_I210 is not set # CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set # CONFIG_DRIVERS_INTEL_WIFI is not set # CONFIG_USE_SAR is not set # CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_LPC_TPM is not set # CONFIG_MAINBOARD_HAS_LPC_TPM is not set # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set # CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set # CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVERS_USB_ACPI is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set # CONFIG_COMMONLIB_STORAGE is not set # # Security # # # Verified Boot (vboot) # # # Trusted Platform Module # CONFIG_USER_NO_TPM=y # CONFIG_ACPI_SATA_GENERATOR is not set CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y # CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set # CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y # CONFIG_RTC is not set # # Console # CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_SERIAL=y # # I/O mapped, 8250-compatible # # # Serial port base address = 0x3f8 # # CONFIG_CONSOLE_SERIAL_921600 is not set # CONFIG_CONSOLE_SERIAL_460800 is not set # CONFIG_CONSOLE_SERIAL_230400 is not set CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set # CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set CONFIG_HAVE_MONOTONIC_TIMER=y # CONFIG_GENERIC_UDELAY is not set # CONFIG_TIMER_QUEUE is not set # CONFIG_HAVE_OPTION_TABLE is not set # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y # CONFIG_USE_WATCHDOG_ON_BOOT is not set # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y # CONFIG_COMMON_FADT is not set # CONFIG_ACPI_NHLT is not set # # System tables # # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y # # Payload # # CONFIG_PAYLOAD_NONE is not set # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_LINUXBOOT is not set CONFIG_PAYLOAD_SEABIOS=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_YABITS is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" CONFIG_SEABIOS_STABLE=y # CONFIG_SEABIOS_MASTER is not set # CONFIG_SEABIOS_REVISION is not set # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set CONFIG_SEABIOS_BOOTORDER_FILE="./FSP/bootorder" # CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set CONFIG_SEABIOS_DEBUG_LEVEL=8 CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set # CONFIG_PAYLOAD_FIT_SUPPORT is not set CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # # Secondary Payloads # # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set # CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set # CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging # # # CPU Debug Settings # CONFIG_HAVE_DISPLAY_MTRRS=y # CONFIG_DISPLAY_MTRRS is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # # General Debug Settings # # CONFIG_GDB_STUB is not set CONFIG_FATAL_ASSERTS=y CONFIG_HAVE_DEBUG_GPIO=y CONFIG_DEBUG_GPIO=y # CONFIG_DEBUG_CBFS is not set # CONFIG_HAVE_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set CONFIG_DEBUG_BOOT_STATE=y # CONFIG_DEBUG_ADA_CODE is not set # CONFIG_HAVE_EM100_SUPPORT is not set CONFIG_NO_EDID_FILL_FB=y # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set # CONFIG_NO_XIP_EARLY_STAGES is not set CONFIG_EARLY_CBMEM_INIT=y # CONFIG_EARLY_CBMEM_LIST is not set CONFIG_RELOCATABLE_MODULES=y CONFIG_NO_STAGE_CACHE=y CONFIG_C_ENVIRONMENT_BOOTBLOCK=y

3 2

[EC] ACPI DSDT not complete
by Johnny Sorocil 10 Feb '19

10 Feb '19

First thank you all for good work, is pretty impressive to have (as it is possible to be) open source version of firmware for modern x86 black box. Not sure if this is right mailing list, if not, please redirect me to the correct one. I am using CoreBoot with SeaBIOS as a payload for ThinkPad T430s to boot FreeBSD (but with Linux problem is same). DSDT provided by CoreBoot is missing battery charge start (BCTG, BCCS) and stop (BCSG, BCSS) thresholds. I have tried to boot OS with OEM DSDT table (either included on flash or OS override of the default DSDT found in RAM) and that doesn't work - USB timeouts, no cpu frequency scalling, and other problems. I have tried to patch CoreBoot provided DSDT but without success - ACPI is a little too much for me: I don't know how to implement missing methods nor how to connect EC registers with ACPI methods. Can someone push me in the right direction? Some addition questions related to embedded controller: - How to get/set keyboard backlight? - How to get/set LCD backlight level? - Is it possible to play some tones when charges is connected/disconnected or battery is at critical charge?

1 0

Re: [Qemu-devel] [PULL 1/1] update seabios to master snapshot
by Gerd Hoffmann 05 Feb '19

05 Feb '19

On Mon, Feb 04, 2019 at 10:25:34AM -0500, Emilio G. Cota wrote: > On Mon, Feb 04, 2019 at 12:20:33 +0100, Gerd Hoffmann wrote: > > > How can I bisect seabios? I can't find a recipe to generate > > > the .bin files included in this commit. > > > > "make -C roms bios" will build it, using the roms/seabios submodule. > > Thanks! This helped. > > The regression was introduced between 1.11 and 1.12 by: > 96060ad ("tpm: Wait for interface startup when probing", 2018-03-02) > > Fortunately, the issue is fixed right after the 1.12 tag by: > 42efebd ("tpm: Check for TPM related ACPI tables before attempting hw > probe", 2018-11-27) > > Are there any further seabios updates planned for 4.0? Would be > nice to get this fix in. Created 1.12-stable branch and cherry-picked this fix. We'll do a 1.12.1 stable release in time for qemu 4.0. cheers, Gerd

1 0

bmp/bootsplash: Added support for 16/24/32bpp in one function
by Joseph Pacheco-Corwin 05 Feb '19

05 Feb '19

Specifically added support for 16 and 32bpp files, in addition to 24bpp. The function bmp_show() in bmp.c has had the hardcoded check for 24bpp replaced with a general bpp check that uses a % to check for remainder, and returns 1 if the remainder is >0. The previous method for adjusting the BMP data (raw_data_format_adjust_24bpp) relied on a preset 3*bytes_per_line_src, this has been changed and the multiplication is now performed in the function's arguments. This change still allows someone else to reuse the same function for 1/2/4bpp support if necessary. The file util.h has been modified to reflect this decision. The changes to raw_data_format_adjust() is based on an abandoned patch by Gert Menke (submitted March 14, 2017), credit to them for that change and the addition of *bpp to bmp_get_info(). Any feedback? I would appreciate it. Signed-off-by: Joseph S. Pacheco-Corwin <hammersamatom(a)gmail.com> --- src/bmp.c | 19 +++++++++---------- src/bootsplash.c | 17 +++++++++++++---- src/util.h | 2 +- 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/src/bmp.c b/src/bmp.c index 96a2b3f..fecc295 100644 --- a/src/bmp.c +++ b/src/bmp.c @@ -56,10 +56,9 @@ typedef struct tagRGBQUAD { * arrange horizontal pixel data, add extra space in the dest buffer * for every line */ -static void raw_data_format_adjust_24bpp(u8 *src, u8 *dest, int width, - int height, int bytes_per_line_dest) +static void raw_data_format_adjust(u8 *src, u8 *dest, int width, + int height, int bytes_per_line_src, int bytes_per_line_dest) { - int bytes_per_line_src = 3 * width; int i; for (i = 0 ; i < height ; i++) { memcpy(dest + i * bytes_per_line_dest, @@ -95,22 +94,22 @@ int bmp_decode(struct bmp_decdata *bmp, unsigned char *data, int data_size) } /* get bmp properties */ -void bmp_get_size(struct bmp_decdata *bmp, int *width, int *height) +void bmp_get_info(struct bmp_decdata *bmp, int *width, int *height, int *bpp) { *width = bmp->width; *height = bmp->height; + *bpp = bmp->bpp; } /* flush flat picture data to *pc */ -int bmp_show(struct bmp_decdata *bmp, unsigned char *pic, int width - , int height, int depth, int bytes_per_line_dest) +int bmp_show(struct bmp_decdata *bmp, unsigned char *pic, int width, + int height, int depth, int bytes_per_line_dest) { if (bmp->datap == pic) return 0; - /* now only support 24bpp bmp file */ - if ((depth == 24) && (bmp->bpp == 24)) { - raw_data_format_adjust_24bpp(bmp->datap, pic, width, height, - bytes_per_line_dest); + if ((depth == bmp->bpp) && (bmp->bpp%8 == 0)) { + raw_data_format_adjust(bmp->datap, pic, width, height, + (bmp->bpp/8)*width, bytes_per_line_dest); return 0; } return 1; diff --git a/src/bootsplash.c b/src/bootsplash.c index 165c98d..401c348 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -172,10 +172,13 @@ enable_bootsplash(void) dprintf(1, "bmp_decode failed with return code %d...\n", ret); goto done; } - bmp_get_size(bmp, &width, &height); - bpp_require = 24; + bmp_get_info(bmp, &width, &height, &bpp_require); } - /* jpeg would use 16 or 24 bpp video mode, BMP use 24bpp mode only */ + + /* jpeg would use 16 or 24 bpp video mode, BMP uses 8/16/24/32 bpp mode. + * 8bpp for BMP has corrupted colors, and lower than 8bpp fails to display + * or results in a loop. + */ // Try to find a graphics mode with the corresponding dimensions. int videomode = find_videomode(vesa_info, mode_info, width, height, @@ -192,7 +195,13 @@ enable_bootsplash(void) dprintf(3, "bytes per scanline: %d\n", mode_info->bytes_per_scanline); dprintf(3, "bits per pixel: %d\n", depth); - // Allocate space for image and decompress it. + // Allocate space for image and decompress it. + /* + * Has a weird issue with low bpp image files, imagesize is not + * consistent. Example: 8bpp images are correct, being essentially + * multiplied/divided by 1, but if you use 4bpp images, width is divided by + * 8, when it should be divided by 2. + */ int imagesize = height * mode_info->bytes_per_scanline; picture = malloc_tmphigh(imagesize); if (!picture) { diff --git a/src/util.h b/src/util.h index 6dd080f..9c06850 100644 --- a/src/util.h +++ b/src/util.h @@ -12,7 +12,7 @@ void handle_1553(struct bregs *regs); // bmp.c struct bmp_decdata *bmp_alloc(void); int bmp_decode(struct bmp_decdata *bmp, unsigned char *data, int data_size); -void bmp_get_size(struct bmp_decdata *bmp, int *width, int *height); +void bmp_get_info(struct bmp_decdata *bmp, int *width, int *height, int *bpp); int bmp_show(struct bmp_decdata *bmp, unsigned char *pic, int width , int height, int depth, int bytes_per_line_dest); -- 2.20.1

2 4

Affordable SOIC8 SMT sockets for BIOS chips (15pcs / 36E + cheeap shipping)
by Ivan Ivanov 02 Feb '19

02 Feb '19

Just sharing our pleasant experience and nice find :) These SOIC8 SMT sockets for BIOS chips are too expensive at AliExpress (don't know why) - and to order them directly from Dediprog is economically inefficient because last time I checked they offered only overpriced express shipping - the cost of which is comparable to the price of sockets themselves! - But we are patient people and don't want to overpay that much for shipping regardless of its' speed. So we decided to order from this EU-based "The LAB eShop" : https://www.thelabeshop.com/en/Programmer-Emulators/SPI-Flash-Programmers/A… They are asking 36E (41US) for 15pcs sockets. Dediprog's price is 30US for 15pcs sockets, but "thanks" to their overpriced express shipping: "thelabeshop" prices are more affordable if you need just the sockets - they have an ordinary cheap post shipping method available with a tracking number, for 5 or 6. Although our first package has been lost, they kindly sent it again without any extra fees and this time it got delivered :) All 15 pcs sockets have these rectangular plastic caps and were reliably packet in a plastic ribbon to protect their fragile pins and for more convenience. If you need some photos we could share. What is also great about this "thelabeshop" is that, like aliexpress, they don't require you to use paypal (paypal adds unnecessary extra fees and has a horrible ethics / customer service). Payment could be done by a credit card. So if you need these rare SOIC8 sockets, "thelabeshop" price seems to be the most affordable. They also have SOIC16 sockets, although their expensive 58E price seems to be a mistake and maybe they could lower it for you if you would contact them - type "SOK-SPI-16W" at their search field if you are interested. And to find SOIC8, write "SOK-SPI-8W". These sockets could be very useful for routers or laptop motherboards, although you need a steady hand or ask professional to install them for you. Best regards, Ivan Ivanov

1 0

[PATCH 0/2] Add menu item for activating TPM 2.0 PCR banks
by Stefan Berger 30 Jan '19

30 Jan '19

The following two patches add a menu item to the TPM 2.0 menu that allows a user to activate and deactivate the PCR banks the attached TPM 2.0 supports. This operation has to be done while in the firmware. Stefan v1->v2: - Refactor existing function for looking up the buffer size a hash needs to use a table instead; we extend the table then in patch 2 Stefan Berger (2): tcgbios: Use table to convert hash to buffer size tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks src/std/tcg.h | 18 ++++ src/tcgbios.c | 270 +++++++++++++++++++++++++++++++++++++++++++++++--- src/util.h | 2 + 3 files changed, 275 insertions(+), 15 deletions(-) -- 2.17.2

2 4

[PATCH] build: Allow to use cross C preprocessor
by Roman Bolshakov 29 Jan '19

29 Jan '19

An attempt to cross-compile SeaBIOS on macOS can fail because host C preprocessor doesn't comprehend the command line options: Compiling IASL src/fw/acpi-dsdt.hex cpp -P -MD -MT src/fw/acpi-dsdt.hex src/fw/acpi-dsdt.dsl -o out/src/fw/acpi-dsdt.dsl.i.orig clang: error: no input files make: *** [src/fw/acpi-dsdt.hex] Error 1 Signed-off-by: Roman Bolshakov <r.bolshakov(a)yadro.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d2d11db..909c0a1 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ OBJCOPY=$(CROSS_PREFIX)objcopy OBJDUMP=$(CROSS_PREFIX)objdump STRIP=$(CROSS_PREFIX)strip PYTHON=python -CPP=cpp +CPP=$(CROSS_PREFIX)cpp IASL:=iasl LD32BIT_FLAG:=-melf_i386 -- 2.20.1

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