SeaBIOS

seabios@seabios.org

3783 discussions

bmp/bootsplash: Added support for 16/24/32bpp in one function
by Joseph Pacheco-Corwin 05 Feb '19

05 Feb '19

Specifically added support for 16 and 32bpp files, in addition to 24bpp. The function bmp_show() in bmp.c has had the hardcoded check for 24bpp replaced with a general bpp check that uses a % to check for remainder, and returns 1 if the remainder is >0. The previous method for adjusting the BMP data (raw_data_format_adjust_24bpp) relied on a preset 3*bytes_per_line_src, this has been changed and the multiplication is now performed in the function's arguments. This change still allows someone else to reuse the same function for 1/2/4bpp support if necessary. The file util.h has been modified to reflect this decision. The changes to raw_data_format_adjust() is based on an abandoned patch by Gert Menke (submitted March 14, 2017), credit to them for that change and the addition of *bpp to bmp_get_info(). Any feedback? I would appreciate it. Signed-off-by: Joseph S. Pacheco-Corwin <hammersamatom(a)gmail.com> --- src/bmp.c | 19 +++++++++---------- src/bootsplash.c | 17 +++++++++++++---- src/util.h | 2 +- 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/src/bmp.c b/src/bmp.c index 96a2b3f..fecc295 100644 --- a/src/bmp.c +++ b/src/bmp.c @@ -56,10 +56,9 @@ typedef struct tagRGBQUAD { * arrange horizontal pixel data, add extra space in the dest buffer * for every line */ -static void raw_data_format_adjust_24bpp(u8 *src, u8 *dest, int width, - int height, int bytes_per_line_dest) +static void raw_data_format_adjust(u8 *src, u8 *dest, int width, + int height, int bytes_per_line_src, int bytes_per_line_dest) { - int bytes_per_line_src = 3 * width; int i; for (i = 0 ; i < height ; i++) { memcpy(dest + i * bytes_per_line_dest, @@ -95,22 +94,22 @@ int bmp_decode(struct bmp_decdata *bmp, unsigned char *data, int data_size) } /* get bmp properties */ -void bmp_get_size(struct bmp_decdata *bmp, int *width, int *height) +void bmp_get_info(struct bmp_decdata *bmp, int *width, int *height, int *bpp) { *width = bmp->width; *height = bmp->height; + *bpp = bmp->bpp; } /* flush flat picture data to *pc */ -int bmp_show(struct bmp_decdata *bmp, unsigned char *pic, int width - , int height, int depth, int bytes_per_line_dest) +int bmp_show(struct bmp_decdata *bmp, unsigned char *pic, int width, + int height, int depth, int bytes_per_line_dest) { if (bmp->datap == pic) return 0; - /* now only support 24bpp bmp file */ - if ((depth == 24) && (bmp->bpp == 24)) { - raw_data_format_adjust_24bpp(bmp->datap, pic, width, height, - bytes_per_line_dest); + if ((depth == bmp->bpp) && (bmp->bpp%8 == 0)) { + raw_data_format_adjust(bmp->datap, pic, width, height, + (bmp->bpp/8)*width, bytes_per_line_dest); return 0; } return 1; diff --git a/src/bootsplash.c b/src/bootsplash.c index 165c98d..401c348 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -172,10 +172,13 @@ enable_bootsplash(void) dprintf(1, "bmp_decode failed with return code %d...\n", ret); goto done; } - bmp_get_size(bmp, &width, &height); - bpp_require = 24; + bmp_get_info(bmp, &width, &height, &bpp_require); } - /* jpeg would use 16 or 24 bpp video mode, BMP use 24bpp mode only */ + + /* jpeg would use 16 or 24 bpp video mode, BMP uses 8/16/24/32 bpp mode. + * 8bpp for BMP has corrupted colors, and lower than 8bpp fails to display + * or results in a loop. + */ // Try to find a graphics mode with the corresponding dimensions. int videomode = find_videomode(vesa_info, mode_info, width, height, @@ -192,7 +195,13 @@ enable_bootsplash(void) dprintf(3, "bytes per scanline: %d\n", mode_info->bytes_per_scanline); dprintf(3, "bits per pixel: %d\n", depth); - // Allocate space for image and decompress it. + // Allocate space for image and decompress it. + /* + * Has a weird issue with low bpp image files, imagesize is not + * consistent. Example: 8bpp images are correct, being essentially + * multiplied/divided by 1, but if you use 4bpp images, width is divided by + * 8, when it should be divided by 2. + */ int imagesize = height * mode_info->bytes_per_scanline; picture = malloc_tmphigh(imagesize); if (!picture) { diff --git a/src/util.h b/src/util.h index 6dd080f..9c06850 100644 --- a/src/util.h +++ b/src/util.h @@ -12,7 +12,7 @@ void handle_1553(struct bregs *regs); // bmp.c struct bmp_decdata *bmp_alloc(void); int bmp_decode(struct bmp_decdata *bmp, unsigned char *data, int data_size); -void bmp_get_size(struct bmp_decdata *bmp, int *width, int *height); +void bmp_get_info(struct bmp_decdata *bmp, int *width, int *height, int *bpp); int bmp_show(struct bmp_decdata *bmp, unsigned char *pic, int width , int height, int depth, int bytes_per_line_dest); -- 2.20.1

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Affordable SOIC8 SMT sockets for BIOS chips (15pcs / 36E + cheeap shipping)
by Ivan Ivanov 02 Feb '19

02 Feb '19

Just sharing our pleasant experience and nice find :) These SOIC8 SMT sockets for BIOS chips are too expensive at AliExpress (don't know why) - and to order them directly from Dediprog is economically inefficient because last time I checked they offered only overpriced express shipping - the cost of which is comparable to the price of sockets themselves! - But we are patient people and don't want to overpay that much for shipping regardless of its' speed. So we decided to order from this EU-based "The LAB eShop" : https://www.thelabeshop.com/en/Programmer-Emulators/SPI-Flash-Programmers/A… They are asking 36E (41US) for 15pcs sockets. Dediprog's price is 30US for 15pcs sockets, but "thanks" to their overpriced express shipping: "thelabeshop" prices are more affordable if you need just the sockets - they have an ordinary cheap post shipping method available with a tracking number, for 5 or 6. Although our first package has been lost, they kindly sent it again without any extra fees and this time it got delivered :) All 15 pcs sockets have these rectangular plastic caps and were reliably packet in a plastic ribbon to protect their fragile pins and for more convenience. If you need some photos we could share. What is also great about this "thelabeshop" is that, like aliexpress, they don't require you to use paypal (paypal adds unnecessary extra fees and has a horrible ethics / customer service). Payment could be done by a credit card. So if you need these rare SOIC8 sockets, "thelabeshop" price seems to be the most affordable. They also have SOIC16 sockets, although their expensive 58E price seems to be a mistake and maybe they could lower it for you if you would contact them - type "SOK-SPI-16W" at their search field if you are interested. And to find SOIC8, write "SOK-SPI-8W". These sockets could be very useful for routers or laptop motherboards, although you need a steady hand or ask professional to install them for you. Best regards, Ivan Ivanov

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[PATCH 0/2] Add menu item for activating TPM 2.0 PCR banks
by Stefan Berger 31 Jan '19

31 Jan '19

The following two patches add a menu item to the TPM 2.0 menu that allows a user to activate and deactivate the PCR banks the attached TPM 2.0 supports. This operation has to be done while in the firmware. Stefan v1->v2: - Refactor existing function for looking up the buffer size a hash needs to use a table instead; we extend the table then in patch 2 Stefan Berger (2): tcgbios: Use table to convert hash to buffer size tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks src/std/tcg.h | 18 ++++ src/tcgbios.c | 270 +++++++++++++++++++++++++++++++++++++++++++++++--- src/util.h | 2 + 3 files changed, 275 insertions(+), 15 deletions(-) -- 2.17.2

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[PATCH] build: Allow to use cross C preprocessor
by Roman Bolshakov 30 Jan '19

30 Jan '19

An attempt to cross-compile SeaBIOS on macOS can fail because host C preprocessor doesn't comprehend the command line options: Compiling IASL src/fw/acpi-dsdt.hex cpp -P -MD -MT src/fw/acpi-dsdt.hex src/fw/acpi-dsdt.dsl -o out/src/fw/acpi-dsdt.dsl.i.orig clang: error: no input files make: *** [src/fw/acpi-dsdt.hex] Error 1 Signed-off-by: Roman Bolshakov <r.bolshakov(a)yadro.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d2d11db..909c0a1 100644 --- a/Makefile +++ b/Makefile @@ -23,7 +23,7 @@ OBJCOPY=$(CROSS_PREFIX)objcopy OBJDUMP=$(CROSS_PREFIX)objdump STRIP=$(CROSS_PREFIX)strip PYTHON=python -CPP=cpp +CPP=$(CROSS_PREFIX)cpp IASL:=iasl LD32BIT_FLAG:=-melf_i386 -- 2.20.1

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Re: [SeaBIOS] [coreboot] Upgrade the 12 years old LZMA libraries - should we do it?
by Carl-Daniel Hailfinger 29 Jan '19

29 Jan '19

Hi Ivan, On 03.04.2018 20:03, Ivan Ivanov wrote: > I have noticed that both coreboot and seabios are using the very old > versions of LZMA SDK. True. I introduced the lzma code in coreboot (back when it was called LinuxBIOS) when we were working on OLPC XO-1 support. > If we will upgrade our LZMA libraries from the > outdated-by-12-years 4.42 to the current version 18.04 , speed and > compression ratio should improve and maybe a few bugs will be fixed. Do you have any numbers for this? An improved compression ratio and improved speed would be nice indeed, but how does the size of the decompression code change? If the decompression code grows more than the size reduction from better compression, it would be a net loss. A significantly reduced decompression speed would also be a problem. Decompression speed would have to be measured both for stream decompression (i.e. the decompressor gets the compressed data in single-byte or multibyte chunks) as well as full-size decompression (i.e. the decompressor can access all compressed data at once). We also have to make sure that stream decompression still works after the change. > Do you think it should be done, or you are OK with using such an > outdated version? A size benefit for the resulting image is a good reason to switch. Regards, Carl-Daniel

3 2

Mailing list update
by Kevin O'Connor 22 Jan '19

22 Jan '19

FYI, the SeaBIOS mailing list backend was recently updated (upgrade to Mailman3). Service should not be impacted, but if anyone does experience an issue then please let me know. Cheers, -Kevin

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[PATCH] tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks
by Stefan Berger 15 Jan '19

15 Jan '19

Implement a TPM 2.0 menu item that allows a user to toggle the activation of PCR banks of the TPM 2.0. After successful activation we shut down the TPM 2.0 and reset the machine. Signed-off-by: Stefan Berger <stefanb(a)linux.ibm.com> --- src/std/tcg.h | 18 ++++ src/tcgbios.c | 235 +++++++++++++++++++++++++++++++++++++++++++++++++- src/util.h | 2 + 3 files changed, 253 insertions(+), 2 deletions(-) diff --git a/src/std/tcg.h b/src/std/tcg.h index 09a92d8..eb9e67d 100644 --- a/src/std/tcg.h +++ b/src/std/tcg.h @@ -336,6 +336,12 @@ struct tpm_res_sha1complete { #define TPM2_ALG_SHA512 0x000d #define TPM2_ALG_SM3_256 0x0012 +#define TPM2_ALG_SHA1_FLAG (1 << 0) +#define TPM2_ALG_SHA256_FLAG (1 << 1) +#define TPM2_ALG_SHA384_FLAG (1 << 2) +#define TPM2_ALG_SHA512_FLAG (1 << 3) +#define TPM2_ALG_SM3_256_FLAG (1 << 4) + /* TPM 2 command tags */ #define TPM2_ST_NO_SESSIONS 0x8001 #define TPM2_ST_SESSIONS 0x8002 @@ -345,8 +351,10 @@ struct tpm_res_sha1complete { #define TPM2_CC_Clear 0x126 #define TPM2_CC_ClearControl 0x127 #define TPM2_CC_HierarchyChangeAuth 0x129 +#define TPM2_CC_PCR_Allocate 0x12b #define TPM2_CC_SelfTest 0x143 #define TPM2_CC_Startup 0x144 +#define TPM2_CC_Shutdown 0x145 #define TPM2_CC_StirRandom 0x146 #define TPM2_CC_GetCapability 0x17a #define TPM2_CC_GetRandom 0x17b @@ -442,6 +450,15 @@ struct tpm2_res_getcapability { u8 data[0]; /* capability dependent data */ } PACKED; +struct tpm2_req_pcr_allocate { + struct tpm_req_header hdr; + u32 authhandle; + u32 authblocksize; + struct tpm2_authblock authblock; + u32 count; + u8 tpms_pcr_selections[4]; +} PACKED; + struct tpms_pcr_selection { u16 hashAlg; u8 sizeOfSelect; @@ -550,5 +567,6 @@ struct pcctes_romex #define TPM_PPI_OP_CLEAR 5 #define TPM_PPI_OP_SET_OWNERINSTALL_TRUE 8 #define TPM_PPI_OP_SET_OWNERINSTALL_FALSE 9 +#define TPM_PPI_OP_SET_PCR_BANKS 23 #endif // tcg.h diff --git a/src/tcgbios.c b/src/tcgbios.c index 24846d3..ae0020e 100644 --- a/src/tcgbios.c +++ b/src/tcgbios.c @@ -180,6 +180,60 @@ tpm20_get_hash_buffersize(u16 hashAlg) } } +static u8 +tpm20_hashalg_to_flag(u16 hashAlg) +{ + switch (hashAlg) { + case TPM2_ALG_SHA1: + return TPM2_ALG_SHA1_FLAG; + case TPM2_ALG_SHA256: + return TPM2_ALG_SHA256_FLAG; + case TPM2_ALG_SHA384: + return TPM2_ALG_SHA384_FLAG; + case TPM2_ALG_SHA512: + return TPM2_ALG_SHA512_FLAG; + case TPM2_ALG_SM3_256: + return TPM2_ALG_SM3_256_FLAG; + default: + return 0; + } +} + +static u16 +tpm20_hashalg_flag_to_hashalg(u8 hashalg_flag) +{ + switch (hashalg_flag) { + case TPM2_ALG_SHA1_FLAG: + return TPM2_ALG_SHA1; + case TPM2_ALG_SHA256_FLAG: + return TPM2_ALG_SHA256; + case TPM2_ALG_SHA384_FLAG: + return TPM2_ALG_SHA384; + case TPM2_ALG_SHA512_FLAG: + return TPM2_ALG_SHA512; + case TPM2_ALG_SM3_256_FLAG: + return TPM2_ALG_SM3_256; + default: + return 0; + } +} + +static const char * +tpm20_hashalg_flag_to_name(u8 hashalg_flag) +{ + switch (hashalg_flag) { + case TPM2_ALG_SHA1_FLAG: + return "SHA1"; + case TPM2_ALG_SHA256_FLAG: + return "SHA256"; + case TPM2_ALG_SHA384_FLAG: + return "SHA384"; + case TPM2_ALG_SHA512_FLAG: + return "SHA512"; + } + return NULL; +} + // Add an entry at the start of the log describing digest formats static int tpm20_write_EfiSpecIdEventStruct(void) @@ -432,6 +486,104 @@ tpm20_get_pcrbanks(void) return ret; } +static int +tpm20_get_suppt_pcrbanks(u8 *suppt_pcrbanks, u8 *active_pcrbanks) +{ + *suppt_pcrbanks = 0; + *active_pcrbanks = 0; + + if (!tpm20_pcr_selection) + return -1; + + struct tpms_pcr_selection *sel = tpm20_pcr_selection->selections; + void *end = (void*)tpm20_pcr_selection + tpm20_pcr_selection_size; + + while (1) { + u8 sizeOfSelect = sel->sizeOfSelect; + void *nsel = (void*)sel + sizeof(*sel) + sizeOfSelect; + if (nsel > end) + return 0; + + u16 hashalg = be16_to_cpu(sel->hashAlg); + u8 hashalg_flag = tpm20_hashalg_to_flag(hashalg); + + *suppt_pcrbanks |= hashalg_flag; + + unsigned i; + for (i = 0; i < sizeOfSelect; i++) { + if (sel->pcrSelect[i]) { + *active_pcrbanks |= hashalg_flag; + break; + } + } + + sel = nsel; + } +} + +static int +tpm20_set_pcrbanks(u32 active_banks) +{ + struct tpm2_req_pcr_allocate trpa = { + .hdr.tag = cpu_to_be16(TPM2_ST_SESSIONS), + .hdr.ordinal = cpu_to_be32(TPM2_CC_PCR_Allocate), + .authhandle = cpu_to_be32(TPM2_RH_PLATFORM), + .authblocksize = cpu_to_be32(sizeof(trpa.authblock)), + .authblock = { + .handle = cpu_to_be32(TPM2_RS_PW), + .noncesize = cpu_to_be16(0), + .contsession = TPM2_YES, + .pwdsize = cpu_to_be16(0), + }, + }; + struct tpms_pcr_selection3 { + u16 hashAlg; + u8 sizeOfSelect; + u8 pcrSelect[3]; + } tps[ARRAY_SIZE(trpa.tpms_pcr_selections)]; + int i = 0; + u8 hashalg_flag = TPM2_ALG_SHA1_FLAG; + u8 dontcare, suppt_banks; + + tpm20_get_suppt_pcrbanks(&suppt_banks, &dontcare); + + while (hashalg_flag) { + if ((hashalg_flag & suppt_banks)) { + u16 hashalg = tpm20_hashalg_flag_to_hashalg(hashalg_flag); + + if (hashalg) { + u8 mask = 0; + tps[i].hashAlg = cpu_to_be16(hashalg); + tps[i].sizeOfSelect = 3; + + if (active_banks & hashalg_flag) + mask = 0xff; + + tps[i].pcrSelect[0] = mask; + tps[i].pcrSelect[1] = mask; + tps[i].pcrSelect[2] = mask; + i++; + } + } + hashalg_flag <<= 1; + } + + trpa.count = cpu_to_be32(i); + memcpy(trpa.tpms_pcr_selections, tps, i * sizeof(tps[0])); + trpa.hdr.totlen = cpu_to_be32(offsetof(struct tpm2_req_pcr_allocate, + tpms_pcr_selections) + + i * sizeof(tps[0])); + + struct tpm_rsp_header rsp; + u32 resp_length = sizeof(rsp); + + int ret = tpmhw_transmit(0, &trpa.hdr, &rsp, &resp_length, + TPM_DURATION_TYPE_SHORT); + ret = ret ? -1 : be32_to_cpu(rsp.errcode); + + return ret; +} + static int tpm12_get_capability(u32 cap, u32 subcap, struct tpm_rsp_header *rsp, u32 rsize) { @@ -1752,7 +1904,7 @@ tpm20_clear(void) } static int -tpm20_process_cfg(tpm_ppi_code msgCode, int verbose) +tpm20_process_cfg(tpm_ppi_code msgCode, u32 pprm, int verbose) { int ret = 0; @@ -1765,6 +1917,13 @@ tpm20_process_cfg(tpm_ppi_code msgCode, int verbose) if (!ret) ret = tpm20_clear(); break; + + case TPM_PPI_OP_SET_PCR_BANKS: + ret = tpm20_set_pcrbanks(pprm); + if (!ret) + ret = tpm_simple_cmd(0, TPM2_CC_Shutdown, + 2, TPM2_SU_CLEAR, TPM_DURATION_TYPE_SHORT); + break; } if (ret) @@ -1947,14 +2106,77 @@ tpm12_menu(void) } } +static int +tpm20_menu_change_active_pcrbanks(u8 *activate_banks) +{ + u8 active_banks, suppt_banks; + + tpm20_get_suppt_pcrbanks(&suppt_banks, &active_banks); + + *activate_banks = active_banks; + + while (1) { + u8 hashalg_flag = TPM2_ALG_SHA1_FLAG; + u8 i = 0; + + printf("\nToggle active PCR banks by pressing number key\n\n"); + + while (hashalg_flag) { + u8 flag = hashalg_flag & suppt_banks; + const char *hashname = tpm20_hashalg_flag_to_name(flag); + + i++; + if (hashname) { + printf(" %d: %s", i, hashname); + if (*activate_banks & hashalg_flag) + printf(" (enabled)"); + printf("\n"); + } + + hashalg_flag <<= 1; + } + printf("\n" + "ESC: return to previous menu without changing active PCR banks\n" + "A : activate selection\n"); + u8 flagnum; + int show = 0; + while (!show) { + int scancode = get_keystroke(1000); + + switch (scancode) { + case ~0: + continue; + case 1: /* ESC */ + printf("\n"); + return -1; + case 2 ... 6: /* keys 1 .. 5 */ + flagnum = scancode - 1; + if (flagnum > i) + continue; + if (suppt_banks & (1 << (flagnum - 1))) { + *activate_banks ^= 1 << (flagnum - 1); + show = 1; + } + break; + case SCANCODE_A: + return 0; + } + } + } +} + static void tpm20_menu(void) { int scan_code; tpm_ppi_code msgCode; + u32 pprm; + u8 active_banks; + int do_reset = 0; for (;;) { printf("1. Clear TPM\n"); + printf("2. Change active PCR banks\n"); printf("\nIf no change is desired or if this menu was reached by " "mistake, press ESC to\n" @@ -1973,11 +2195,20 @@ tpm20_menu(void) case 2: msgCode = TPM_PPI_OP_CLEAR; break; + case 3: + if (tpm20_menu_change_active_pcrbanks(&active_banks) < 0) + continue; + msgCode = TPM_PPI_OP_SET_PCR_BANKS; + pprm = active_banks; + do_reset = 1; + break; default: continue; } - tpm20_process_cfg(msgCode, 0); + tpm20_process_cfg(msgCode, pprm, 0); + if (do_reset) + reset(); } } diff --git a/src/util.h b/src/util.h index 6dd080f..b7169dd 100644 --- a/src/util.h +++ b/src/util.h @@ -38,6 +38,8 @@ struct usbdevice_s; int bootprio_find_usb(struct usbdevice_s *usbdev, int lun); int get_keystroke(int msec); +#define SCANCODE_A 0x1e + // bootsplash.c void enable_vga_console(void); void enable_bootsplash(void); -- 2.17.2

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USB-to-SATA bridge conflicts with USB boot flash drive
by Аладышев Константин 24 Dec '18

24 Dec '18

Hello! I use coreboot+SeaBIOS bundle on custom motherboard with Intel Haswell i7 and Lynxpoint-LP chipset and I've come to a strange issue with USB-to-SATA bridge TUSB9261 (http://www.ti.com/product/TUSB9261). In my experiments I plug HDD to one USB port, and USB boot flash drive to another USB port. Everything works fine when HDD is present on USB-to-SATA bridge. SeaBIOS displays both devices in its boot menu. But if HDD is not present and if USB boot flash drive is plugged to a port greater than USB-to-SATA bridge port, SeaBIOS doesn't see flash drive as bootable device. In this case I see in log messages similar to this: """ Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@7/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@7 ehci_send_pipe qh=0x000eab80 dir=0 data=0x00006b79 size=31 ehci_send_pipe qh=0x000eab00 dir=128 data=0x00006c98 size=36 WARNING - Timeout at ehci_wait_td:516! ehci pipe=0x000eab00 cur=000069c0 tok=80240d80 next=1 td=0x000069c0 status=240d80 USB transmission failed Unable to configure USB MSC drive. phys_free f4950 (detail=0x7f6c13c0) Unable to configure USB MSC device. """ Summarizing all the above with SeaBIOS logs: SeaBIOS displays flash drive correctly as bootable device when: - HDD is present on SATA-to-USB port (https://pastebin.com/SuKBkQrq) - HDD is not present on USB port, but SATA-to-USB port number is greater than USB flash drive number (https://pastebin.com/9f6RTBHB) SeaBIOS doesn't display flash drive as bootable device when: - HDD is not present on USB port and SATA-to-USB port number is less than USB flash drive number (https://pastebin.com/abBPhej0) What can be the source of the problem and what can I do to solve this issue? Best Regards, Aladyshev Konstantin

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Re: [SeaBIOS] [PATCH v2] ramdisk: search for all available floppy images instead of one
by Kevin O'Connor 19 Dec '18

19 Dec '18

On Thu, Dec 06, 2018 at 07:12:19PM +0300, Mike Banon wrote: > Hi Kevin, thank you very much for the suggestions! This is a second > version of my "more_than_one_floppy" patch : now it will search for > the max size of floppy stored inside CBFS, then allocate this size of > RAM and use it later for any floppy selected by user. sha256 = > 2f8bb18c1606d437de49e585769f100c085234de29d8520e2dc74d25b7f7645a Thanks, see my comments below. [...] > --- > diff --git a/src/block.h b/src/block.h > index f64e880..aaa236f 100644 > --- a/src/block.h > +++ b/src/block.h > @@ -2,7 +2,7 @@ > #define __BLOCK_H > > #include "types.h" // u32 > - > +#include "romfile.h" // struct romfile_s > > /**************************************************************** > * Disk command request > @@ -48,6 +48,7 @@ struct drive_s { > struct drive_s { > u8 type; // Driver type (DTYPE_*) > u8 floppy_type; // Type of floppy (only for floppy drives). > + struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). > struct chs_s lchs; // Logical CHS > u64 sectors; // Total sectors count > u32 cntl_id; // Unique id for a given driver type. Driver specific fields should not be added to drive_s - the code should use the container_of() trick to allocate driver specific fields. (Create and allocate a custom driver struct that contains a 'struct drive_s' and when called with a drive_s use container_of() to get a pointer back to that main struct - for an example, take a look at what src/hw/usb-msc.c does.) > diff --git a/src/boot.c b/src/boot.c > index 9f82f3c..79f1e7d 100644 > --- a/src/boot.c > +++ b/src/boot.c > @@ -584,7 +584,7 @@ bcv_prepboot(void) > break; > case IPL_TYPE_FLOPPY: > map_floppy_drive(pos->drive); > - add_bev(IPL_TYPE_FLOPPY, 0); > + add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); > break; > case IPL_TYPE_HARDDISK: > map_hd_drive(pos->drive); > @@ -733,6 +733,12 @@ do_boot(int seq_nr) > static void > do_boot(int seq_nr) > { > + > + int ret; > + void *pos; > + struct romfile_s *file; > + struct drive_s *drive; > + > if (! CONFIG_BOOT) > panic("Boot support not compiled in.\n"); > > @@ -744,6 +750,16 @@ do_boot(int seq_nr) > switch (ie->type) { > case IPL_TYPE_FLOPPY: > printf("Booting from Floppy...\n"); > + drive = (struct drive_s *)ie->vector; > + file = drive->floppy_file; > + // File is NULL if a floppy is physical. > + if (file) { > + // Copy virtual floppy image into ram. > + pos = (void *)drive->cntl_id; > + ret = file->copy(file, pos, file->size); > + if (ret < 0) > + break; > + } Similarly, we shouldn't add driver specific code into the boot phase. A better place to do this would be during the BCV mapping phase (eg, bcv_prepboot() ). The idea is to do the work after the boot menu, but before the boot phase. Ideally the code would detect the driver wants a callback and then call driver specific code that resides in src/hw/ramdisk.c. -Kevin

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[PATCH] shadow: set code segment to high rom region when enabling RAM
by Evgeny Yakovlev 18 Dec '18

18 Dec '18

Currently make_bios_writable_intel will call __make_bios_writeable_intel from high rom memory by manually correcting its offset to make sure that we safely execute it while overriding memory mapping through PAMs However we still may call code from low memory, when __make_bios_writeable_intel itself calls other code without manual pointer adjustments. Right now it calls pci_config_readl and pci_config_writel. Consider this scenario: 0. Linker puts pci_config_writel in F-segment. 1. first pci_config_writel is called to reprogram PAM0-3, which means remap regions 0xF0000-0xFFFFF and 0xD0000 - 0xC7FFF. 2. second pci_config_writel is called to reprogram PAM4-7 but code in F-segment is no longer valid, including pci_config_writel. However we don't crash due to instruction cache being hot between two calls. Adding manual i-cache flush (by reloading the same CS segment for example) between two calls finally crashes the firmware. This change wraps a call to __make_bios_writable_bios by setting code segment at base 0xFFF00000. This way simple nested function calls work as long as no data fetches happen during execution through CS segment (i.e. something like dprintf is still not safe to call). Signed-off-by: Evgeny Yakovlev <wrfsh(a)yandex-team.ru> --- src/config.h | 16 ++++++++++------ src/fw/shadow.c | 37 ++++++++++++++++++++++++++++--------- src/misc.c | 8 ++++++++ 3 files changed, 46 insertions(+), 15 deletions(-) diff --git a/src/config.h b/src/config.h index 93c8dbc..87c4118 100644 --- a/src/config.h +++ b/src/config.h @@ -60,13 +60,17 @@ #define SEG_BDA 0x0040 #define SEG_BIOS 0xf000 +// On the emulators, the bios at 0xf0000 is also at 0xffff0000 +#define BIOS_SRC_OFFSET 0xfff00000 + // Segment definitions in protected mode (see rombios32_gdt in misc.c) -#define SEG32_MODE32_CS (1 << 3) -#define SEG32_MODE32_DS (2 << 3) -#define SEG32_MODE16_CS (3 << 3) -#define SEG32_MODE16_DS (4 << 3) -#define SEG32_MODE16BIG_CS (5 << 3) -#define SEG32_MODE16BIG_DS (6 << 3) +#define SEG32_MODE32_CS (1 << 3) +#define SEG32_MODE32_DS (2 << 3) +#define SEG32_MODE16_CS (3 << 3) +#define SEG32_MODE16_DS (4 << 3) +#define SEG32_MODE16BIG_CS (5 << 3) +#define SEG32_MODE16BIG_DS (6 << 3) +#define SEG32_MODE32_HIGH_CS (7 << 3) // Debugging levels. If non-zero and CONFIG_DEBUG_LEVEL is greater // than the specified value, then the corresponding irq handler will diff --git a/src/fw/shadow.c b/src/fw/shadow.c index 4c627a8..80d0889 100644 --- a/src/fw/shadow.c +++ b/src/fw/shadow.c @@ -18,9 +18,6 @@ #include "util.h" // make_bios_writable #include "x86.h" // wbinvd -// On the emulators, the bios at 0xf0000 is also at 0xffff0000 -#define BIOS_SRC_OFFSET 0xfff00000 - union pamdata_u { u8 data8[8]; u32 data32[2]; @@ -56,6 +53,30 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) , SYMBOL(code32flat_end) - SYMBOL(code32flat_start)); } +// A wrapper for executing __make_bios_writable_intel in high memory code segment +static void +__make_bios_writable_intel_highmem(u16 bdf, u32 pam0) +{ + // Save whatever CS segment we've had before entering here + // and switch to highmem code + u16 prev_cs; + __asm__ __volatile__ ("mov %%cs, %0":"=rm"(prev_cs)); + __asm__ __volatile__ ("ljmp %0, $__make_bios_writable_intel_highmem__enter\n" + "__make_bios_writable_intel_highmem__enter:\n" + : + : "n"(SEG32_MODE32_HIGH_CS)); + + __make_bios_writable_intel(bdf, pam0); + + // Far jump to return to previous segment + __asm__ __volatile__ ("push %0\n" + "push $__make_bios_writable_intel_highmem__exit\n" + "retf\n" + "__make_bios_writable_intel_highmem__exit:\n" + : + : "rm"((u32)prev_cs)); +} + static void make_bios_writable_intel(u16 bdf, u32 pam0) { @@ -65,13 +86,11 @@ make_bios_writable_intel(u16 bdf, u32 pam0) // if ram isn't backing the bios segment when shadowing is // disabled, the code itself won't be in memory. So, run the // code from the high-memory flash location. - u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET; - void (*func)(u16 bdf, u32 pam0) = (void*)pos; - func(bdf, pam0); - return; + __make_bios_writable_intel_highmem(bdf, pam0); + } else { + // Ram already present - just enable writes + __make_bios_writable_intel(bdf, pam0); } - // Ram already present - just enable writes - __make_bios_writable_intel(bdf, pam0); } static void diff --git a/src/misc.c b/src/misc.c index b511730..cb931a5 100644 --- a/src/misc.c +++ b/src/misc.c @@ -160,6 +160,14 @@ u64 rombios32_gdt[] VARFSEG __aligned(8) = { GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR), // 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS) GDT_GRANLIMIT(0xffffffff) | GDT_DATA, + + // + // Following segments are used when enabling shadow memory + // where we need to execute code strictly from base 0xFFF00000 + // + + // 32 bit code segment in high memory + GDT_GRANLIMIT(0xfffff) | GDT_CODE | GDT_B | GDT_BASE(BIOS_SRC_OFFSET), }; // GDT descriptor -- 2.7.4

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