SeaBIOS

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3799 discussions

Re: [SeaBIOS] [PATCH 2/2] seabios: pciinit: fix overflow when bar allocation.
by Kevin O'Connor 27 Jul '10

27 Jul '10

On Mon, Jul 26, 2010 at 02:02:46PM +0900, Isaku Yamahata wrote: > When allocating bar, overflow can occur. > So add overflow check and don't allocate bar if overflowed. > Overflow check is ugly, but necessary. > Another suggested way is to change related variables u64 from u32 > thus overflow can't occur because the related value are all u32 addressable. > Anyway even with u64, it is necessary to the resulted value > max_u32. I wonder if we could create malloc zones for this and then use pmm_alloc. The pmm_alloc function already handles overflow and alignments. One difficulty, though, is that pmm_alloc doesn't guarentee linear allocations, and it looks like pci_bios_init_device_bridge assumes this. -Kevin

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[PATCH] Fix bug causing truncation of files in cbfs_copyfile().
by Kevin O'Connor 27 Jul '10

27 Jul '10

Fix bug causing truncation of uncompressed files that had a size not a multiple of 4. Make sure to allocate extra space for jpeg temp location in bootsplash code. --- src/bootsplash.c | 2 +- src/coreboot.c | 6 +++--- src/util.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/bootsplash.c b/src/bootsplash.c index ed10415..9dcdd99 100644 --- a/src/bootsplash.c +++ b/src/bootsplash.c @@ -119,7 +119,7 @@ void enable_vga_console(void) struct cbfs_file *file = cbfs_finddatafile("bootsplash.jpg"); if (!file) goto gotext; - int filesize = cbfs_datasize(file); + int filesize = ALIGN(cbfs_datasize(file), 4); int imagesize = (CONFIG_BOOTSPLASH_X * CONFIG_BOOTSPLASH_Y * (CONFIG_BOOTSPLASH_DEPTH / 8)); diff --git a/src/coreboot.c b/src/coreboot.c index 5d9a101..207c4a4 100644 --- a/src/coreboot.c +++ b/src/coreboot.c @@ -507,10 +507,10 @@ cbfs_copyfile(struct cbfs_file *file, void *dst, u32 maxlen) return -1; u32 size = ntohl(file->len); + u32 asize = ALIGN(size, 4); void *src = (void*)file + ntohl(file->offset); if (cbfs_iscomp(file)) { // Compressed - copy to temp ram and uncompress it. - u32 asize = ALIGN(size, 4); void *temp = malloc_tmphigh(asize); if (!temp) return -1; @@ -523,11 +523,11 @@ cbfs_copyfile(struct cbfs_file *file, void *dst, u32 maxlen) // Not compressed. dprintf(3, "Copying data %d@%p to %d@%p\n", size, src, maxlen, dst); - if (size > maxlen) { + if (asize > maxlen) { warn_noalloc(); return -1; } - iomemcpy(dst, src, size); + iomemcpy(dst, src, asize); return size; } diff --git a/src/util.c b/src/util.c index 2c22dfc..d99bf06 100644 --- a/src/util.c +++ b/src/util.c @@ -202,7 +202,7 @@ memcpy(void *d1, const void *s1, size_t len) return d1; } -// Copy from memory mapped IO. IO mem is very slow, so yield +// Copy to/from memory mapped IO. IO mem is very slow, so yield // periodically. 'len' must be 4 byte aligned. void iomemcpy(void *d, const void *s, u32 len) -- 1.7.1.1

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[PATCH 0/6] Bootsplash cleanups and enhancements
by Kevin O'Connor 27 Jul '10

27 Jul '10

This patch series fixes some bugs in the bootsplash code, and adds some cleanups. It is in preparation for turning bootsplash on by default. Kevin O'Connor (6): Bootsplash fixes and cleanups. Check that malloc succeeds in bootsplash code. Don't do "double buffering" in bootsplash code. Add call16_int10 helper to bootsplash.c. Be sure to disable bootsplash on all BIOS boot cases. Cleanup bootsplash vesa signature detection. src/biosvar.h | 3 +- src/boot.c | 8 +- src/bootsplash.c | 210 ++++++++++++++++++++++-------------------------------- src/post.c | 8 ++- src/util.h | 5 +- 5 files changed, 101 insertions(+), 133 deletions(-)

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Re: [SeaBIOS] [PATCH 1/2] seabios: pciinit: fix 64bit bar initilization.
by Kevin O'Connor 27 Jul '10

27 Jul '10

On Mon, Jul 26, 2010 at 02:02:45PM +0900, Isaku Yamahata wrote: > When 64bit bar allocation failed, leave it untouched as 32bit bar case. > There is no point to set higher bit to all 1, it is just leftover from > debug code. Thanks. -Kevin

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[PATCH 0/2] seabios: pciinit: fix bar allocation
by Isaku Yamahata 26 Jul '10

26 Jul '10

This patch set fixes pci bar allocation. Cam Macdonell reported that there was something wrong with 64bit/32bit 512M BAR. This addresses his report. Isaku Yamahata (2): seabios: pciinit: fix 64bit bar initilization. seabios: pciinit: fix overflow when bar allocation. src/pciinit.c | 56 ++++++++++++++++++++++++++++++++++++-------------------- 1 files changed, 36 insertions(+), 20 deletions(-)

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Re: [SeaBIOS] [RFC PATCH v3 0/3] Add segment limit checks to emulator
by Kevin O'Connor 25 Jul '10

25 Jul '10

On Sat, Jul 24, 2010 at 11:45:22AM -0400, Kevin O'Connor wrote: > On Mon, Jul 12, 2010 at 04:13:06PM +0300, Avi Kivity wrote: > > Does SeaBIOS use big real mode now? > > SeaBIOS calls option roms in big real mode. This is required by the > relevant specs. > > See the transition16big function in src/romlayout.S. It briefly jumps > to an address at 0xffxxx during the transition to real-mode. At a > quick glance, it looks like it could probably be changed to not use a > code address >64K. I put together a SeaBIOS patch so it does not use code addresses >64K in big real mode - in case anyone wants to test it. Note, this only reduces the use of code addresses >64K - SeaBIOS will still try to use data addresses >64K (eg, in option rom PMM code). -Kevin diff --git a/src/misc.c b/src/misc.c index 354df87..108c332 100644 --- a/src/misc.c +++ b/src/misc.c @@ -156,8 +156,8 @@ u64 rombios32_gdt[] VAR16VISIBLE __aligned(8) = { GDT_LIMIT(BUILD_BIOS_SIZE-1) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR), // 16 bit data segment base=0x0 limit=0xffff (SEG32_MODE16_DS) GDT_LIMIT(0x0ffff) | GDT_DATA, - // 16 bit code segment base=0 limit=0xffffffff (SEG32_MODE16BIG_CS) - GDT_LIMIT(0xfffff) | GDT_CODE | GDT_G, + // 16 bit code segment base=0xf0000 limit=0xffffffff (SEG32_MODE16BIG_CS) + GDT_LIMIT(0xfffff) | GDT_CODE | GDT_G | GDT_BASE(BUILD_BIOS_ADDR), // 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS) GDT_LIMIT(0xfffff) | GDT_DATA | GDT_G, }; diff --git a/src/romlayout.S b/src/romlayout.S index 54e5a4d..a469596 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -105,7 +105,7 @@ transition16big: movw %ax, %fs movw %ax, %gs - ljmpl $SEG32_MODE16BIG_CS, $(BUILD_BIOS_ADDR + 1f) + ljmpw $SEG32_MODE16BIG_CS, $1f .code16gcc 1:

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[PATCH v2 0/2] abstract shadow and smm opreration.
by Isaku Yamahata 24 Jul '10

24 Jul '10

This is on top of the patch series of PATCH v2 "abstract chipset(i440fx) specific register operation." Patch descriontion: This patch set abstract out shadow and smm operation which are specific to chipset. and spit out i440fx specific part into dev-i440fx.c. Thus q35 specific register value/operation will be added easily. Changes v1 -> v2: - separated non-arguable part to make the merge easy. - factor out intel specific shadow memory operation. - factor out smm operation. - abstract at device level, not register level. Isaku Yamahata (2): seabios: shadow: make device finding more generic. seabios: smm: move out piix4 specific smram logic to dev-i440fx.c src/dev-i440fx.c | 44 ++++++++++++++++++++++ src/dev-i440fx.h | 3 ++ src/shadow.c | 106 +++++++++++++++++++++++++++++++++--------------------- src/smm.c | 58 +++++++++++++----------------- src/util.h | 6 +++ 5 files changed, 143 insertions(+), 74 deletions(-)

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Impossible to distinguish between two '/' keys
by Christopher Gautier 23 Jul '10

23 Jul '10

Hello, On a French keyboard, the '/' can be obtained by shifting the ':/' key (scancode 0x34), or using the '/' keypad key which is the extended '0xe0+0x35'. However, calling the 0x16 interrupt while pressing the keypad '/' does not return an extended key: it returns 0x35 which maps to '!§'. This means it is impossible to implement a correct key mapping for both '/' keys, and '!'. It seems to me that the problem is due to the following test in the __processkey() function (kbd.c, seabios 0.5.1 and git repository): if (flags2 & KF2_LAST_E0 && scancode >= 0x47 && scancode <= 0x53) { /* extended keys handling */ ... } which disregards the case scancode = 0x35. Changing the 0x47 boundary value fixes the problem. Could somebody validate this micro patch? -- k

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[PATCH 0/5] abstract chipset(i440fx) specific register operation.(Part I)
by Isaku Yamahata 20 Jul '10

20 Jul '10

Changes v2 -> v1: - dropped patches which are under discussion to make the merge easy. The updated one on top of this patch series will be posted as Part II. - moved cpu_to_le{16, 32}() to util.h Patch descriontion: This patch set abstract out chipset specific operation, and spit out i440fx specific operation into dev-i440fx.c with it. Thus q35 specific register value/operation will be added easily. Isaku Yamahata (5): seabios: pci: introduce helper function to find device from table and initialize it. seabios: acpi: move out endian conversion helper function. seabios: acpi: move acpi definitions to acpi.h from acpi.c seabios: acpi: split out piix4 pm logic. seabios: acpi: clean up of finding pm device. src/acpi.c | 107 +++++++++--------------------------------------------- src/acpi.h | 76 ++++++++++++++++++++++++++++++++++++++ src/dev-i440fx.c | 15 ++++++++ src/dev-i440fx.h | 1 + src/pci.c | 12 ++++++ src/pci.h | 1 + src/util.h | 10 +++++ 7 files changed, 133 insertions(+), 89 deletions(-)

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Re: [SeaBIOS] [PATCH 2/7] seabios: shadow: make device finding more generic.
by Kevin O'Connor 20 Jul '10

20 Jul '10

On Mon, Jul 12, 2010 at 08:47:47PM +0900, Isaku Yamahata wrote: > pam register offset is north bridge specific. > So determine the offset based on found north bridge. Is it really just the offset that is north bridge specific? I thought the entire process was very north bridge specific. If so, I don't think it makes sense to pass back the pam0 register - instead the north bridge specific code should do the necessary work (using helper functions if possible). I have the same concern with part 3 and 4 of this series. -Kevin

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