SeaBIOS

seabios@seabios.org

2 participants
3799 discussions

[PATCH] fix virtio-blk failure after reboot
by Gleb Natapov 13 Nov '10

13 Nov '10

vring_virtqueue should be zeroed otherwise old values will be reused after reboot. Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/src/virtio-blk.c b/src/virtio-blk.c index 34d7863..7a25826 100644 --- a/src/virtio-blk.c +++ b/src/virtio-blk.c @@ -109,6 +109,7 @@ init_virtio_blk(u16 bdf) goto fail; } memset(vdrive_g, 0, sizeof(*vdrive_g)); + memset(vq, 0, sizeof(*vq)); vdrive_g->drive.type = DTYPE_VIRTIO; vdrive_g->drive.cntl_id = bdf; vdrive_g->vq = vq; -- Gleb.

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Re: [SeaBIOS] [PATCH] [Seabios] Over 4GB address ranges for 64bit PCI BARs
by Alexey Korolev 08 Nov '10

08 Nov '10

Hi, > Hi. > The current BAR allocation doesn't check overflow and some patches > are floating around which aren't merged yet. > There are several issues. > > - overflow check > This should be fixed. > Some patches are proposed. None hasn't been merged yet. > Your patch also addresses this issue. > http://www.seabios.org/pipermail/seabios/2010-July/000794.html > http://www.seabios.org/pipermail/seabios/2010-October/001089.html Right. It would be great if the fix get included in seabios/qemu. Update: I've seen today's message from Kevin. He is going to merge your patch. So it will be good news for us. > - >4GB 64bit bar allocation > Your patche tries to address this issue. But it breaks PCI-to-PCI > bridge filtering support. Hmm, it is quite possible, as we don't know a lot about seabios PCI-to-PCI bridge filtering support. Just out of curiosity: what is the issue? > If the BAR size is huge (or there are too many BARs), the bar can't > be allocated under 4G. So several persons want seabios to allocate > such BARs at >4GB area complaining that OS can't use BARs that seabios > didn't assigned. > > Others think such BAR can be left unallocated. > Seabios role is to setup minimal basic environment for bootloader > to boot OS, 64bit bar allocation is beyond it's role. > bootloader/rombios usually doesn't handle BARs that is allocated > beyond 4GB, and Modern OSes can re-arrange PCI bar allocation itself. > So 64bit bar allocation support wouldn't be needed. > > I'm not sure if there is enough demand to support 64bit BAR allocation > and if Kevin will accept it or not. Consensus is needed. > What OS are you using? > For us >4GB allocation is welcome but not critical, because we mainly use Linux versions 2.6.18 and newer. We've tested the seabios without assignment of the regions which do not fit in first 32bit and it appears to work fine. So for us 64bit bar allocation support wouldn't be needed. It is possible that people will use an ancient version of Linux, but the probability of this event is very low. Thanks, Alexey

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FWD:[PATCH] [Seabios] Over 4GB address ranges for 64bit PCI BARs
by Isaku Yamahata 06 Nov '10

06 Nov '10

FWD ----- Forwarded message from Isaku Yamahata <yamahata(a)valinux.co.jp> ----- Subject: Re: [PATCH] [Seabios] Over 4GB address ranges for 64bit PCI BARs User-Agent: Mutt/1.5.19 (2009-01-05) Hi. The current BAR allocation doesn't check overflow and some patches are floating around which aren't merged yet. There are several issues. - overflow check This should be fixed. Some patches are proposed. None hasn't been merged yet. Your patch also addresses this issue. http://www.seabios.org/pipermail/seabios/2010-July/000794.html http://www.seabios.org/pipermail/seabios/2010-October/001089.html - abstraction of pci bar allocation This is very coding detail. This should be addressed. The current PCI BAR allocation uses primitives. So overflow check becomes ugly. So it would desirable to abstract it. Kevin suggested to use the existing PMM framework. But I concluded PMM doesn't suit for it, so introduced new api. But I haven't got any feedback from him yet. - >4GB 64bit bar allocation Your patche tries to address this issue. But it breaks PCI-to-PCI bridge filtering support. If the BAR size is huge (or there are too many BARs), the bar can't be allocated under 4G. So several persons want seabios to allocate such BARs at >4GB area complaining that OS can't use BARs that seabios didn't assigned. Others think such BAR can be left unallocated. Seabios role is to setup minimal basic environment for bootloader to boot OS, 64bit bar allocation is beyond it's role. bootloader/rombios usually doesn't handle BARs that is allocated beyond 4GB, and Modern OSes can re-arrange PCI bar allocation itself. So 64bit bar allocation support wouldn't be needed. I'm not sure if there is enough demand to support 64bit BAR allocation and if Kevin will accept it or not. Consensus is needed. What OS are you using? - bridge filtering 64bit BAR allocation must be aware of PCI-to-PCI bridge filtering. I suppose one more pci bus walk (or two) would be necessary. i.e. make pci bar allocation two (or three) pass. thanks, On Fri, Nov 05, 2010 at 03:13:38PM +1300, Alexey Korolev wrote: > Hi, > > We have seen some issues with 64bit PCI address and large BAR region support in > seabios. > > On attempting to register a 64bit BAR of 1GB size we had some strange failures > in qemu. After some debugging we find out that source of the issue was in > seabios PCI enumeration code. > > The issue takes place because of u32 overflow in pciinit.c. > …......... > if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) { > dprintf(1, > "prefmem region of (bdf 0x%x bar %d) can't be mapped. " > "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n", > bdf, region_num, BUILD_PCIPREFMEM_SIZE); > size = 0; > } > …........... > if (size > 0) { > *paddr = ALIGN(*paddr, size); > pci_set_io_region_addr(bdf, region_num, *paddr); > *paddr += size; > } > > If size is greater than 0xFFFFFFFF ??? BUILD_PCIPREFMEM_START (256MB), > this call ALIGN(*paddr, size) will always return 0. The protection test fails, size remains > 0, and guest memory mapping will be corrupted. > > We have found that a very similar problem was discussed previously: > > http://www.mail-archive.com/qemu-devel@nongnu.org/msg38090.html > > The discussion also touches on the question of 64bit addressing for PCI BARs. > In the current implementation regardless of whether the PCI BAR type is 64bit or not > the addressable range will be limited to the first 4GB. We also want to have "true" 64bit > addressable range for PCI BARs. > > So to solve these issues some changes were made. > Tracking for overflows has been added as well as support for 64bit range. > To support the full 64bit address range a pci_bios_64bit_addr variable has been added. > The 64bit range can be used only if BAR has PCI_BASE_ADDRESS_MEM_TYPE_64 > attribute and the given region doesn't fit in first 4GB. The patch has been > tested on Linux and BSD guest OS's and it appears to work fine. > > > > Signed-off-by Alexey Korolev <Alexey.Korolev(a)endace.com> > Signed-off-by Stephen Donelly <Stephen.Donelly(a)endace.com> > --- > pciinit.c | 83 ++++++++++++++++++++++++++++++++------------------------------ > 1 file changed, 43 insertions(+), 40 deletions(-) > > diff --git a/src/pciinit.c b/src/pciinit.c > index 0346423..86c8137 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -20,6 +20,7 @@ static void pci_bios_init_device_in_bus(int bus); > static u32 pci_bios_io_addr; > static u32 pci_bios_mem_addr; > static u32 pci_bios_prefmem_addr; > +static u64 pci_bios_64bit_addr; > /* host irqs corresponding to PCI irqs A-D */ > const u8 pci_irqs[4] = { > 10, 10, 11, 11 > @@ -56,9 +57,11 @@ static int pci_bios_allocate_region(u16 bdf, int region_num) > { > u32 *paddr; > u32 ofs = pci_bar(bdf, region_num); > - > u32 old = pci_config_readl(bdf, ofs); > u32 mask; > + u32 limit_addr; > + int is_64bit; > + > if (region_num == PCI_ROM_SLOT) { > mask = PCI_ROM_ADDRESS_MASK; > pci_config_writel(bdf, ofs, mask); > @@ -73,50 +76,49 @@ static int pci_bios_allocate_region(u16 bdf, int region_num) > pci_config_writel(bdf, ofs, old); > > u32 size = (~(val & mask)) + 1; > - if (val != 0) { > - if (val & PCI_BASE_ADDRESS_SPACE_IO) { > - paddr = &pci_bios_io_addr; > - if (ALIGN(*paddr, size) + size >= 64 * 1024) { > - dprintf(1, > - "io region of (bdf 0x%x bar %d) can't be mapped.\n", > - bdf, region_num); > - size = 0; > - } > - } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) && > - /* keep behaviour on bus = 0 */ > - pci_bdf_to_bus(bdf) != 0 && > - /* If pci_bios_prefmem_addr == 0, keep old behaviour */ > - pci_bios_prefmem_addr != 0) { > - paddr = &pci_bios_prefmem_addr; > - if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) { > - dprintf(1, > - "prefmem region of (bdf 0x%x bar %d) can't be mapped. " > - "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n", > - bdf, region_num, BUILD_PCIPREFMEM_SIZE); > - size = 0; > - } > - } else { > - paddr = &pci_bios_mem_addr; > - if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) { > + if (!val || !size) > + return 0; > + > + is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) && > + (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64; > + > + if (val & PCI_BASE_ADDRESS_SPACE_IO) { > + paddr = &pci_bios_io_addr; > + limit_addr = 64 * 1024; > + } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) && > + /* keep behaviour on bus = 0 */ > + pci_bdf_to_bus(bdf) != 0 && > + /* If pci_bios_prefmem_addr == 0, keep old behaviour */ > + pci_bios_prefmem_addr != 0) { > + paddr = &pci_bios_prefmem_addr; > + limit_addr = BUILD_PCIPREFMEM_END; > + } else { > + paddr = &pci_bios_mem_addr; > + limit_addr = BUILD_PCIMEM_END; > + } > + > + /* The region is out of allowed 32bit mapping range */ > + if ((ALIGN(*paddr, size) + size >= limit_addr) || > + (ALIGN(*paddr, size) + size <= *paddr)) { > + if (!is_64bit) { > dprintf(1, > "mem region of (bdf 0x%x bar %d) can't be mapped. " > - "increase BUILD_PCIMEM_SIZE and recompile. size %x\n", > - bdf, region_num, BUILD_PCIMEM_SIZE); > - size = 0; > + "Region size %x\n", bdf, region_num, size); > + return 0; > } > - } > - if (size > 0) { > - *paddr = ALIGN(*paddr, size); > - pci_set_io_region_addr(bdf, region_num, *paddr); > - *paddr += size; > - } > + pci_bios_64bit_addr = ALIGN(pci_bios_64bit_addr, size); > + pci_set_io_region_addr(bdf, region_num, (u32)pci_bios_64bit_addr); > + pci_set_io_region_addr(bdf, region_num + 1, > + (u32)(pci_bios_64bit_addr >> 32)); > + pci_bios_64bit_addr += size; > + return is_64bit; > } > > - int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) && > - (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64; > - if (is_64bit && size > 0) { > - pci_config_writel(bdf, ofs + 4, 0); > - } > + *paddr = ALIGN(*paddr, size); > + pci_set_io_region_addr(bdf, region_num, *paddr); > + if (is_64bit) > + pci_set_io_region_addr(bdf, region_num + 1, 0); > + *paddr += size; > return is_64bit; > } > > @@ -409,6 +411,7 @@ pci_setup(void) > pci_bios_io_addr = 0xc000; > pci_bios_mem_addr = BUILD_PCIMEM_START; > pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START; > + pci_bios_64bit_addr = ALIGN(RamSizeOver4G + 0x100000000ull, 0x100000000ull); > > pci_bios_init_bus(); > > > -- yamahata ----- End forwarded message ----- -- yamahata

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FWD:[PATCH] [Seabios] Over 4GB address ranges for 64bit PCI BARs]
by Isaku Yamahata 06 Nov '10

06 Nov '10

FWD ----- Forwarded message from Alexey Korolev <alexey.korolev(a)endace.com> ----- Subject: [PATCH] [Seabios] Over 4GB address ranges for 64bit PCI BARs X-Mailer: Evolution 2.24.3 Hi, We have seen some issues with 64bit PCI address and large BAR region support in seabios. On attempting to register a 64bit BAR of 1GB size we had some strange failures in qemu. After some debugging we find out that source of the issue was in seabios PCI enumeration code. The issue takes place because of u32 overflow in pciinit.c. …......... if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) { dprintf(1, "prefmem region of (bdf 0x%x bar %d) can't be mapped. " "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n", bdf, region_num, BUILD_PCIPREFMEM_SIZE); size = 0; } …........... if (size > 0) { *paddr = ALIGN(*paddr, size); pci_set_io_region_addr(bdf, region_num, *paddr); *paddr += size; } If size is greater than 0xFFFFFFFF ??? BUILD_PCIPREFMEM_START (256MB), this call ALIGN(*paddr, size) will always return 0. The protection test fails, size remains > 0, and guest memory mapping will be corrupted. We have found that a very similar problem was discussed previously: http://www.mail-archive.com/qemu-devel@nongnu.org/msg38090.html The discussion also touches on the question of 64bit addressing for PCI BARs. In the current implementation regardless of whether the PCI BAR type is 64bit or not the addressable range will be limited to the first 4GB. We also want to have "true" 64bit addressable range for PCI BARs. So to solve these issues some changes were made. Tracking for overflows has been added as well as support for 64bit range. To support the full 64bit address range a pci_bios_64bit_addr variable has been added. The 64bit range can be used only if BAR has PCI_BASE_ADDRESS_MEM_TYPE_64 attribute and the given region doesn't fit in first 4GB. The patch has been tested on Linux and BSD guest OS's and it appears to work fine. Signed-off-by Alexey Korolev <Alexey.Korolev(a)endace.com> Signed-off-by Stephen Donelly <Stephen.Donelly(a)endace.com> --- pciinit.c | 83 ++++++++++++++++++++++++++++++++------------------------------ 1 file changed, 43 insertions(+), 40 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index 0346423..86c8137 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -20,6 +20,7 @@ static void pci_bios_init_device_in_bus(int bus); static u32 pci_bios_io_addr; static u32 pci_bios_mem_addr; static u32 pci_bios_prefmem_addr; +static u64 pci_bios_64bit_addr; /* host irqs corresponding to PCI irqs A-D */ const u8 pci_irqs[4] = { 10, 10, 11, 11 @@ -56,9 +57,11 @@ static int pci_bios_allocate_region(u16 bdf, int region_num) { u32 *paddr; u32 ofs = pci_bar(bdf, region_num); - u32 old = pci_config_readl(bdf, ofs); u32 mask; + u32 limit_addr; + int is_64bit; + if (region_num == PCI_ROM_SLOT) { mask = PCI_ROM_ADDRESS_MASK; pci_config_writel(bdf, ofs, mask); @@ -73,50 +76,49 @@ static int pci_bios_allocate_region(u16 bdf, int region_num) pci_config_writel(bdf, ofs, old); u32 size = (~(val & mask)) + 1; - if (val != 0) { - if (val & PCI_BASE_ADDRESS_SPACE_IO) { - paddr = &pci_bios_io_addr; - if (ALIGN(*paddr, size) + size >= 64 * 1024) { - dprintf(1, - "io region of (bdf 0x%x bar %d) can't be mapped.\n", - bdf, region_num); - size = 0; - } - } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) && - /* keep behaviour on bus = 0 */ - pci_bdf_to_bus(bdf) != 0 && - /* If pci_bios_prefmem_addr == 0, keep old behaviour */ - pci_bios_prefmem_addr != 0) { - paddr = &pci_bios_prefmem_addr; - if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) { - dprintf(1, - "prefmem region of (bdf 0x%x bar %d) can't be mapped. " - "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n", - bdf, region_num, BUILD_PCIPREFMEM_SIZE); - size = 0; - } - } else { - paddr = &pci_bios_mem_addr; - if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) { + if (!val || !size) + return 0; + + is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) && + (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64; + + if (val & PCI_BASE_ADDRESS_SPACE_IO) { + paddr = &pci_bios_io_addr; + limit_addr = 64 * 1024; + } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) && + /* keep behaviour on bus = 0 */ + pci_bdf_to_bus(bdf) != 0 && + /* If pci_bios_prefmem_addr == 0, keep old behaviour */ + pci_bios_prefmem_addr != 0) { + paddr = &pci_bios_prefmem_addr; + limit_addr = BUILD_PCIPREFMEM_END; + } else { + paddr = &pci_bios_mem_addr; + limit_addr = BUILD_PCIMEM_END; + } + + /* The region is out of allowed 32bit mapping range */ + if ((ALIGN(*paddr, size) + size >= limit_addr) || + (ALIGN(*paddr, size) + size <= *paddr)) { + if (!is_64bit) { dprintf(1, "mem region of (bdf 0x%x bar %d) can't be mapped. " - "increase BUILD_PCIMEM_SIZE and recompile. size %x\n", - bdf, region_num, BUILD_PCIMEM_SIZE); - size = 0; + "Region size %x\n", bdf, region_num, size); + return 0; } - } - if (size > 0) { - *paddr = ALIGN(*paddr, size); - pci_set_io_region_addr(bdf, region_num, *paddr); - *paddr += size; - } + pci_bios_64bit_addr = ALIGN(pci_bios_64bit_addr, size); + pci_set_io_region_addr(bdf, region_num, (u32)pci_bios_64bit_addr); + pci_set_io_region_addr(bdf, region_num + 1, + (u32)(pci_bios_64bit_addr >> 32)); + pci_bios_64bit_addr += size; + return is_64bit; } - int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) && - (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64; - if (is_64bit && size > 0) { - pci_config_writel(bdf, ofs + 4, 0); - } + *paddr = ALIGN(*paddr, size); + pci_set_io_region_addr(bdf, region_num, *paddr); + if (is_64bit) + pci_set_io_region_addr(bdf, region_num + 1, 0); + *paddr += size; return is_64bit; } @@ -409,6 +411,7 @@ pci_setup(void) pci_bios_io_addr = 0xc000; pci_bios_mem_addr = BUILD_PCIMEM_START; pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START; + pci_bios_64bit_addr = ALIGN(RamSizeOver4G + 0x100000000ull, 0x100000000ull); pci_bios_init_bus(); ----- End forwarded message ----- -- yamahata

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Re: [SeaBIOS] seabios fails to send output to the QEMU BIOS debug port
by Kevin O'Connor 04 Nov '10

04 Nov '10

On Thu, Nov 04, 2010 at 03:03:10PM +0800, Lin Ming wrote: > Hi, > > I just find that I can't send output to the QEMU BIOS debug port. > It's caused by commit d4bded451. > > In qemu-kvm/hw/acpi_piix4.c, > #define ACPI_DBG_IO_ADDR 0xb044 > > Don't know why the DBG was changed from 0xb044 to 0x0402. > But it still does not work if I changed the port back to 0xb044. > - OperationRegion (DBG, SystemIO, 0x0402, 0x01) > + OperationRegion (DBG, SystemIO, 0xb044, 0x01) > > Any fix? That was intentional. The new system sends output using the regular bios debug mechanism - you should be able to see that output by adding the following to qemu command line: -chardev stdio,id=seabios \ -device isa-debugcon,iobase=0x402,chardev=seabios The above should be simpler then having to recompile qemu with acpi debugging. -Kevin

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[PATCH] mark irq9 active high in DSDT
by Gleb Natapov 31 Oct '10

31 Oct '10

In PIIX4 SCI (irq9) is active high. Seabios marks it so in interrupt override table, but some OSes (FreeBSD) require the same information to be present in DSDT too. Make it so. Signed-off-by: Gleb Natapov <gleb(a)redhat.com> diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl index bb0a176..dafcf45 100644 --- a/src/acpi-dsdt.dsl +++ b/src/acpi-dsdt.dsl @@ -73,7 +73,7 @@ DefinitionBlock ( #define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB) prt_slot0(0x0000), /* Device 1 is power mgmt device, and can only use irq 9 */ - Package() { 0x0001ffff, 0, 0, 9 }, + Package() { 0x0001ffff, 0, LNKS, 0 }, Package() { 0x0001ffff, 1, LNKB, 0 }, Package() { 0x0001ffff, 2, LNKC, 0 }, Package() { 0x0001ffff, 3, LNKD, 0 }, @@ -634,6 +634,46 @@ DefinitionBlock ( Store (TMP, PRQ3) } } + Device(LNKS){ + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 5) + Name(_PRS, ResourceTemplate(){ + Interrupt (, Level, ActiveHigh, Shared) + { 9 } + }) + Method (_STA, 0, NotSerialized) + { + Store (0x0B, Local0) + If (And (0x80, PRQ0, Local1)) + { + Store (0x09, Local0) + } + Return (Local0) + } + Method (_DIS, 0, NotSerialized) + { + Or (PRQ0, 0x80, PRQ0) + } + Method (_CRS, 0, NotSerialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (, Level, ActiveHigh, Shared) + {9} + }) + CreateDWordField (PRR0, 0x05, TMP) + Store (PRQ0, Local0) + If (LLess (Local0, 0x80)) + { + Store (Local0, TMP) + } + Else + { + Store (Zero, TMP) + } + Return (PRR0) + } + } } /* -- Gleb.

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Re: [SeaBIOS] [PATCH v2 2/2] pciinit: use pci_region functions.
by Michael S. Tsirkin 28 Oct '10

28 Oct '10

As a sepaate note, BIOS currently seems to allocate regions in-order, correct? A classical trick is to allocate regions behind each bridge in the reverse order of their size. This avoids holes due to alignment. -- MST

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Re: [SeaBIOS] [PATCH v2 1/2] pci: introduce pci_region to manage pci io/memory/prefmemory regions.
by Michael S. Tsirkin 28 Oct '10

28 Oct '10

On Thu, Oct 28, 2010 at 02:04:05PM +0900, Isaku Yamahata wrote: > This patch adds helper functions to manage pci area. > > Signed-off-by: Isaku Yamahata <yamahata(a)valinux.co.jp> > > --- > Changes v1 -> v2 > - add comments > --- > Makefile | 3 +- > src/pci_region.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > src/util.h | 28 +++++++++++++++++++ > 3 files changed, 107 insertions(+), 1 deletions(-) > create mode 100644 src/pci_region.c > > diff --git a/Makefile b/Makefile > index 9d412f1..1663a5d 100644 > --- a/Makefile > +++ b/Makefile > @@ -19,7 +19,8 @@ SRCBOTH=misc.c pmm.c stacks.c output.c util.c block.c floppy.c ata.c mouse.c \ > SRC16=$(SRCBOTH) system.c disk.c font.c > SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \ > acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \ > - lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c > + lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c dev-i440fx.c \ > + pci_region.c > SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c > > cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \ > diff --git a/src/pci_region.c b/src/pci_region.c > new file mode 100644 > index 0000000..c8656cb > --- /dev/null > +++ b/src/pci_region.c > @@ -0,0 +1,77 @@ > +// helper functions to manage pci io/memory/prefetch memory region > +// > +// Copyright (C) 2009 Isaku Yamahata <yamahata at valinux co jp> > +// > +// This file may be distributed under the terms of the GNU LGPLv3 license. > +// > +// > + > +#include "util.h" > + > +#define PCI_REGION_DISABLED (-1) > + > +void pci_region_init(struct pci_region *r, u32 start, u32 end) > +{ > + r->start = start; > + r->end = end; > + > + r->cur_end = start; > +} > + > +// PCI_REGION_DISABLED represents that the region is in special state. > +// its value is chosen such that cur_end can't be PCI_REGION_DISABLED normally. > +u32 pci_region_disable(struct pci_region *r) > +{ > + return r->cur_end = PCI_REGION_DISABLED; > +} > + > +static int pci_region_disabled(const struct pci_region *r) > +{ > + return r->cur_end == PCI_REGION_DISABLED; > +} > + > +static u32 pci_region_alloc_align(struct pci_region *r, u32 size, u32 align) > +{ > + if (pci_region_disabled(r)) { > + return 0; > + } > + > + u32 s = ALIGN(r->cur_end, align); > + if (s > r->end || s < r->cur_end) { > + return 0; > + } > + u32 e = s + size; > + if (e > r->end || e < s) { > + return 0; > + } > + r->cur_end = e; > + return s; > +} > + > +u32 pci_region_alloc(struct pci_region *r, u32 size) > +{ > + return pci_region_alloc_align(r, size, size); > +} > + > +u32 pci_region_align(struct pci_region *r, u32 align) > +{ > + return pci_region_alloc_align(r, 0, align); > +} > + > +void pci_region_revert(struct pci_region *r, u32 addr) > +{ > + r->cur_end = addr; > +} > + > +u32 pci_region_addr(const struct pci_region *r) > +{ > + if (pci_region_disabled(r)){ > + return r->end; > + } > + return r->cur_end; > +} > + > +u32 pci_region_size(const struct pci_region *r) > +{ > + return r->end - r->start; > +} > diff --git a/src/util.h b/src/util.h > index 5cc9f17..17eedd0 100644 > --- a/src/util.h > +++ b/src/util.h > @@ -344,6 +344,34 @@ void qemu_prep_reset(void); > void smm_save_and_copy(void); > void smm_relocate_and_restore(void); > > +// pci_region.c > +// region allocator. pci region allocates the requested region > +// sequentially with overflow check. > +struct pci_region { > + // The region is [start, region). [start end)? > + u32 start; > + u32 end; > + > + // The next allocation is start from this. > + // i.e. [start, cur_end) is allocated. > + // Right after initialization cur_end == start. > + u32 cur_end; What is the value for a region at 0xfffff000 and size 0x1000? Maybe first, last is better to detect this? > +}; > +// initialize the pci_region of [start, end) > +void pci_region_init(struct pci_region *r, u32 start, u32 end); > +// allocate the region of size > +u32 pci_region_alloc(struct pci_region *r, u32 size); > +// make the next allocation aligned to align > +u32 pci_region_align(struct pci_region *r, u32 align); > +// revert the allocation to addr. > +void pci_region_revert(struct pci_region *r, u32 addr); > +// make the allocation fail. > +u32 pci_region_disable(struct pci_region *r); > +// returns the current allocation point. > +u32 pci_region_addr(const struct pci_region *r); > +// returns the region size. > +u32 pci_region_size(const struct pci_region *r); > + > // pciinit.c > extern const u8 pci_irqs[4]; > void pci_bios_allocate_regions(u16 bdf, void *arg); > -- > 1.7.1.1

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[PATCH v2 0/2] pciinit: fix overflow when bar allocation
by Isaku Yamahata 28 Oct '10

28 Oct '10

Okay, now added comments to members and functions as requested. No essential code change. Changes v1 -> v2: - add comment. Patch description: This patch set fixes PCI bar allocation when bar overflow occured. I checked if pmm_alloc facility can be used, but it doesn't suit for pci bar allocation. So I resulted in new API, pci_region which encapsulates region allocation and overflow checks. The first patch introduces pci_region, and the second patch fixes the overflow case with pci_region. Isaku Yamahata (2): pci: introduce pci_region to manage pci io/memory/prefmemory regions. pciinit: use pci_region functions. Makefile | 3 +- src/pci_region.c | 77 ++++++++++++++++++++++++++++++++++ src/pciinit.c | 122 ++++++++++++++++++++++++++--------------------------- src/util.h | 28 ++++++++++++ 4 files changed, 167 insertions(+), 63 deletions(-) create mode 100644 src/pci_region.c

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Re: [SeaBIOS] [Qemu-devel] [PATCH 1/2] pci: Automatically patch PCI device id in PCI ROM
by Anthony Liguori 21 Oct '10

21 Oct '10

On 10/15/2010 03:51 PM, Stefan Weil wrote: > PCI device with different device ids sometimes share > the same rom code. Only the device id and the checksum > differ in a boot rom for such devices. > BTW, SeaBIOS doesn't reject ROMs when they're loaded via rombar, only when they're loaded via romfile. Maybe it's better to use fw_cfg to explicitly tell SeaBIOS to ignore the PCI device id in the rom header for a certain device? Regards, Anthony Liguori > The i825xx ethernet controller family is a typical example > which is implemented in hw/eepro100.c. It uses at least > 3 different device ids, so normally 3 boot roms would be needed. > > By automatically patching the device id (and the checksum) > in qemu, all emulated family members can share the same > boot rom. > > Cc: Markus Armbruster<armbru(a)redhat.com> > Cc: Michael S. Tsirkin<mst(a)redhat.com> > Signed-off-by: Stefan Weil<weil(a)mail.berlios.de> > --- > hw/pci.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 53 insertions(+), 0 deletions(-) > > diff --git a/hw/pci.c b/hw/pci.c > index 1280d4d..c1f8218 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -1797,6 +1797,57 @@ static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, p > cpu_register_physical_memory(addr, size, pdev->rom_offset); > } > > +/* Patch the PCI device id in a PCI rom image if necessary. > + This is needed for an option rom which is used for more than one device. */ > +static void pci_patch_device_id(PCIDevice *pdev, uint8_t *ptr, int size) > +{ > + uint16_t vendor_id; > + uint16_t device_id; > + uint16_t rom_vendor_id; > + uint16_t rom_device_id; > + uint16_t rom_magic; > + uint16_t pcir_offset; > + > + /* Words in rom data are little endian (like in PCI configuration), > + so they can be read / written with pci_get_word / pci_set_word. */ > + > + /* Only a valid rom will be patched. */ > + rom_magic = pci_get_word(ptr); > + if (rom_magic != 0xaa55) { > + PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); > + return; > + } > + pcir_offset = pci_get_word(ptr + 0x18); > + if (pcir_offset + 8>= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { > + PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); > + return; > + } > + > + vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); > + device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); > + rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); > + rom_device_id = pci_get_word(ptr + pcir_offset + 6); > + > + /* Don't patch a rom with wrong vendor id (might be changed if needed). */ > + if (vendor_id != rom_vendor_id) { > + return; > + } > + > + PCI_DPRINTF("ROM id %04x%04x / PCI id %04x%04x\n", > + vendor_id, device_id, rom_vendor_id, rom_device_id); > + > + if (device_id != rom_device_id) { > + /* Patch device id and checksum (at offset 6 for etherboot roms). */ > + uint8_t checksum; > + checksum = ptr[6]; > + checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id>> 8); > + checksum -= (uint8_t)device_id + (uint8_t)(device_id>> 8); > + PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); > + ptr[6] = checksum; > + pci_set_word(ptr + pcir_offset + 6, device_id); > + } > +} > + > /* Add an option rom for the device */ > static int pci_add_option_rom(PCIDevice *pdev) > { > @@ -1849,6 +1900,8 @@ static int pci_add_option_rom(PCIDevice *pdev) > load_image(path, ptr); > qemu_free(path); > > + pci_patch_device_id(pdev, ptr, size); > + > pci_register_bar(pdev, PCI_ROM_SLOT, size, > 0, pci_map_option_rom); > >

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