SeaBIOS

seabios@seabios.org

2 participants
3799 discussions

How to add support for PCIe bridge to coreboot on Baytrial SoC
by zahra rahimkhani 13 Jan '20

13 Jan '20

I Compiled Coreboot with Seabios and Tianocore payload on Baytrail SoC. I want to use a [PCIe bridge][3] to convert a PCIE-x1 to 2 PCIE-X1 connectors but booting FreeBSD won't show any active bridge. The [Baytrail SoC documentation][1] states that a register called [SLCTL_SLSTS][2] should be set in order to activate the bridge support but I don't know how to set such flag on coreboot. - Is it possible to use PCIe bridge on Baytrail SoCs? - How one can add bridge support to coreboot if possible? [1]: https://www.mouser.com/datasheet/2/612/atom-e3800-family-datasheet-1522396.… [2]: https://github.com/coreboot/coreboot/blob/master/src/soc/intel/baytrail/inc… [3]: https://www.amazon.co.uk/IOCrest-Ports-Extension-Switch-Multiplier/dp/B075K…

1 0

[PATCH v2 0/2] Initialize only bootable virtio-blk/virtio-blk
by Alexey Kirillov 06 Jan '20

06 Jan '20

This patch aimed to avoid problem with uninitialized virtio-blk and virtio-scsi boot devices. Currently, 12 KiB of memory is allocated for each virtio-blk/scsi, so no more than about 10 devices can be initialized. If the device is not initialized, we cannot boot from it. So, if we have more than 10 devices, we can't boot from any of the following (11, 12, etc.). We can initialize only bootable devices, i.e. listed in boot order list, that this patch does. Alexey Kirillov (2): boot: Detect strict boot order (HALT record) in function virtio: Do not init non-bootable devices src/boot.c | 5 +++++ src/hw/virtio-blk.c | 11 ++++++++++- src/hw/virtio-scsi.c | 11 ++++++++++- src/util.h | 1 + 4 files changed, 26 insertions(+), 2 deletions(-) -- 2.17.1

2 3

strange behavior (regression?) with SeaBIOS + iPXE + WDSNBP.COM
by Laszlo Ersek 02 Jan '20

02 Jan '20

Hi Michael & Lists, I'd like to ask for ideas with the following problem we have. (1) There is a functional iPXE + WDS setup, with iPXE built as a traditional BIOS PCI option ROM, using CONFIG=qemu. Accordingly the platform is qemu, with SeaBIOS, and the NIC is virtio-net-pci. I don't know anything about the particulars of the WDS setup at this point, only that the boot loader program it exposes is WDSNBP.COM. (2) The setup works fine when iPXE is built at commit 4e85b2708fa0 ("[virtio] Use host-specified MTU when available", 2017-01-23). (3) When iPXE is built at commit 133f4c47baef ("[build] Handle R_X86_64_PLT32 from binutils 2.31", 2018-09-17), the setup breaks. The symptom is that iPXE fetches WDSNBP.COM just fine, but WDSNBP.COM, rather than doing whatever it does otherwise, keeps PXE-booting itself (3+ times), and finally aborts. Consider the following log output (my undertanding is that all this is logged by WDSNBP.COM): > Downloaded WDSNBP... > > Press F12 for network service boot > Architecture: x64 > WDSNBP started using DHCP Referral. > Contacting Server: ... (Gateway: ...) > Contacting Server: ... > TFTP Download: boot\x86\wdsnbp.com This block repeats approx. 3 times, after which the following is displayed: > Windows Deployment Services: PXE Boot Aborted. > Could not boot image: Error 0x7f8d8101 (http://ipxe.org/7f8d8101) > No more network devices > > No bootable device My understanding is that the first line from this last block is printed by WDSNBP.COM, the second line by iPXE (in pxe_start_nbp()), the third line also by iPXE, and the last one by SeaBIOS. This seems to indicate that WDSNBP.COM exits with an error code, and pxe_start_nbp() logs it as "Error 0x7f8d8101". (4) Now, after a bit of searching the web, I've found the following articles, which indicate that the WDS (= server side) setup is incorrect: (4a) "disable NetBios over TCPIP, on the WDS server" https://techthoughts.info/pxe-booting-wds-dhcp-scope-vs-ip-helpers/#comment… https://social.technet.microsoft.com/Forums/ie/en-US/f3883e8b-1039-477d-999… (4b) "cover all combinations of forward and backwards slashes in ReadFilter, on the WDS server" http://ipxe.org/appnote/chainload_wds#tftp_loops However: the regression appears to be a function of *only* the git commit at which we build iPXE. It seems so deterministic that we bisected commit range 4e85b2708fa0..133f4c47baef. (Hence we have not captured the network traffic yet, nor have we investigated the WDS server config.) The "culprit" commit is ea29122a70c6 ("[http] Include error messages for 4xx and 5xx response codes", 2017-12-28). (5) Which makes no sense to me, unfortunately. :( Commit ea29122a70c6 adds the "http_errors" array to the code. According to src/include/ipxe/tables.h and the build artifact src/bin/1af41000.rom.tmp.map this new array is placed in a new section called .textdata.tbl.errortab.01 Trying to retro-fit those facts to the symptom encountered, I came up with the idea that *maybe* the new array (or section) causes a memory allocation failure in WDSNBP.COM -- due to increased memory footprint of iPXE. Which then leads to the misbehavior of WDSNBP.COM. After all, WDSNBP.COM is a 16-bit real-mode program: https://support.microsoft.com/en-us/help/4468601/pxe-boot-in-configuration-… so it could be susceptible to the size & fragmentation of the RAM that is under 640KB. (6) Unfortunately, this "low RAM exhaustion" idea doesn't seem to hold water. There are at least two counter-arguments: (6a) if I revert commit ea29122a70c6 on top of commit 133f4c47baef, then the issue does *not* go away. (The issue also does not go away if I remove the "netdev_errors" array, also on top of commit 133f4c47baef -- that's a larger array.) (... In theory anyway, this might not necessarily disprove the memory exhaustion idea. What if the iPXE footprint grows, over the ea29122a70c6..133f4c47baef so much, for independent reasons, that reverting ea29122a70c6 at the end cannot compensate for that increase?) (6b) I added "DEBUG=pxe_call:1" to the "make" command, and compared the debug messages printed by pxe_start_nbp(), between 4e85b2708fa0 and 133f4c47baef. Alas, the debug messages are identical: > PXE NBP starting with netdev net0, code 9c6c:0802, data 9cf0:2ce0 which to me suggests that there is no change in the amount of memory that is made available to WDSNBP.COM -- its code and data continue to start at 0x9_CEC2 and 0x9_FBE0, respectively. Any hints as to what could be going wrong? Thanks! Laszlo

2 5

[PATCH 0/1] Initialize only bootable virtio-blk/virtio-blk
by Alexey Kirillov 20 Dec '19

20 Dec '19

This patch aimed to avoid problem with uninitialized virtio-blk and virtio-scsi boot devices. Currently, 12 KiB of memory is allocated for each virtio-blk/scsi, so no more than about 10 devices can be initialized. If the device is not initialized, we cannot boot from it. So, if we have more than 10 devices, we can't boot from any of the following (11, 12, etc.). We can initialize only bootable devices, i.e. listed in boot order list, that this patch does. Alexey Kirillov (1): virtio: do not init non-bootable devices docs/Runtime_config.md | 1 + src/hw/virtio-blk.c | 10 ++++++++++ src/hw/virtio-scsi.c | 10 ++++++++++ 3 files changed, 21 insertions(+) -- 2.17.1

2 4

[PATCH v2 1/3] csm: Call pci_probe_devices() late until PrepareToBoot is invoked by UEFI
by Bin Gao 20 Dec '19

20 Dec '19

On physical hardware, some PCI devices are not detectable when UEFI BIOS invokes our InitializeYourself() function. But they are guaranteed to be available before UEFI invokes our PreparToBoot() function. So in the case of running CSM on physical hardware, we execute pci_probe_devices() at PrepareToBoot() stage. Signed-off-by: Bin Gao <gaobin(a)amazon.com> --- src/fw/csm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/fw/csm.c b/src/fw/csm.c index 8359bcb..82d375c 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -63,7 +63,9 @@ static void csm_maininit(struct bregs *regs) { interface_init(); - pci_probe_devices(); + + if (CONFIG_CSM && CONFIG_QEMU_HARDWARE) + pci_probe_devices(); csm_compat_table.PnPInstallationCheckSegment = SEG_BIOS; csm_compat_table.PnPInstallationCheckOffset = get_pnp_offset(); @@ -143,6 +145,13 @@ handle_csm_0002(struct bregs *regs) return; } + // On physical hardware, some PCI devices are not detectable when + // UEFI invokes our InitializeYourself() function. But they + // are guaranteed to be available before UEFI invokes our + // PreparToBoot() function. + if (CONFIG_CSM && !CONFIG_QEMU_HARDWARE) + pci_probe_devices(); + dprintf(3, "PrepareToBoot table %04x:%04x\n", regs->es, regs->bx); struct e820entry *p = (void *)csm_compat_table.E820Pointer; -- 2.17.1

2 7

[PATCH v2] hw/usb-hid: handle devices with illegal max packet size
by Matt DeVillier 13 Dec '19

13 Dec '19

Some USB keyboards report 9 or 10-byte max packet sizes, instead of the 8-byte max specified by the USB HID spec. Handle this by increasing the size of the keyevent struct to 10 bytes, zeroizing it before use, and using the key array size of the usbkeyinfo struct as loop bounds rather than that of the keyevent struct (since the former will always be smaller, and within spec) to prevent buffer overflow. Test: built/boot on Google Pixel Slate, observe keyboard functional Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/hw/usb-hid.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/hw/usb-hid.c b/src/hw/usb-hid.c index fa4d9a2..bce1b5f 100644 --- a/src/hw/usb-hid.c +++ b/src/hw/usb-hid.c @@ -8,6 +8,7 @@ #include "config.h" // CONFIG_* #include "output.h" // dprintf #include "ps2port.h" // ATKBD_CMD_GETID +#include <string.h> //memset #include "usb.h" // usb_ctrlrequest #include "usb-hid.h" // usb_keyboard_setup #include "util.h" // process_key @@ -59,8 +60,10 @@ usb_kbd_setup(struct usbdevice_s *usbdev // XXX - this enables the first found keyboard (could be random) return -1; - if (epdesc->wMaxPacketSize != 8) + if (epdesc->wMaxPacketSize > 10) { + dprintf(1, "USB keyboard endpoint wMaxPacketSize > 10; aborting\n"); return -1; + } // Enable "boot" protocol. int ret = set_protocol(usbdev->defpipe, 0); @@ -163,11 +166,15 @@ static u16 ModifierToScanCode[] VAR16 = { #define RELEASEBIT 0x80 -// Format of USB keyboard event data +// Format of USB keyboard event data. +// Some keyboards use a 9/10 byte packet size, +// so account for that here to prevent buffer +// overflow. We'll ignore the 9th/10th bytes +// as it's out of spec. struct keyevent { u8 modifiers; u8 reserved; - u8 keys[6]; + u8 keys[8]; }; // Translate data from KeyToScanCode[] to calls to process_key(). @@ -253,7 +260,7 @@ handle_key(struct keyevent *data) break; int j; for (j=0;; j++) { - if (j>=ARRAY_SIZE(data->keys)) { + if (j>=ARRAY_SIZE(old.keys)) { // Key released. procscankey(key, RELEASEBIT, data->modifiers); if (i+1 >= ARRAY_SIZE(old.keys) || !old.keys[i+1]) @@ -274,7 +281,7 @@ handle_key(struct keyevent *data) // Process new keys procmodkey(data->modifiers & ~old.modifiers, 0); old.modifiers = data->modifiers; - for (i=0; i<ARRAY_SIZE(data->keys); i++) { + for (i=0; i<ARRAY_SIZE(old.keys); i++) { u8 key = data->keys[i]; if (!key) continue; @@ -310,6 +317,8 @@ usb_check_key(void) for (;;) { struct keyevent data; + // zeroize struct as most keyboards won't fill it + memset(&data, 0, sizeof(data)); int ret = usb_poll_intr(pipe, &data); if (ret) break; -- 2.20.1

1 0

Subject: [PATCH 1/2] hw/usb-hid: handle devices with illegal max packet size
by Matt DeVillier 13 Dec '19

13 Dec '19

Some USB keyboards report 9 or 10-byte max packet sizes, instead of the 8-byte max specified by the USB HID spec. Handle this by increasing the size of the keyevent struct to 10 bytes, zeroizing it before use, and using the key array size of the usbkeyinfo struct as loop bounds rather than that of the keyevent struct (since the former will always be smaller, and within spec). Test: built/boot on Google Pixel Slate, observe keyboard functional Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/hw/usb-hid.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/hw/usb-hid.c b/src/hw/usb-hid.c index fa4d9a2..cedec0b 100644 --- a/src/hw/usb-hid.c +++ b/src/hw/usb-hid.c @@ -8,6 +8,7 @@ #include "config.h" // CONFIG_* #include "output.h" // dprintf #include "ps2port.h" // ATKBD_CMD_GETID +#include <string.h> //memset #include "usb.h" // usb_ctrlrequest #include "usb-hid.h" // usb_keyboard_setup #include "util.h" // process_key @@ -59,7 +60,7 @@ usb_kbd_setup(struct usbdevice_s *usbdev // XXX - this enables the first found keyboard (could be random) return -1; - if (epdesc->wMaxPacketSize != 8) + if (epdesc->wMaxPacketSize > 10) return -1; // Enable "boot" protocol. @@ -163,11 +164,15 @@ static u16 ModifierToScanCode[] VAR16 = { #define RELEASEBIT 0x80 -// Format of USB keyboard event data +// Format of USB keyboard event data. +// Some keyboards use a 9/10 byte packet size, +// so account for that here to prevent buffer +// overflow. We'll ignore the 9th/10th bytes +// as it's out of spec. struct keyevent { u8 modifiers; u8 reserved; - u8 keys[6]; + u8 keys[8]; }; // Translate data from KeyToScanCode[] to calls to process_key(). @@ -253,7 +258,7 @@ handle_key(struct keyevent *data) break; int j; for (j=0;; j++) { - if (j>=ARRAY_SIZE(data->keys)) { + if (j>=ARRAY_SIZE(old.keys)) { // Key released. procscankey(key, RELEASEBIT, data->modifiers); if (i+1 >= ARRAY_SIZE(old.keys) || !old.keys[i+1]) @@ -274,7 +279,7 @@ handle_key(struct keyevent *data) // Process new keys procmodkey(data->modifiers & ~old.modifiers, 0); old.modifiers = data->modifiers; - for (i=0; i<ARRAY_SIZE(data->keys); i++) { + for (i=0; i<ARRAY_SIZE(old.keys); i++) { u8 key = data->keys[i]; if (!key) continue; @@ -310,6 +315,8 @@ usb_check_key(void) for (;;) { struct keyevent data; + //zeroize struct as most keyboards won't fill it + memset(&data, 0, sizeof(data)); int ret = usb_poll_intr(pipe, &data); if (ret) break; -- 2.20.1

2 1

[PATCH 4/4] serialio: Support for pci serial ports
by Your Real Name 11 Dec '19

11 Dec '19

From f65c435b8e3caf7249a3fb25150e7055898ccc12 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Fri, 18 Oct 2019 23:00:21 -0700 Subject: [PATCH 4/4] serialio: Support for pci serial ports Some Intel PCHs integrate pci uarts which are used for serial port debugging. For compatibility purpose, BIOS implementation may assign 0x3f8 to the pci uart's io bar at PEI stage, later during DXE stage the pci uart's bar is re-assigned to a different address. As a result, we can't use the hard coded IO port 0x3f8 in SeaBIOS for debugging. Instead, we need read the port base address from the pci uart's BAR, either an IO BAR, or a 32bit memory BAR. This patch adds support for pci serial port debugging. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/Kconfig | 34 +++++++++++++++++++++++++++++++++- src/hw/serialio.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 60 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6606ce4..6d9ce3b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -550,8 +550,40 @@ menu "Debugging" default 0x3f8 help Base port for serial - generally 0x3f8, 0x2f8, 0x3e8, or 0x2e8. - config DEBUG_SERIAL_MMIO + config DEBUG_SERIAL_PCI_IO depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL + bool "Serial port debugging via PCI IO" + default n + help + Send debugging information to PCI serial port. + The base address of the uart is in the PCI device's IO bar. + config DEBUG_SERIAL_PCI_MEM32 + depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO + bool "Serial port debugging via PCI MEM32" + default n + help + Send debugging information to PCI serial port. + The base address of the uart is in the PCI device's MEM32 bar. + config DEBUG_SERIAL_PCI_BDF + depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32 + hex "Serial port PCI bus/device/function" + range 0 ffff + help + 16bit hex of B:D:F of the PCI serial port. + Bit 15:8 - bus, bit 7:3 - device, bit 2:0 - function + E.g. for a PCI device: bus 0x0, dev 0x1a, func 0x1 you + should input 00d1. + config DEBUG_SERIAL_PCI_BAR + depends on DEBUG_SERIAL_PCI_IO || DEBUG_SERIAL_PCI_MEM32 + hex "Serial port PCI BAR index (0 - 5)" + range 0 5 + default 0 + help + The index of the BAR where the base address would be read + from for the PCI serial port. Only IO BAR and 32bit memory + BAR are supported. + config DEBUG_SERIAL_MMIO + depends on DEBUG_LEVEL != 0 && !DEBUG_SERIAL && !DEBUG_SERIAL_PCI_IO && !DEBUG_SERIAL_PCI_MEM32 bool "Serial port debugging via memory mapped IO" default n help diff --git a/src/hw/serialio.c b/src/hw/serialio.c index 3163344..9a8565c 100644 --- a/src/hw/serialio.c +++ b/src/hw/serialio.c @@ -9,6 +9,7 @@ #include "output.h" // dprintf #include "serialio.h" // serial_debug_preinit #include "x86.h" // outb +#include "pci.h" //pci_config_readw /**************************************************************** @@ -23,6 +24,15 @@ serial_debug_write(u8 offset, u8 val) { if (CONFIG_DEBUG_SERIAL) { outb(val, CONFIG_DEBUG_SERIAL_PORT + offset); + } else if (CONFIG_DEBUG_SERIAL_PCI_IO) { + u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3); + outb(val, base + offset); + } else if (CONFIG_DEBUG_SERIAL_PCI_MEM32) { + ASSERT32FLAT(); + u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7); + writeb((void*)base + 4*offset, val); } else if (CONFIG_DEBUG_SERIAL_MMIO) { ASSERT32FLAT(); writeb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset, val); @@ -35,6 +45,17 @@ serial_debug_read(u8 offset) { if (CONFIG_DEBUG_SERIAL) return inb(CONFIG_DEBUG_SERIAL_PORT + offset); + if (CONFIG_DEBUG_SERIAL_PCI_IO) { + u16 base = pci_config_readw(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x3); + return inb(base + offset); + } + if (CONFIG_DEBUG_SERIAL_PCI_MEM32) { + ASSERT32FLAT(); + u32 base = pci_config_readl(CONFIG_DEBUG_SERIAL_PCI_BDF, + 0x10 + CONFIG_DEBUG_SERIAL_PCI_BAR*4) & (~0x7); + return readb((void*)base + 4*offset); + } if (CONFIG_DEBUG_SERIAL_MMIO) { ASSERT32FLAT(); return readb((void*)CONFIG_DEBUG_SERIAL_MEM_ADDRESS + 4*offset); @@ -65,7 +86,9 @@ serial_debug_preinit(void) static void serial_debug(char c) { - if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT)) + if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO && + ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) || + MODESEGMENT)) return; int timeout = DEBUG_TIMEOUT; while ((serial_debug_read(SEROFF_LSR) & 0x20) != 0x20) @@ -87,7 +110,9 @@ serial_debug_putc(char c) void serial_debug_flush(void) { - if (!CONFIG_DEBUG_SERIAL && (!CONFIG_DEBUG_SERIAL_MMIO || MODESEGMENT)) + if (!CONFIG_DEBUG_SERIAL && !CONFIG_DEBUG_SERIAL_PCI_IO && + ((!CONFIG_DEBUG_SERIAL_MMIO && !CONFIG_DEBUG_SERIAL_PCI_MEM32) || + MODESEGMENT)) return; int timeout = DEBUG_TIMEOUT; while ((serial_debug_read(SEROFF_LSR) & 0x60) != 0x60) -- 2.17.1

3 11

[PATCH 3/4] csm: Enable boot from pci option rom
by Your Real Name 11 Dec '19

11 Dec '19

From 9ca6590769692b99e98acf48acc3ce700238e451 Mon Sep 17 00:00:00 2001 From: gaobin <gaobin(a)amazon.com> Date: Thu, 19 Sep 2019 22:47:43 -0700 Subject: [PATCH 3/4] csm: Enable boot from pci option rom In csm mode, the bev pointer of the pci option rom was not added to the bootentry list, resulting in failure to boot from pci option rom. This patch fixed it. Signed-off-by: gaobin <gaobin(a)amazon.com> --- src/fw/csm.c | 18 ++++++++++++++++++ src/optionroms.c | 2 +- src/util.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/fw/csm.c b/src/fw/csm.c index c8111cd..8e2a1aa 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -19,6 +19,7 @@ #include "std/acpi.h" // RSDP_SIGNATURE #include "std/bda.h" // struct bios_data_area_s #include "std/optionrom.h" // struct rom_header +#include "std/pnpbios.h" // PNP_SIGNATURE #include "util.h" // copy_smbios #define UINT8 u8 @@ -218,12 +219,16 @@ handle_csm_0003(struct bregs *regs) regs->ax = 1; } +static int rom_instance; + /* Legacy16DispatchOprom */ static void handle_csm_0005(struct bregs *regs) { EFI_DISPATCH_OPROM_TABLE *table = MAKE_FLATPTR(regs->es, regs->bx); struct rom_header *rom; + struct pnp_data *pnp; + u64 sources[(BUILD_BIOS_ADDR - BUILD_ROM_START) / OPTION_ROM_ALIGN]; u16 bdf; if (!CONFIG_OPTIONROMS) { @@ -250,6 +255,19 @@ handle_csm_0005(struct bregs *regs) rom_confirm(rom->size * 512); + // PnP rom - check for BEV and BCV boot capabilities. + pnp = (void*)((u8*)rom + rom->pnpoffset); + if (pnp->signature == PNP_SIGNATURE) { + if (pnp->bev) + boot_add_bev(FLATPTR_TO_SEG(rom), pnp->bev, pnp->productname, + getRomPriority(sources, rom, rom_instance++)); + else if (pnp->bcv) + boot_add_bcv(FLATPTR_TO_SEG(rom), pnp->bcv, pnp->productname, + getRomPriority(sources, rom, rom_instance++)); + } else { + dprintf(1, "rom 0x%p is not PnP rom, no BEV and BCV capability\n", table); + } + regs->bx = 0; // FIXME regs->ax = 0; } diff --git a/src/optionroms.c b/src/optionroms.c index e906ab9..4f3848d 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -153,7 +153,7 @@ setRomSource(u64 *sources, struct rom_header *rom, u64 source) sources[((u32)rom - BUILD_ROM_START) / OPTION_ROM_ALIGN] = source; } -static int +int getRomPriority(u64 *sources, struct rom_header *rom, int instance) { u64 source = sources[((u32)rom - BUILD_ROM_START) / OPTION_ROM_ALIGN]; diff --git a/src/util.h b/src/util.h index b173fa8..0a52338 100644 --- a/src/util.h +++ b/src/util.h @@ -217,6 +217,7 @@ int is_pci_vga(struct pci_device *pci); void optionrom_setup(void); void vgarom_setup(void); void s3_resume_vga(void); +int getRomPriority(u64 *sources, struct rom_header *rom, int instance); extern int ScreenAndDebug; // pcibios.c -- 2.17.1

2 8

[ANNOUNCE] SeaBIOS 1.13.0
by Kevin O'Connor 09 Dec '19

09 Dec '19

The 1.13.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups For information on obtaining SeaBIOS, please see: http://seabios.org/Download ===== git shortlog -n rel-1.12.0..rel-1.13.0 ===== Gerd Hoffmann (25): vga: move modelist from bochsvga.c to new svgamodes.c vga: make memcpy_high() public vga: add atiext driver vga: add ati bios tables vbe: add edid support. ati: add edid support. bochsvga: add edid support. bochsdisplay: add edid support. bochsdisplay: parse resolution from edid. add get_keystroke_full() helper bootmenu: add support for more than 9 entries optionrom: disallow int19 redirect for pnp roms. ati-vga: make less verbose ati-vga: fix ati_read() ati-vga: make i2c register and bits configurable ati-vga: try vga ddc first ati-vga: add rage128 edid support bochsdisplay: add copyright and license to bochsdisplay.c ramfb: add copyright and license to ramfb.c cp437: add license to cp437.c ahci: zero-initialize port struct Revert "geometry: Apply LCHS values for boot devices" Revert "config: Add toggle for bootdevice information" Revert "geometry: Add boot_lchs_find_*() utility functions" Revert "geometry: Read LCHS from fw_cfg" Kevin O'Connor (11): output: Avoid thunking to 16bit mode in printf() if no vgabios docs: Update mailing list archive links docs: Fix cut-and-paste error in Mailinglist.md archive link usb-ehci: Clear pipe token on pipe reallocate pciinit: Use %pP shorthand for printing device ids in intel_igd_setup() virtio-pci: Use %pP format in dprintf() calls Makefile: Build with -Wno-address-of-packed-member svgamodes: Add copyright notice to vgasrc/svgamodes.c docs: Add developer-certificate-of-origin docs: Note release date for v1.12.1 docs: Note v1.13.0 release Sam Eiderman (10): smbios: Add missing zero byte to Type 0 geometry: Read LCHS from fw_cfg boot: Reorder functions in boot.c geometry: Add boot_lchs_find_*() utility functions config: Add toggle for bootdevice information geometry: Apply LCHS values for boot devices geometry: Read LCHS from fw_cfg boot: Build ata and scsi paths in function geometry: Add boot_lchs_find_*() utility functions geometry: Apply LCHS values for boot devices Stefan Berger (4): tcgbios: Use table to convert hash to buffer size tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks tpm: Require a response to have minimum size of a valid response header tcgbios: Check for enough bytes returned from TPM2_GetCapability Uwe Kleine-König (3): cbvga: reuse svga modes definitions from svgamodes.c Add additional resolutions for 16:9 displays: 1600x900 and 2560x1440 Remove dos line endings introduced in the last two commits David Woodhouse (2): csm: Sanitise alignment constraint in Legacy16GetTableAddress csm: Fix boot priority translation Denis Plotnikov (1): virtio: extend virtio queue size to 256 Joseph Pacheco-Corwin (1): bootsplash: Added support for 16/24/32bpp in one function Liran Alon (1): pvscsi: ring_desc do not have to be page aligned Stefano Garzarella (1): qemu: avoid debug prints if debugcon is not enabled Stephen Douthit (1): tpm: Check for TPM related ACPI tables before attempting hw probe

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

SeaBIOS